sh: Definitions for 3-level page table layout
If using 64-bit PTEs and 4K pages then each page table has 512 entries
(as opposed to 1024 entries with 32-bit PTEs). Unlike MIPS, SH follows
the convention that all structures in the page table (pgd_t, pmd_t,
pgprot_t, etc) must be the same size. Therefore, 64-bit PTEs require
64-bit PGD entries, etc. Using 2-levels of page tables and 64-bit PTEs
it is only possible to map 1GB of virtual address space.
In order to map all 4GB of virtual address space we need to adopt a
3-level page table layout. This actually works out better for
CONFIG_SUPERH32 because we only waste 2 PGD entries on the P1 and P2
areas (which are untranslated) instead of 256.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 0e7ba8e..b3f6c1a 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -190,19 +190,37 @@
depends on MEMORY_HOTPLUG
choice
+ prompt "Page table layout"
+ default PGTABLE_LEVELS_3 if X2TLB
+ default PGTABLE_LEVELS_2
+
+config PGTABLE_LEVELS_2
+ bool "2 Levels"
+ help
+ This is the default page table layout for all SuperH CPUs.
+
+config PGTABLE_LEVELS_3
+ bool "3 Levels"
+ depends on X2TLB
+ help
+ This enables a 3 level page table structure.
+
+endchoice
+
+choice
prompt "Kernel page size"
default PAGE_SIZE_8KB if X2TLB
default PAGE_SIZE_4KB
config PAGE_SIZE_4KB
bool "4kB"
- depends on !MMU || !X2TLB
+ depends on !MMU || !X2TLB || PGTABLE_LEVELS_3
help
This is the default page size used by all SuperH CPUs.
config PAGE_SIZE_8KB
bool "8kB"
- depends on !MMU || X2TLB
+ depends on !MMU || X2TLB && !PGTABLE_LEVELS_3
help
This enables 8kB pages as supported by SH-X2 and later MMUs.
@@ -214,7 +232,7 @@
config PAGE_SIZE_64KB
bool "64kB"
- depends on !MMU || CPU_SH4 || CPU_SH5
+ depends on !MMU || CPU_SH4 && !PGTABLE_LEVELS_3 || CPU_SH5
help
This enables support for 64kB pages, possible on all SH-4
CPUs and later.