commit 64f495323c9a902b3e59fe0a588585102bb3b13e
author Kyle McMartin <kyle@parisc-linux.org> Sat Apr 22 00:48:22 2006 -0600
committer Kyle McMartin <kyle@hera.kernel.org> Tue Jun 27 23:28:32 2006 +0000
tree 202d6c0105b0348aadfa8761e7c3cf27a5e98db9
parent f36f44de721db44b4c2944133c3c5c2e06f633f0

[PARISC] Ensure all ldcw uses are ldcw,co on pa2.0

ldcw,co should always be used on pa2.0, otherwise the strict cache
width alignment requirement is not relaxed.

Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>

arch/parisc/kernel/entry.S

diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S
index d9e53cf..630730c 100644
--- a/arch/parisc/kernel/entry.S
+++ b/arch/parisc/kernel/entry.S
@@ -1638,7 +1638,7 @@
 	load32		PA(pa_dbit_lock),t0
 
 dbit_spin_20w:
-	ldcw            0(t0),t1
+	LDCW		0(t0),t1
 	cmpib,=         0,t1,dbit_spin_20w
 	nop
 
@@ -1674,7 +1674,7 @@
 	load32		PA(pa_dbit_lock),t0
 
 dbit_spin_11:
-	ldcw            0(t0),t1
+	LDCW		0(t0),t1
 	cmpib,=         0,t1,dbit_spin_11
 	nop
 
@@ -1714,7 +1714,7 @@
 	load32		PA(pa_dbit_lock),t0
 
 dbit_spin_20:
-	ldcw            0(t0),t1
+	LDCW		0(t0),t1
 	cmpib,=         0,t1,dbit_spin_20
 	nop
 

arch/parisc/kernel/syscall.S

diff --git a/arch/parisc/kernel/syscall.S b/arch/parisc/kernel/syscall.S
index 479d9a0..a028c99 100644
--- a/arch/parisc/kernel/syscall.S
+++ b/arch/parisc/kernel/syscall.S
@@ -541,7 +541,7 @@
 # endif
 /* ENABLE_LWS_DEBUG */
 
-	ldcw	0(%sr2,%r20), %r28			/* Try to acquire the lock */
+	LDCW	0(%sr2,%r20), %r28			/* Try to acquire the lock */
 	cmpb,<>,n	%r0, %r28, cas_action		/* Did we get it? */
 cas_wouldblock:
 	ldo	2(%r0), %r28				/* 2nd case */