[PARISC] Ensure all ldcw uses are ldcw,co on pa2.0
ldcw,co should always be used on pa2.0, otherwise the strict cache
width alignment requirement is not relaxed.
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S
index d9e53cf..630730c 100644
--- a/arch/parisc/kernel/entry.S
+++ b/arch/parisc/kernel/entry.S
@@ -1638,7 +1638,7 @@
load32 PA(pa_dbit_lock),t0
dbit_spin_20w:
- ldcw 0(t0),t1
+ LDCW 0(t0),t1
cmpib,= 0,t1,dbit_spin_20w
nop
@@ -1674,7 +1674,7 @@
load32 PA(pa_dbit_lock),t0
dbit_spin_11:
- ldcw 0(t0),t1
+ LDCW 0(t0),t1
cmpib,= 0,t1,dbit_spin_11
nop
@@ -1714,7 +1714,7 @@
load32 PA(pa_dbit_lock),t0
dbit_spin_20:
- ldcw 0(t0),t1
+ LDCW 0(t0),t1
cmpib,= 0,t1,dbit_spin_20
nop