commit 7a74a4436b20980f8e19138e857bc7e39db5ad4b
author Stephen Warren <swarren@nvidia.com> Mon Sep 10 17:02:45 2012 -0600
committer Stephen Warren <swarren@nvidia.com> Tue Sep 11 10:05:55 2012 -0600
tree 6c82b601493c7622806a024da773c9e9fdcdd802
parent fa67ccb61d10fbd55d1c3b5b6b537e4d74da1e4b

ARM: tegra: fix overflow in tegra20_pll_clk_round_rate()

32-bit math isn't enough when e.g. *prate=12000000, and sel->n=1000.
Use 64-bit math to prevent this.

Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

arch/arm/mach-tegra/tegra20_clocks.c

diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
index b9124af..d9ce008 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -789,7 +789,7 @@
 	struct clk_tegra *c = to_clk_tegra(hw);
 	const struct clk_pll_freq_table *sel;
 	unsigned long input_rate = *prate;
-	unsigned long output_rate = *prate;
+	u64 output_rate = *prate;
 	int mul;
 	int div;