[MIPS] Implement clockevents for R4000-style cp0 count/compare interrupt
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/qemu/q-irq.c b/arch/mips/qemu/q-irq.c
index 89891e9..4681757 100644
--- a/arch/mips/qemu/q-irq.c
+++ b/arch/mips/qemu/q-irq.c
@@ -2,6 +2,7 @@
#include <linux/linkage.h>
#include <asm/i8259.h>
+#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/qemu.h>
#include <asm/system.h>
@@ -12,7 +13,7 @@
unsigned int pending = read_c0_status() & read_c0_cause();
if (pending & 0x8000) {
- ll_timer_interrupt(Q_COUNT_COMPARE_IRQ);
+ do_IRQ(Q_COUNT_COMPARE_IRQ);
return;
}
if (pending & 0x0400) {
@@ -29,6 +30,7 @@
{
mips_hpt_frequency = QEMU_C0_COUNTER_CLOCK; /* 100MHz */
+ mips_cpu_irq_init();
init_i8259_irqs();
set_c0_status(0x8400);
}
diff --git a/arch/mips/qemu/q-setup.c b/arch/mips/qemu/q-setup.c
index 8413943..89a2076 100644
--- a/arch/mips/qemu/q-setup.c
+++ b/arch/mips/qemu/q-setup.c
@@ -17,7 +17,6 @@
outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */
outb_p(LATCH & 0xff , 0x40); /* LSB */
outb(LATCH >> 8 , 0x40); /* MSB */
- setup_irq(0, irq);
}
void __init plat_mem_setup(void)