)]}'
{
  "commit": "802f192e4a600f7ef84ca25c8b818c8830acef5a",
  "tree": "51e9a6ed164e6a2d8741af510c3954ad79bf19af",
  "parents": [
    "0216f86dafb389c0ad97529fd45e64e883298cfd"
  ],
  "author": {
    "name": "Bob Picco",
    "email": "bob.picco@hp.com",
    "time": "Sat Sep 03 15:54:26 2005 -0700"
  },
  "committer": {
    "name": "Linus Torvalds",
    "email": "torvalds@evo.osdl.org",
    "time": "Mon Sep 05 00:05:38 2005 -0700"
  },
  "message": "[PATCH] SPARSEMEM EXTREME\n\nA new option for SPARSEMEM is ARCH_SPARSEMEM_EXTREME.  Architecture\nplatforms with a very sparse physical address space would likely want to\nselect this option.  For those architecture platforms that don\u0027t select the\noption, the code generated is equivalent to SPARSEMEM currently in -mm.\nI\u0027ll be posting a patch on ia64 ml which uses this new SPARSEMEM feature.\n\nARCH_SPARSEMEM_EXTREME makes mem_section a one dimensional array of\npointers to mem_sections.  This two level layout scheme is able to achieve\nsmaller memory requirements for SPARSEMEM with the tradeoff of an\nadditional shift and load when fetching the memory section.  The current\nSPARSEMEM -mm implementation is a one dimensional array of mem_sections\nwhich is the default SPARSEMEM configuration.  The patch attempts isolates\nthe implementation details of the physical layout of the sparsemem section\narray.\n\nARCH_SPARSEMEM_EXTREME depends on 64BIT and is by default boolean false.\n\nI\u0027ve boot tested under aim load ia64 configured for ARCH_SPARSEMEM_EXTREME.\n I\u0027ve also boot tested a 4 way Opteron machine with !ARCH_SPARSEMEM_EXTREME\nand tested with aim.\n\nSigned-off-by: Andy Whitcroft \u003capw@shadowen.org\u003e\nSigned-off-by: Bob Picco \u003cbob.picco@hp.com\u003e\nSigned-off-by: Dave Hansen \u003chaveblue@us.ibm.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n",
  "tree_diff": [
    {
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      "old_mode": 33188,
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      "type": "modify",
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}