)]}'
{
  "commit": "84fdde5af1eca5ff170d1dff7e2681b0a50a9ecb",
  "tree": "950f8b4208a76503f3149fc711baedd7b167d068",
  "parents": [
    "cd6eed3718b1b32c60a6ee5658ae6341de3177d9"
  ],
  "author": {
    "name": "Paul Mackerras",
    "email": "paulus@samba.org",
    "time": "Wed Oct 03 14:41:15 2007 +1000"
  },
  "committer": {
    "name": "Paul Mackerras",
    "email": "paulus@samba.org",
    "time": "Tue Oct 09 21:00:48 2007 +1000"
  },
  "message": "[POWERPC] Use cache-inhibited large page bit from firmware\n\nDiscussions with firmware architects have confirmed that the bit in\nthe ibm,pa-features property that indicates support for\ncache-inhibited large (\u003e\u003d 64kB) page mappings does in fact mean that\nthe hypervisor allows 64kB mappings to I/O devices.\n\nThus we can now enable the code that tests that bit and sets our\nCPU_FTR_CI_LARGE_PAGE feature bit.\n\nSigned-off-by: Paul Mackerras \u003cpaulus@samba.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "172dcc3849a0f9ad32bc5838c3a847a4e6c6420a",
      "old_mode": 33188,
      "old_path": "arch/powerpc/kernel/prom.c",
      "new_id": "9f329a8928eaed27f3192e27c729e24bb73ac888",
      "new_mode": 33188,
      "new_path": "arch/powerpc/kernel/prom.c"
    }
  ]
}