[PATCH] mips: clean up 32/64-bit configuration
Start cleaning 32-bit vs. 64-bit configuration.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index a0230ee..d330358 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -13,8 +13,8 @@
ifdef CONFIG_MODULES
obj-y += mips_ksyms.o module.o
-obj-$(CONFIG_MIPS32) += module-elf32.o
-obj-$(CONFIG_MIPS64) += module-elf64.o
+obj-$(CONFIG_32BIT) += module-elf32.o
+obj-$(CONFIG_64BIT) += module-elf64.o
endif
obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o
@@ -45,8 +45,8 @@
obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o
obj-$(CONFIG_IRQ_MV64340) += irq-mv6434x.o
-obj-$(CONFIG_MIPS32) += scall32-o32.o
-obj-$(CONFIG_MIPS64) += scall64-64.o
+obj-$(CONFIG_32BIT) += scall32-o32.o
+obj-$(CONFIG_64BIT) += scall64-64.o
obj-$(CONFIG_BINFMT_IRIX) += binfmt_irix.o
obj-$(CONFIG_MIPS32_COMPAT) += ioctl32.o linux32.o signal32.o
obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall64-n32.o signal_n32.o
@@ -55,7 +55,7 @@
obj-$(CONFIG_KGDB) += gdb-low.o gdb-stub.o
obj-$(CONFIG_PROC_FS) += proc.o
-obj-$(CONFIG_MIPS64) += cpu-bugs64.o
+obj-$(CONFIG_64BIT) += cpu-bugs64.o
obj-$(CONFIG_GEN_RTC) += genrtc.o
diff --git a/arch/mips/kernel/gdb-low.S b/arch/mips/kernel/gdb-low.S
index ece6dda..512bedb 100644
--- a/arch/mips/kernel/gdb-low.S
+++ b/arch/mips/kernel/gdb-low.S
@@ -13,13 +13,13 @@
#include <asm/stackframe.h>
#include <asm/gdb-stub.h>
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
#define DMFC0 mfc0
#define DMTC0 mtc0
#define LDC1 lwc1
#define SDC1 lwc1
#endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
#define DMFC0 dmfc0
#define DMTC0 dmtc0
#define LDC1 ldc1
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index a5b0a38..3a1a3e7 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -54,7 +54,7 @@
#endif
mfc0 k1, CP0_CAUSE
andi k1, k1, 0x7c
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
dsll k1, k1, 1
#endif
PTR_L k0, exception_handlers(k1)
@@ -81,7 +81,7 @@
beq k1, k0, handle_vced
li k0, 14<<2
beq k1, k0, handle_vcei
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
dsll k1, k1, 1
#endif
.set pop
@@ -244,10 +244,10 @@
start with an n and gas will believe \n is ok ... */
.macro __BUILD_verbose nexception
LONG_L a1, PT_EPC(sp)
-#if CONFIG_MIPS32
+#if CONFIG_32BIT
PRINT("Got \nexception at %08lx\012")
#endif
-#if CONFIG_MIPS64
+#if CONFIG_64BIT
PRINT("Got \nexception at %016lx\012")
#endif
.endm
@@ -293,7 +293,7 @@
BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
BUILD_HANDLER reserved reserved sti verbose /* others */
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
/* A temporary overflow handler used by check_daddi(). */
__INIT
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index a64e87d..2a1b45d 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -107,7 +107,7 @@
.endm
.macro setup_c0_status_pri
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
setup_c0_status ST0_KX 0
#else
setup_c0_status 0 0
@@ -115,7 +115,7 @@
.endm
.macro setup_c0_status_sec
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
setup_c0_status ST0_KX ST0_BEV
#else
setup_c0_status 0 ST0_BEV
@@ -215,7 +215,7 @@
* slightly different layout ...
*/
page swapper_pg_dir, _PGD_ORDER
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
page invalid_pmd_table, _PMD_ORDER
#endif
page invalid_pte_table, _PTE_ORDER
diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c
index eed29fc..86e42c6 100644
--- a/arch/mips/kernel/mips_ksyms.c
+++ b/arch/mips/kernel/mips_ksyms.c
@@ -35,7 +35,7 @@
EXPORT_SYMBOL(memmove);
EXPORT_SYMBOL(strcat);
EXPORT_SYMBOL(strchr);
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
EXPORT_SYMBOL(strncmp);
#endif
EXPORT_SYMBOL(strlen);
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 6e70c42..e4f2f80 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -70,7 +70,7 @@
/* New thread loses kernel privileges. */
status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|KU_MASK);
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
status &= ~ST0_FR;
status |= (current->thread.mflags & MF_32BIT_REGS) ? 0 : ST0_FR;
#endif
@@ -236,10 +236,10 @@
break;
if (
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
ip->i_format.opcode == sw_op &&
#endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
ip->i_format.opcode == sd_op &&
#endif
ip->i_format.rs == 29)
@@ -353,7 +353,7 @@
out:
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
if (current->thread.mflags & MF_32BIT_REGS) /* Kludge for 32-bit ps */
pc &= 0xffffffffUL;
#endif
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 92e70ca..0b571a5 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -124,7 +124,7 @@
if (tsk_used_math(child)) {
fpureg_t *fregs = get_fpu_regs(child);
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
/*
* The odd registers are actually the high
* order bits of the values stored in the even
@@ -135,7 +135,7 @@
else
tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff);
#endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
tmp = fregs[addr - FPR_BASE];
#endif
} else {
@@ -213,7 +213,7 @@
sizeof(child->thread.fpu.hard));
child->thread.fpu.hard.fcr31 = 0;
}
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
/*
* The odd registers are actually the high order bits
* of the values stored in the even registers - unless
@@ -227,7 +227,7 @@
fregs[addr - FPR_BASE] |= data;
}
#endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
fregs[addr - FPR_BASE] = data;
#endif
break;
@@ -304,14 +304,14 @@
static inline int audit_arch(void)
{
#ifdef CONFIG_CPU_LITTLE_ENDIAN
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
if (!(current->thread.mflags & MF_32BIT_REGS))
return AUDIT_ARCH_MIPSEL64;
#endif /* MIPS64 */
return AUDIT_ARCH_MIPSEL;
#else /* big endian... */
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
if (!(current->thread.mflags & MF_32BIT_REGS))
return AUDIT_ARCH_MIPS64;
#endif /* MIPS64 */
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index ebb643d..aba665b 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -36,7 +36,7 @@
LEAF(_save_fp_context)
cfc1 t1, fcr31
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
/* Store the 16 odd double precision registers */
EX sdc1 $f1, SC_FPREGS+8(a0)
EX sdc1 $f3, SC_FPREGS+24(a0)
@@ -118,7 +118,7 @@
*/
LEAF(_restore_fp_context)
EX lw t0, SC_FPC_CSR(a0)
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
EX ldc1 $f1, SC_FPREGS+8(a0)
EX ldc1 $f3, SC_FPREGS+24(a0)
EX ldc1 $f5, SC_FPREGS+40(a0)
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 1fc3b2e..175dd1f 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -105,7 +105,7 @@
* Save a thread's fp context.
*/
LEAF(_save_fp)
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
mfc0 t1, CP0_STATUS
#endif
fpu_save_double a0 t1 t0 t2 # clobbers t1
@@ -142,7 +142,7 @@
li t1, -1 # SNaN
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
sll t0, t0, 5
bgez t0, 1f # 16 / 32 register mode?
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 3a240e3..12b531c 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -241,7 +241,7 @@
if (*tmp)
strcat(command_line, tmp);
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
/* HACK: Guess if the sign extension was forgotten */
if (start > 0x0000000080000000 && start < 0x00000000ffffffff)
start |= 0xffffffff00000000;
@@ -446,7 +446,7 @@
{
int i;
-#if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64)
+#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
/*
* The 64bit code in 32bit object format trick can't represent
* 64bit wide relocations for linker script symbols.
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 56c36e4..a53b1ed 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -924,7 +924,7 @@
* flag that some firmware may have left set and the TS bit (for
* IP27). Set XX for ISA IV code to work.
*/
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
#endif
if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 3f24a1d..36c5212 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -240,7 +240,7 @@
break;
case lwu_op:
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
/*
* A 32-bit kernel might be running on a 64-bit processor. But
* if we're on a 32-bit processor and an i-cache incoherency
@@ -278,13 +278,13 @@
*newvalue = value;
*regptr = ®s->regs[insn.i_format.rt];
break;
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
/* Cannot handle 64-bit instructions in 32-bit kernel */
goto sigill;
case ld_op:
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
/*
* A 32-bit kernel might be running on a 64-bit processor. But
* if we're on a 32-bit processor and an i-cache incoherency
@@ -320,7 +320,7 @@
*newvalue = value;
*regptr = ®s->regs[insn.i_format.rt];
break;
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
/* Cannot handle 64-bit instructions in 32-bit kernel */
goto sigill;
@@ -392,7 +392,7 @@
break;
case sd_op:
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
/*
* A 32-bit kernel might be running on a 64-bit processor. But
* if we're on a 32-bit processor and an i-cache incoherency
@@ -428,7 +428,7 @@
if (res)
goto fault;
break;
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
/* Cannot handle 64-bit instructions in 32-bit kernel */
goto sigill;