[PATCH] CRIS update: SMP
Patches to support SMP.
* Each CPU has its own current_pgd.
* flush_tlb_range is implemented as flush_tlb_mm.
* Atomic operations implemented with spinlocks.
* Semaphores implemented with spinlocks.
Signed-off-by: Mikael Starvik <starvik@axis.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
diff --git a/arch/cris/arch-v10/mm/fault.c b/arch/cris/arch-v10/mm/fault.c
index 6805cdb..fe26150 100644
--- a/arch/cris/arch-v10/mm/fault.c
+++ b/arch/cris/arch-v10/mm/fault.c
@@ -14,6 +14,7 @@
#include <asm/uaccess.h>
#include <asm/pgtable.h>
#include <asm/arch/svinto.h>
+#include <asm/mmu_context.h>
/* debug of low-level TLB reload */
#undef DEBUG
@@ -24,8 +25,6 @@
#define D(x)
#endif
-extern volatile pgd_t *current_pgd;
-
extern const struct exception_table_entry
*search_exception_tables(unsigned long addr);
@@ -46,7 +45,7 @@
int page_id;
int acc, inv;
#endif
- pgd_t* pgd = (pgd_t*)current_pgd;
+ pgd_t* pgd = (pgd_t*)per_cpu(current_pgd, smp_processor_id());
pmd_t *pmd;
pte_t pte;
int miss, we, writeac;
@@ -94,24 +93,3 @@
*R_TLB_LO = pte_val(pte);
local_irq_restore(flags);
}
-
-/* Called from arch/cris/mm/fault.c to find fixup code. */
-int
-find_fixup_code(struct pt_regs *regs)
-{
- const struct exception_table_entry *fixup;
-
- if ((fixup = search_exception_tables(regs->irp)) != 0) {
- /* Adjust the instruction pointer in the stackframe. */
- regs->irp = fixup->fixup;
-
- /*
- * Don't return by restoring the CPU state, so switch
- * frame-type.
- */
- regs->frametype = CRIS_FRAME_NORMAL;
- return 1;
- }
-
- return 0;
-}