[PARISC] Properly specify index field to I/D cache flush ops
replace use of "0" with "%r0" since PA 1.1 I/D flush ops only take a
general register and not an immediate value for the index field.
This just forces the code to always be PA 1.1 "clean".
From: Joel Soete <soete.joel@tiscali.be>
Signed-off-by: Grant Grundler <grundler@parisc-linux.org>
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
diff --git a/arch/parisc/kernel/signal.c b/arch/parisc/kernel/signal.c
index befdfe7..82c24e6 100644
--- a/arch/parisc/kernel/signal.c
+++ b/arch/parisc/kernel/signal.c
@@ -625,11 +625,14 @@
put_user(0xe0008200, &usp[3]);
put_user(0x34140000, &usp[4]);
- /* Stack is 64-byte aligned, and we only
- * need to flush 1 cache line */
- asm("fdc 0(%%sr3, %0)\n"
+ /* Stack is 64-byte aligned, and we only need
+ * to flush 1 cache line.
+ * Flushing one cacheline is cheap.
+ * "sync" on bigger (> 4 way) boxes is not.
+ */
+ asm("fdc %%r0(%%sr3, %0)\n"
"sync\n"
- "fic 0(%%sr3, %0)\n"
+ "fic %%r0(%%sr3, %0)\n"
"sync\n"
: : "r"(regs->gr[30]));