[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
This just leaves include/asm-arm/plat-* to deal with.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
diff --git a/arch/arm/mach-lh7a40x/arch-kev7a400.c b/arch/arm/mach-lh7a40x/arch-kev7a400.c
index c794ca7..551b972 100644
--- a/arch/arm/mach-lh7a40x/arch-kev7a400.c
+++ b/arch/arm/mach-lh7a40x/arch-kev7a400.c
@@ -13,7 +13,7 @@
#include <linux/device.h>
#include <linux/interrupt.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
index ff3109a..e373fb8 100644
--- a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
+++ b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
@@ -14,7 +14,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-lh7a40x/clcd.c b/arch/arm/mach-lh7a40x/clcd.c
index 395ad9b..a2a5432 100644
--- a/arch/arm/mach-lh7a40x/clcd.c
+++ b/arch/arm/mach-lh7a40x/clcd.c
@@ -23,7 +23,7 @@
#include <asm/mach/irq.h>
#include <asm/system.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
diff --git a/arch/arm/mach-lh7a40x/clocks.c b/arch/arm/mach-lh7a40x/clocks.c
index 9fe7f3a..4fb23ac 100644
--- a/arch/arm/mach-lh7a40x/clocks.c
+++ b/arch/arm/mach-lh7a40x/clocks.c
@@ -9,8 +9,8 @@
*/
#include <linux/cpufreq.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clocks.h>
+#include <mach/hardware.h>
+#include <mach/clocks.h>
#include <linux/err.h>
struct module;
diff --git a/arch/arm/mach-lh7a40x/include/mach/clocks.h b/arch/arm/mach-lh7a40x/include/mach/clocks.h
new file mode 100644
index 0000000..fe2e025
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/clocks.h
@@ -0,0 +1,18 @@
+/* arch/arm/mach-lh7a40x/include/mach/clocks.h
+ *
+ * Copyright (C) 2004 Marc Singer
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_CLOCKS_H
+#define __ASM_ARCH_CLOCKS_H
+
+unsigned int fclkfreq_get (void);
+unsigned int hclkfreq_get (void);
+unsigned int pclkfreq_get (void);
+
+#endif /* _ASM_ARCH_CLOCKS_H */
diff --git a/arch/arm/mach-lh7a40x/include/mach/constants.h b/arch/arm/mach-lh7a40x/include/mach/constants.h
new file mode 100644
index 0000000..55c6edb
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/constants.h
@@ -0,0 +1,91 @@
+/* arch/arm/mach-lh7a40x/include/mach/constants.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ * Copyright (C) 2004 Logic Product Development
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_CONSTANTS_H
+#define __ASM_ARCH_CONSTANTS_H
+
+
+/* Addressing constants */
+
+ /* SoC CPU IO addressing */
+#define IO_PHYS (0x80000000)
+#define IO_VIRT (0xf8000000)
+#define IO_SIZE (0x0000B000)
+
+#ifdef CONFIG_MACH_KEV7A400
+# define CPLD_PHYS (0x20000000)
+# define CPLD_VIRT (0xf2000000)
+# define CPLD_SIZE PAGE_SIZE
+#endif
+
+#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
+
+# define IOBARRIER_PHYS 0x10000000 /* Second bank, fastest timing */
+# define IOBARRIER_VIRT 0xf0000000
+# define IOBARRIER_SIZE PAGE_SIZE
+
+# define CF_PHYS 0x60200000
+# define CF_VIRT 0xf6020000
+# define CF_SIZE (8*1024)
+
+ /* The IO mappings for the LPD CPLD are, unfortunately, sparse. */
+# define CPLDX_PHYS(x) (0x70000000 | ((x) << 20))
+# define CPLDX_VIRT(x) (0xf7000000 | ((x) << 16))
+# define CPLD00_PHYS CPLDX_PHYS (0x00) /* Wired LAN */
+# define CPLD00_VIRT CPLDX_VIRT (0x00)
+# define CPLD00_SIZE PAGE_SIZE
+# define CPLD02_PHYS CPLDX_PHYS (0x02)
+# define CPLD02_VIRT CPLDX_VIRT (0x02)
+# define CPLD02_SIZE PAGE_SIZE
+# define CPLD06_PHYS CPLDX_PHYS (0x06)
+# define CPLD06_VIRT CPLDX_VIRT (0x06)
+# define CPLD06_SIZE PAGE_SIZE
+# define CPLD08_PHYS CPLDX_PHYS (0x08)
+# define CPLD08_VIRT CPLDX_VIRT (0x08)
+# define CPLD08_SIZE PAGE_SIZE
+# define CPLD0A_PHYS CPLDX_PHYS (0x0a)
+# define CPLD0A_VIRT CPLDX_VIRT (0x0a)
+# define CPLD0A_SIZE PAGE_SIZE
+# define CPLD0C_PHYS CPLDX_PHYS (0x0c)
+# define CPLD0C_VIRT CPLDX_VIRT (0x0c)
+# define CPLD0C_SIZE PAGE_SIZE
+# define CPLD0E_PHYS CPLDX_PHYS (0x0e)
+# define CPLD0E_VIRT CPLDX_VIRT (0x0e)
+# define CPLD0E_SIZE PAGE_SIZE
+# define CPLD10_PHYS CPLDX_PHYS (0x10)
+# define CPLD10_VIRT CPLDX_VIRT (0x10)
+# define CPLD10_SIZE PAGE_SIZE
+# define CPLD12_PHYS CPLDX_PHYS (0x12)
+# define CPLD12_VIRT CPLDX_VIRT (0x12)
+# define CPLD12_SIZE PAGE_SIZE
+# define CPLD14_PHYS CPLDX_PHYS (0x14)
+# define CPLD14_VIRT CPLDX_VIRT (0x14)
+# define CPLD14_SIZE PAGE_SIZE
+# define CPLD16_PHYS CPLDX_PHYS (0x16)
+# define CPLD16_VIRT CPLDX_VIRT (0x16)
+# define CPLD16_SIZE PAGE_SIZE
+# define CPLD18_PHYS CPLDX_PHYS (0x18)
+# define CPLD18_VIRT CPLDX_VIRT (0x18)
+# define CPLD18_SIZE PAGE_SIZE
+# define CPLD1A_PHYS CPLDX_PHYS (0x1a)
+# define CPLD1A_VIRT CPLDX_VIRT (0x1a)
+# define CPLD1A_SIZE PAGE_SIZE
+#endif
+
+ /* Timing constants */
+
+#define XTAL_IN 14745600 /* 14.7456 MHz crystal */
+#define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */
+#define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */
+#define HCLK (99993600)
+//#define HCLK (119808000)
+
+#endif /* __ASM_ARCH_CONSTANTS_H */
diff --git a/arch/arm/mach-lh7a40x/include/mach/debug-macro.S b/arch/arm/mach-lh7a40x/include/mach/debug-macro.S
new file mode 100644
index 0000000..85141ed
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/debug-macro.S
@@ -0,0 +1,39 @@
+/* arch/arm/mach-lh7a40x/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+ @ It is not known if this will be appropriate for every 40x
+ @ board.
+
+ .macro addruart,rx
+ mrc p15, 0, \rx, c1, c0
+ tst \rx, #1 @ MMU enabled?
+ mov \rx, #0x00000700 @ offset from base
+ orreq \rx, \rx, #0x80000000 @ physical base
+ orrne \rx, \rx, #0xf8000000 @ virtual base
+ .endm
+
+ .macro senduart,rd,rx
+ strb \rd, [\rx] @ DATA
+ .endm
+
+ .macro busyuart,rd,rx @ spin while busy
+1001: ldr \rd, [\rx, #0x10] @ STATUS
+ tst \rd, #1 << 3 @ BUSY (TX FIFO not empty)
+ bne 1001b @ yes, spin
+ .endm
+
+ .macro waituart,rd,rx @ wait for Tx FIFO room
+1001: ldrb \rd, [\rx, #0x10] @ STATUS
+ tst \rd, #1 << 5 @ TXFF (TX FIFO full)
+ bne 1001b @ yes, spin
+ .endm
diff --git a/arch/arm/mach-lh7a40x/include/mach/dma.h b/arch/arm/mach-lh7a40x/include/mach/dma.h
new file mode 100644
index 0000000..baa3f8d
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/dma.h
@@ -0,0 +1,86 @@
+/* arch/arm/mach-lh7a40x/include/mach/dma.h
+ *
+ * Copyright (C) 2005 Marc Singer
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+typedef enum {
+ DMA_M2M0 = 0,
+ DMA_M2M1 = 1,
+ DMA_M2P0 = 2, /* Tx */
+ DMA_M2P1 = 3, /* Rx */
+ DMA_M2P2 = 4, /* Tx */
+ DMA_M2P3 = 5, /* Rx */
+ DMA_M2P4 = 6, /* Tx - AC97 */
+ DMA_M2P5 = 7, /* Rx - AC97 */
+ DMA_M2P6 = 8, /* Tx */
+ DMA_M2P7 = 9, /* Rx */
+} dma_device_t;
+
+#define DMA_LENGTH_MAX ((64*1024) - 4) /* bytes */
+
+#define DMAC_GCA __REG(DMAC_PHYS + 0x2b80)
+#define DMAC_GIR __REG(DMAC_PHYS + 0x2bc0)
+
+#define DMAC_GIR_MMI1 (1<<11)
+#define DMAC_GIR_MMI0 (1<<10)
+#define DMAC_GIR_MPI8 (1<<9)
+#define DMAC_GIR_MPI9 (1<<8)
+#define DMAC_GIR_MPI6 (1<<7)
+#define DMAC_GIR_MPI7 (1<<6)
+#define DMAC_GIR_MPI4 (1<<5)
+#define DMAC_GIR_MPI5 (1<<4)
+#define DMAC_GIR_MPI2 (1<<3)
+#define DMAC_GIR_MPI3 (1<<2)
+#define DMAC_GIR_MPI0 (1<<1)
+#define DMAC_GIR_MPI1 (1<<0)
+
+#define DMAC_M2P0 0x0000
+#define DMAC_M2P1 0x0040
+#define DMAC_M2P2 0x0080
+#define DMAC_M2P3 0x00c0
+#define DMAC_M2P4 0x0240
+#define DMAC_M2P5 0x0200
+#define DMAC_M2P6 0x02c0
+#define DMAC_M2P7 0x0280
+#define DMAC_M2P8 0x0340
+#define DMAC_M2P9 0x0300
+#define DMAC_M2M0 0x0100
+#define DMAC_M2M1 0x0140
+
+#define DMAC_P_PCONTROL(c) __REG(DMAC_PHYS + (c) + 0x00)
+#define DMAC_P_PINTERRUPT(c) __REG(DMAC_PHYS + (c) + 0x04)
+#define DMAC_P_PPALLOC(c) __REG(DMAC_PHYS + (c) + 0x08)
+#define DMAC_P_PSTATUS(c) __REG(DMAC_PHYS + (c) + 0x0c)
+#define DMAC_P_REMAIN(c) __REG(DMAC_PHYS + (c) + 0x14)
+#define DMAC_P_MAXCNT0(c) __REG(DMAC_PHYS + (c) + 0x20)
+#define DMAC_P_BASE0(c) __REG(DMAC_PHYS + (c) + 0x24)
+#define DMAC_P_CURRENT0(c) __REG(DMAC_PHYS + (c) + 0x28)
+#define DMAC_P_MAXCNT1(c) __REG(DMAC_PHYS + (c) + 0x30)
+#define DMAC_P_BASE1(c) __REG(DMAC_PHYS + (c) + 0x34)
+#define DMAC_P_CURRENT1(c) __REG(DMAC_PHYS + (c) + 0x38)
+
+#define DMAC_PCONTROL_ENABLE (1<<4)
+
+#define DMAC_PORT_USB 0
+#define DMAC_PORT_SDMMC 1
+#define DMAC_PORT_AC97_1 2
+#define DMAC_PORT_AC97_2 3
+#define DMAC_PORT_AC97_3 4
+#define DMAC_PORT_UART1 6
+#define DMAC_PORT_UART2 7
+#define DMAC_PORT_UART3 8
+
+#define DMAC_PSTATUS_CURRSTATE_SHIFT 4
+#define DMAC_PSTATUS_CURRSTATE_MASK 0x3
+
+#define DMAC_PSTATUS_NEXTBUF (1<<6)
+#define DMAC_PSTATUS_STALLRINT (1<<0)
+
+#define DMAC_INT_CHE (1<<3)
+#define DMAC_INT_NFB (1<<1)
+#define DMAC_INT_STALL (1<<0)
diff --git a/arch/arm/mach-lh7a40x/include/mach/entry-macro.S b/arch/arm/mach-lh7a40x/include/mach/entry-macro.S
new file mode 100644
index 0000000..069bb4c
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/entry-macro.S
@@ -0,0 +1,149 @@
+/*
+ * arch/arm/mach-lh7a40x/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for LH7A40x platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
+/* In order to allow there to be support for both of the processor
+ classes at the same time, we make a hack here that isn't very
+ pretty. At startup, the link pointed to with the
+ branch_irq_lh7a400 symbol is replaced with a NOP when the CPU is
+ detected as a lh7a404.
+
+ *** FIXME: we should clean this up so that there is only one
+ implementation for each CPU's design.
+
+*/
+
+#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
+
+ .macro disable_fiq
+ .endm
+
+ .macro get_irqnr_preamble, base, tmp
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+branch_irq_lh7a400: b 1000f
+
+@ Implementation of the LH7A404 get_irqnr_and_base.
+
+ mov \irqnr, #0 @ VIC1 irq base
+ mov \base, #io_p2v(0x80000000) @ APB registers
+ add \base, \base, #0x8000
+ ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR
+ tst \tmp, #VA_VECTORED @ Direct vectored
+ bne 1002f
+ tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1
+ ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS
+ bne 1001f
+ add \base, \base, #(0xa000 - 0x8000)
+ ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR
+ tst \tmp, #VA_VECTORED @ Direct vectored
+ bne 1002f
+ ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS
+ mov \irqnr, #32 @ VIC2 irq base
+
+1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
+ bcs 1008f @ Bit set; irq found
+ add \irqnr, \irqnr, #1
+ bne 1001b @ Until no bits
+ b 1009f @ Nothing? Hmm.
+1002: and \irqnr, \tmp, #0x3f @ Mask for valid bits
+1008: movs \irqstat, #1 @ Force !Z
+ str \tmp, [\base, #0x0030] @ Clear vector
+ b 1009f
+
+@ Implementation of the LH7A400 get_irqnr_and_base.
+
+1000: mov \irqnr, #0
+ mov \base, #io_p2v(0x80000000) @ APB registers
+ ldr \irqstat, [\base, #0x500] @ PIC INTSR
+
+1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
+ bcs 1008f @ Bit set; irq found
+ add \irqnr, \irqnr, #1
+ bne 1001b @ Until no bits
+ b 1009f @ Nothing? Hmm.
+1008: movs \irqstat, #1 @ Force !Z
+
+1009:
+ .endm
+
+
+
+#elif defined (CONFIG_ARCH_LH7A400)
+ .macro disable_fiq
+ .endm
+
+ .macro get_irqnr_preamble, base, tmp
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+ mov \irqnr, #0
+ mov \base, #io_p2v(0x80000000) @ APB registers
+ ldr \irqstat, [\base, #0x500] @ PIC INTSR
+
+1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
+ bcs 1008f @ Bit set; irq found
+ add \irqnr, \irqnr, #1
+ bne 1001b @ Until no bits
+ b 1009f @ Nothing? Hmm.
+1008: movs \irqstat, #1 @ Force !Z
+1009:
+ .endm
+
+#elif defined(CONFIG_ARCH_LH7A404)
+
+ .macro disable_fiq
+ .endm
+
+ .macro get_irqnr_preamble, base, tmp
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+ mov \irqnr, #0 @ VIC1 irq base
+ mov \base, #io_p2v(0x80000000) @ APB registers
+ add \base, \base, #0x8000
+ ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR
+ tst \tmp, #VA_VECTORED @ Direct vectored
+ bne 1002f
+ tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1
+ ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS
+ bne 1001f
+ add \base, \base, #(0xa000 - 0x8000)
+ ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR
+ tst \tmp, #VA_VECTORED @ Direct vectored
+ bne 1002f
+ ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS
+ mov \irqnr, #32 @ VIC2 irq base
+
+1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
+ bcs 1008f @ Bit set; irq found
+ add \irqnr, \irqnr, #1
+ bne 1001b @ Until no bits
+ b 1009f @ Nothing? Hmm.
+1002: and \irqnr, \tmp, #0x3f @ Mask for valid bits
+1008: movs \irqstat, #1 @ Force !Z
+ str \tmp, [\base, #0x0030] @ Clear vector
+1009:
+ .endm
+#endif
+
+
diff --git a/arch/arm/mach-lh7a40x/include/mach/hardware.h b/arch/arm/mach-lh7a40x/include/mach/hardware.h
new file mode 100644
index 0000000..48e827d
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/hardware.h
@@ -0,0 +1,62 @@
+/* arch/arm/mach-lh7a40x/include/mach/hardware.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ *
+ * [ Substantially cribbed from arch/arm/mach-pxa/include/mach/hardware.h ]
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h> /* Added for the sake of amba-clcd driver */
+
+#define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff))
+#define io_v2p(x) ( (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff))
+
+#ifdef __ASSEMBLY__
+
+# define __REG(x) io_p2v(x)
+# define __PREG(x) io_v2p(x)
+
+#else
+
+# if 0
+# define __REG(x) (*((volatile u32 *)io_p2v(x)))
+# else
+/*
+ * This __REG() version gives the same results as the one above, except
+ * that we are fooling gcc somehow so it generates far better and smaller
+ * assembly code for access to contigous registers. It's a shame that gcc
+ * doesn't guess this by itself.
+ */
+#include <asm/types.h>
+typedef struct { volatile u32 offset[4096]; } __regbase;
+# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
+# define __REG(x) __REGP(io_p2v(x))
+typedef struct { volatile u16 offset[4096]; } __regbase16;
+# define __REGP16(x) ((__regbase16 *)((x)&~4095))->offset[((x)&4095)>>1]
+# define __REG16(x) __REGP16(io_p2v(x))
+typedef struct { volatile u8 offset[4096]; } __regbase8;
+# define __REGP8(x) ((__regbase8 *)((x)&~4095))->offset[(x)&4095]
+# define __REG8(x) __REGP8(io_p2v(x))
+#endif
+
+/* Let's kick gcc's ass again... */
+# define __REG2(x,y) \
+ ( __builtin_constant_p(y) ? (__REG((x) + (y))) \
+ : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
+
+# define __PREG(x) (io_v2p((u32)&(x)))
+
+#endif
+
+#define MASK_AND_SET(v,m,s) (v) = ((v)&~(m))|(s)
+
+#include "registers.h"
+
+#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-lh7a40x/include/mach/io.h b/arch/arm/mach-lh7a40x/include/mach/io.h
new file mode 100644
index 0000000..031d26f
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/io.h
@@ -0,0 +1,22 @@
+/* arch/arm/mach-lh7a40x/include/mach/io.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/* No ISA or PCI bus on this machine. */
+#define __io(a) ((void __iomem *)(a))
+#define __mem_pci(a) (a)
+
+#endif /* __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-lh7a40x/include/mach/irqs.h b/arch/arm/mach-lh7a40x/include/mach/irqs.h
new file mode 100644
index 0000000..0f9b836
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/irqs.h
@@ -0,0 +1,200 @@
+/* arch/arm/mach-lh7a40x/include/mach/irqs.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ * Copyright (C) 2004 Logic Product Development
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+/* It is to be seen whether or not we can build a kernel for more than
+ * one board. For the time being, these macros assume that we cannot.
+ * Thus, it is OK to ifdef machine/board specific IRQ assignments.
+ */
+
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+
+#define FIQ_START 80
+
+#if defined (CONFIG_ARCH_LH7A400)
+
+ /* FIQs */
+
+# define IRQ_GPIO0FIQ 0 /* GPIO External FIQ Interrupt on F0 */
+# define IRQ_BLINT 1 /* Battery Low */
+# define IRQ_WEINT 2 /* Watchdog Timer, WDT overflow */
+# define IRQ_MCINT 3 /* Media Change, MEDCHG pin rising */
+
+ /* IRQs */
+
+# define IRQ_CSINT 4 /* Audio Codec (ACI) */
+# define IRQ_GPIO1INTR 5 /* GPIO External IRQ Interrupt on F1 */
+# define IRQ_GPIO2INTR 6 /* GPIO External IRQ Interrupt on F2 */
+# define IRQ_GPIO3INTR 7 /* GPIO External IRQ Interrupt on F3 */
+# define IRQ_T1UI 8 /* Timer 1 underflow */
+# define IRQ_T2UI 9 /* Timer 2 underflow */
+# define IRQ_RTCMI 10
+# define IRQ_TINTR 11 /* Clock State Controller 64 Hz tick (CSC) */
+# define IRQ_UART1INTR 12
+# define IRQ_UART2INTR 13
+# define IRQ_LCDINTR 14
+# define IRQ_SSIEOT 15 /* Synchronous Serial Interface (SSI) */
+# define IRQ_UART3INTR 16
+# define IRQ_SCIINTR 17 /* Smart Card Interface (SCI) */
+# define IRQ_AACINTR 18 /* Advanced Audio Codec (AAC) */
+# define IRQ_MMCINTR 19 /* Multimedia Card (MMC) */
+# define IRQ_USBINTR 20
+# define IRQ_DMAINTR 21
+# define IRQ_T3UI 22 /* Timer 3 underflow */
+# define IRQ_GPIO4INTR 23 /* GPIO External IRQ Interrupt on F4 */
+# define IRQ_GPIO5INTR 24 /* GPIO External IRQ Interrupt on F5 */
+# define IRQ_GPIO6INTR 25 /* GPIO External IRQ Interrupt on F6 */
+# define IRQ_GPIO7INTR 26 /* GPIO External IRQ Interrupt on F7 */
+# define IRQ_BMIINTR 27 /* Battery Monitor Interface (BMI) */
+
+# define NR_IRQ_CPU 28 /* IRQs directly recognized by CPU */
+
+ /* Given IRQ, return GPIO interrupt number 0-7 */
+# define IRQ_TO_GPIO(i) ((i) \
+ - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\
+ - (((i) > IRQ_GPIO0INTR) ? IRQ_GPIO1INTR - IRQ_GPIO0INTR - 1 : 0))
+
+#endif
+
+#if defined (CONFIG_ARCH_LH7A404)
+
+# define IRQ_BROWN 0 /* Brownout */
+# define IRQ_WDTINTR 1 /* Watchdog Timer */
+# define IRQ_COMMRX 2 /* ARM Comm Rx for Debug */
+# define IRQ_COMMTX 3 /* ARM Comm Tx for Debug */
+# define IRQ_T1UI 4 /* Timer 1 underflow */
+# define IRQ_T2UI 5 /* Timer 2 underflow */
+# define IRQ_CSINT 6 /* Codec Interrupt (shared by AAC on 404) */
+# define IRQ_DMAM2P0 7 /* -- DMA Memory to Peripheral */
+# define IRQ_DMAM2P1 8
+# define IRQ_DMAM2P2 9
+# define IRQ_DMAM2P3 10
+# define IRQ_DMAM2P4 11
+# define IRQ_DMAM2P5 12
+# define IRQ_DMAM2P6 13
+# define IRQ_DMAM2P7 14
+# define IRQ_DMAM2P8 15
+# define IRQ_DMAM2P9 16
+# define IRQ_DMAM2M0 17 /* -- DMA Memory to Memory */
+# define IRQ_DMAM2M1 18
+# define IRQ_GPIO0INTR 19 /* -- GPIOF Interrupt */
+# define IRQ_GPIO1INTR 20
+# define IRQ_GPIO2INTR 21
+# define IRQ_GPIO3INTR 22
+# define IRQ_SOFT_V1_23 23 /* -- Unassigned */
+# define IRQ_SOFT_V1_24 24
+# define IRQ_SOFT_V1_25 25
+# define IRQ_SOFT_V1_26 26
+# define IRQ_SOFT_V1_27 27
+# define IRQ_SOFT_V1_28 28
+# define IRQ_SOFT_V1_29 29
+# define IRQ_SOFT_V1_30 30
+# define IRQ_SOFT_V1_31 31
+
+# define IRQ_BLINT 32 /* Battery Low */
+# define IRQ_BMIINTR 33 /* Battery Monitor */
+# define IRQ_MCINTR 34 /* Media Change */
+# define IRQ_TINTR 35 /* 64Hz Tick */
+# define IRQ_WEINT 36 /* Watchdog Expired */
+# define IRQ_RTCMI 37 /* Real-time Clock Match */
+# define IRQ_UART1INTR 38 /* UART1 Interrupt (including error) */
+# define IRQ_UART1ERR 39 /* UART1 Error */
+# define IRQ_UART2INTR 40 /* UART2 Interrupt (including error) */
+# define IRQ_UART2ERR 41 /* UART2 Error */
+# define IRQ_UART3INTR 42 /* UART3 Interrupt (including error) */
+# define IRQ_UART3ERR 43 /* UART3 Error */
+# define IRQ_SCIINTR 44 /* Smart Card */
+# define IRQ_TSCINTR 45 /* Touchscreen */
+# define IRQ_KMIINTR 46 /* Keyboard/Mouse (PS/2) */
+# define IRQ_GPIO4INTR 47 /* -- GPIOF Interrupt */
+# define IRQ_GPIO5INTR 48
+# define IRQ_GPIO6INTR 49
+# define IRQ_GPIO7INTR 50
+# define IRQ_T3UI 51 /* Timer 3 underflow */
+# define IRQ_LCDINTR 52 /* LCD Controller */
+# define IRQ_SSPINTR 53 /* Synchronous Serial Port */
+# define IRQ_SDINTR 54 /* Secure Digital Port (MMC) */
+# define IRQ_USBINTR 55 /* USB Device Port */
+# define IRQ_USHINTR 56 /* USB Host Port */
+# define IRQ_SOFT_V2_25 57 /* -- Unassigned */
+# define IRQ_SOFT_V2_26 58
+# define IRQ_SOFT_V2_27 59
+# define IRQ_SOFT_V2_28 60
+# define IRQ_SOFT_V2_29 61
+# define IRQ_SOFT_V2_30 62
+# define IRQ_SOFT_V2_31 63
+
+# define NR_IRQ_CPU 64 /* IRQs directly recognized by CPU */
+
+ /* Given IRQ, return GPIO interrupt number 0-7 */
+# define IRQ_TO_GPIO(i) ((i) \
+ - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\
+ - IRQ_GPIO0INTR)
+
+ /* Vector Address constants */
+# define VA_VECTORED 0x100 /* Set for vectored interrupt */
+# define VA_VIC1DEFAULT 0x200 /* Set as default VECTADDR for VIC1 */
+# define VA_VIC2DEFAULT 0x400 /* Set as default VECTADDR for VIC2 */
+
+#endif
+
+ /* IRQ aliases */
+
+#if !defined (IRQ_GPIO0INTR)
+# define IRQ_GPIO0INTR IRQ_GPIO0FIQ
+#endif
+#define IRQ_TICK IRQ_TINTR
+#define IRQ_PCC1_RDY IRQ_GPIO6INTR /* PCCard 1 ready */
+#define IRQ_PCC2_RDY IRQ_GPIO7INTR /* PCCard 2 ready */
+#define IRQ_USB IRQ_USBINTR /* USB device */
+
+#ifdef CONFIG_MACH_KEV7A400
+# define IRQ_TS IRQ_GPIOFIQ /* Touchscreen */
+# define IRQ_CPLD IRQ_GPIO1INTR /* CPLD cascade */
+# define IRQ_PCC1_CD IRQ_GPIO_F2 /* PCCard 1 card detect */
+# define IRQ_PCC2_CD IRQ_GPIO_F3 /* PCCard 2 card detect */
+#endif
+
+#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
+# define IRQ_CPLD_V28 IRQ_GPIO7INTR /* CPLD cascade through GPIO_PF7 */
+# define IRQ_CPLD_V34 IRQ_GPIO3INTR /* CPLD cascade through GPIO_PF3 */
+#endif
+
+ /* System specific IRQs */
+
+#define IRQ_BOARD_START NR_IRQ_CPU
+
+#ifdef CONFIG_MACH_KEV7A400
+# define IRQ_KEV7A400_CPLD IRQ_BOARD_START
+# define NR_IRQ_BOARD 5
+# define IRQ_KEV7A400_MMC_CD IRQ_KEV7A400_CPLD + 0 /* MMC Card Detect */
+# define IRQ_KEV7A400_RI2 IRQ_KEV7A400_CPLD + 1 /* Ring Indicator 2 */
+# define IRQ_KEV7A400_IDE_CF IRQ_KEV7A400_CPLD + 2 /* Compact Flash (?) */
+# define IRQ_KEV7A400_ETH_INT IRQ_KEV7A400_CPLD + 3 /* Ethernet chip */
+# define IRQ_KEV7A400_INT IRQ_KEV7A400_CPLD + 4
+#endif
+
+#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
+# define IRQ_LPD7A40X_CPLD IRQ_BOARD_START
+# define NR_IRQ_BOARD 2
+# define IRQ_LPD7A40X_ETH_INT IRQ_LPD7A40X_CPLD + 0 /* Ethernet chip */
+# define IRQ_LPD7A400_TS IRQ_LPD7A40X_CPLD + 1 /* Touch screen */
+#endif
+
+#if defined (CONFIG_MACH_LPD7A400)
+# define IRQ_TOUCH IRQ_LPD7A400_TS
+#endif
+
+#define NR_IRQS (NR_IRQ_CPU + NR_IRQ_BOARD)
+
+#endif
diff --git a/arch/arm/mach-lh7a40x/include/mach/memory.h b/arch/arm/mach-lh7a40x/include/mach/memory.h
new file mode 100644
index 0000000..f7107b4
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/memory.h
@@ -0,0 +1,76 @@
+/* arch/arm/mach-lh7a40x/include/mach/memory.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ *
+ * Refer to <file:Documentation/arm/Sharp-LH/SDRAM> for more information.
+ *
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET UL(0xc0000000)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ * address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ * to an address that the kernel can use.
+ */
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#ifdef CONFIG_DISCONTIGMEM
+
+/*
+ * Given a kernel address, find the home node of the underlying memory.
+ */
+
+# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
+# define KVADDR_TO_NID(addr) \
+ ( ((((unsigned long) (addr) - PAGE_OFFSET) >> 24) & 1)\
+ | ((((unsigned long) (addr) - PAGE_OFFSET) >> 25) & ~1))
+# else /* 2 banks per node */
+# define KVADDR_TO_NID(addr) \
+ (((unsigned long) (addr) - PAGE_OFFSET) >> 26)
+# endif
+
+/*
+ * Given a page frame number, convert it to a node id.
+ */
+
+# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
+# define PFN_TO_NID(pfn) \
+ (((((pfn) - PHYS_PFN_OFFSET) >> (24 - PAGE_SHIFT)) & 1)\
+ | ((((pfn) - PHYS_PFN_OFFSET) >> (25 - PAGE_SHIFT)) & ~1))
+# else /* 2 banks per node */
+# define PFN_TO_NID(pfn) \
+ (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
+#endif
+
+/*
+ * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
+ * and returns the index corresponding to the appropriate page in the
+ * node's mem_map.
+ */
+
+# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
+# define LOCAL_MAP_NR(addr) \
+ (((unsigned long)(addr) & 0x003fffff) >> PAGE_SHIFT)
+# else /* 2 banks per node */
+# define LOCAL_MAP_NR(addr) \
+ (((unsigned long)(addr) & 0x01ffffff) >> PAGE_SHIFT)
+# endif
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-lh7a40x/include/mach/registers.h b/arch/arm/mach-lh7a40x/include/mach/registers.h
new file mode 100644
index 0000000..ea44396
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/registers.h
@@ -0,0 +1,224 @@
+/* arch/arm/mach-lh7a40x/include/mach/registers.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ * Copyright (C) 2004 Logic Product Development
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#include <mach/constants.h>
+
+#ifndef __ASM_ARCH_REGISTERS_H
+#define __ASM_ARCH_REGISTERS_H
+
+
+ /* Physical register base addresses */
+
+#define AC97C_PHYS (0x80000000) /* AC97 Controller */
+#define MMC_PHYS (0x80000100) /* Multimedia Card Controller */
+#define USB_PHYS (0x80000200) /* USB Client */
+#define SCI_PHYS (0x80000300) /* Secure Card Interface */
+#define CSC_PHYS (0x80000400) /* Clock/State Controller */
+#define INTC_PHYS (0x80000500) /* Interrupt Controller */
+#define UART1_PHYS (0x80000600) /* UART1 Controller */
+#define SIR_PHYS (0x80000600) /* IR Controller, same are UART1 */
+#define UART2_PHYS (0x80000700) /* UART2 Controller */
+#define UART3_PHYS (0x80000800) /* UART3 Controller */
+#define DCDC_PHYS (0x80000900) /* DC to DC Controller */
+#define ACI_PHYS (0x80000a00) /* Audio Codec Interface */
+#define SSP_PHYS (0x80000b00) /* Synchronous ... */
+#define TIMER_PHYS (0x80000c00) /* Timer Controller */
+#define RTC_PHYS (0x80000d00) /* Real-time Clock */
+#define GPIO_PHYS (0x80000e00) /* General Purpose IO */
+#define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */
+#define HRTFTC_PHYS (0x80001000) /* High-res TFT Controller (LH7A400) */
+#define ALI_PHYS (0x80001000) /* Advanced LCD Interface (LH7A404) */
+#define WDT_PHYS (0x80001400) /* Watchdog Timer */
+#define SMC_PHYS (0x80002000) /* Static Memory Controller */
+#define SDRC_PHYS (0x80002400) /* SDRAM Controller */
+#define DMAC_PHYS (0x80002800) /* DMA Controller */
+#define CLCDC_PHYS (0x80003000) /* Color LCD Controller */
+
+ /* Physical registers of the LH7A404 */
+
+#define ADC_PHYS (0x80001300) /* A/D & Touchscreen Controller */
+#define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */
+#define USBH_PHYS (0x80009000) /* USB OHCI host controller */
+#define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */
+
+/*#define KBD_PHYS (0x80000e00) */
+/*#define LCDICP_PHYS (0x80001000) */
+
+
+ /* Clock/State Controller register */
+
+#define CSC_PWRSR __REG(CSC_PHYS + 0x00) /* Reset register & ID */
+#define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */
+#define CSC_CLKSET __REG(CSC_PHYS + 0x20) /* Clock speed control */
+#define CSC_USBDRESET __REG(CSC_PHYS + 0x4c) /* USB Device resets */
+
+#define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */
+#define CSC_PWRCNT_DMAC_M2M1_EN (1<<27)
+#define CSC_PWRCNT_DMAC_M2M0_EN (1<<26)
+#define CSC_PWRCNT_DMAC_M2P8_EN (1<<25)
+#define CSC_PWRCNT_DMAC_M2P9_EN (1<<24)
+#define CSC_PWRCNT_DMAC_M2P6_EN (1<<23)
+#define CSC_PWRCNT_DMAC_M2P7_EN (1<<22)
+#define CSC_PWRCNT_DMAC_M2P4_EN (1<<21)
+#define CSC_PWRCNT_DMAC_M2P5_EN (1<<20)
+#define CSC_PWRCNT_DMAC_M2P2_EN (1<<19)
+#define CSC_PWRCNT_DMAC_M2P3_EN (1<<18)
+#define CSC_PWRCNT_DMAC_M2P0_EN (1<<17)
+#define CSC_PWRCNT_DMAC_M2P1_EN (1<<16)
+
+#define CSC_PWRSR_CHIPMAN_SHIFT (24)
+#define CSC_PWRSR_CHIPMAN_MASK (0xff)
+#define CSC_PWRSR_CHIPID_SHIFT (16)
+#define CSC_PWRSR_CHIPID_MASK (0xff)
+
+#define CSC_USBDRESET_APBRESETREG (1<<1)
+#define CSC_USBDRESET_IORESETREG (1<<0)
+
+ /* Interrupt Controller registers */
+
+#define INTC_INTSR __REG(INTC_PHYS + 0x00) /* Status */
+#define INTC_INTRSR __REG(INTC_PHYS + 0x04) /* Raw Status */
+#define INTC_INTENS __REG(INTC_PHYS + 0x08) /* Enable Set */
+#define INTC_INTENC __REG(INTC_PHYS + 0x0c) /* Enable Clear */
+
+
+ /* Vectored Interrupted Controller registers */
+
+#define VIC1_IRQSTATUS __REG(VIC1_PHYS + 0x00)
+#define VIC1_FIQSTATUS __REG(VIC1_PHYS + 0x04)
+#define VIC1_RAWINTR __REG(VIC1_PHYS + 0x08)
+#define VIC1_INTSEL __REG(VIC1_PHYS + 0x0c)
+#define VIC1_INTEN __REG(VIC1_PHYS + 0x10)
+#define VIC1_INTENCLR __REG(VIC1_PHYS + 0x14)
+#define VIC1_SOFTINT __REG(VIC1_PHYS + 0x18)
+#define VIC1_SOFTINTCLR __REG(VIC1_PHYS + 0x1c)
+#define VIC1_PROTECT __REG(VIC1_PHYS + 0x20)
+#define VIC1_VECTADDR __REG(VIC1_PHYS + 0x30)
+#define VIC1_NVADDR __REG(VIC1_PHYS + 0x34)
+#define VIC1_VAD0 __REG(VIC1_PHYS + 0x100)
+#define VIC1_VECTCNTL0 __REG(VIC1_PHYS + 0x200)
+#define VIC2_IRQSTATUS __REG(VIC2_PHYS + 0x00)
+#define VIC2_FIQSTATUS __REG(VIC2_PHYS + 0x04)
+#define VIC2_RAWINTR __REG(VIC2_PHYS + 0x08)
+#define VIC2_INTSEL __REG(VIC2_PHYS + 0x0c)
+#define VIC2_INTEN __REG(VIC2_PHYS + 0x10)
+#define VIC2_INTENCLR __REG(VIC2_PHYS + 0x14)
+#define VIC2_SOFTINT __REG(VIC2_PHYS + 0x18)
+#define VIC2_SOFTINTCLR __REG(VIC2_PHYS + 0x1c)
+#define VIC2_PROTECT __REG(VIC2_PHYS + 0x20)
+#define VIC2_VECTADDR __REG(VIC2_PHYS + 0x30)
+#define VIC2_NVADDR __REG(VIC2_PHYS + 0x34)
+#define VIC2_VAD0 __REG(VIC2_PHYS + 0x100)
+#define VIC2_VECTCNTL0 __REG(VIC2_PHYS + 0x200)
+
+#define VIC_CNTL_ENABLE (0x20)
+
+ /* USB Host registers (Open HCI compatible) */
+
+#define USBH_CMDSTATUS __REG(USBH_PHYS + 0x08)
+
+
+ /* GPIO registers */
+
+#define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* Interrupt Type 1 (Edge) */
+#define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* Interrupt Type 2 */
+#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */
+#define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */
+#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */
+#define GPIO_PINMUX __REG(GPIO_PHYS + 0x2c)
+#define GPIO_PADD __REG(GPIO_PHYS + 0x10)
+#define GPIO_PAD __REG(GPIO_PHYS + 0x00)
+#define GPIO_PCD __REG(GPIO_PHYS + 0x08)
+#define GPIO_PCDD __REG(GPIO_PHYS + 0x18)
+#define GPIO_PEDD __REG(GPIO_PHYS + 0x24)
+#define GPIO_PED __REG(GPIO_PHYS + 0x20)
+
+
+ /* Static Memory Controller registers */
+
+#define SMC_BCR0 __REG(SMC_PHYS + 0x00) /* Bank 0 Configuration */
+#define SMC_BCR1 __REG(SMC_PHYS + 0x04) /* Bank 1 Configuration */
+#define SMC_BCR2 __REG(SMC_PHYS + 0x08) /* Bank 2 Configuration */
+#define SMC_BCR3 __REG(SMC_PHYS + 0x0C) /* Bank 3 Configuration */
+#define SMC_BCR6 __REG(SMC_PHYS + 0x18) /* Bank 6 Configuration */
+#define SMC_BCR7 __REG(SMC_PHYS + 0x1c) /* Bank 7 Configuration */
+
+
+#ifdef CONFIG_MACH_KEV7A400
+# define CPLD_RD_OPT_DIP_SW __REG16(CPLD_PHYS + 0x00) /* Read Option SW */
+# define CPLD_WR_IO_BRD_CTL __REG16(CPLD_PHYS + 0x00) /* Write Control */
+# define CPLD_RD_PB_KEYS __REG16(CPLD_PHYS + 0x02) /* Read Btn Keys */
+# define CPLD_LATCHED_INTS __REG16(CPLD_PHYS + 0x04) /* Read INTR stat. */
+# define CPLD_CL_INT __REG16(CPLD_PHYS + 0x04) /* Clear INTR stat */
+# define CPLD_BOOT_MMC_STATUS __REG16(CPLD_PHYS + 0x06) /* R/O */
+# define CPLD_RD_KPD_ROW_SENSE __REG16(CPLD_PHYS + 0x08)
+# define CPLD_WR_PB_INT_MASK __REG16(CPLD_PHYS + 0x08)
+# define CPLD_RD_BRD_DISP_SW __REG16(CPLD_PHYS + 0x0a)
+# define CPLD_WR_EXT_INT_MASK __REG16(CPLD_PHYS + 0x0a)
+# define CPLD_LCD_PWR_CNTL __REG16(CPLD_PHYS + 0x0c)
+# define CPLD_SEVEN_SEG __REG16(CPLD_PHYS + 0x0e) /* 7 seg. LED mask */
+
+#endif
+
+#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
+
+# define CPLD_CONTROL __REG16(CPLD02_PHYS)
+# define CPLD_SPI_DATA __REG16(CPLD06_PHYS)
+# define CPLD_SPI_CONTROL __REG16(CPLD08_PHYS)
+# define CPLD_SPI_EEPROM __REG16(CPLD0A_PHYS)
+# define CPLD_INTERRUPTS __REG16(CPLD0C_PHYS) /* IRQ mask/status */
+# define CPLD_BOOT_MODE __REG16(CPLD0E_PHYS)
+# define CPLD_FLASH __REG16(CPLD10_PHYS)
+# define CPLD_POWER_MGMT __REG16(CPLD12_PHYS)
+# define CPLD_REVISION __REG16(CPLD14_PHYS)
+# define CPLD_GPIO_EXT __REG16(CPLD16_PHYS)
+# define CPLD_GPIO_DATA __REG16(CPLD18_PHYS)
+# define CPLD_GPIO_DIR __REG16(CPLD1A_PHYS)
+
+#endif
+
+ /* Timer registers */
+
+#define TIMER_LOAD1 __REG(TIMER_PHYS + 0x00) /* Timer 1 initial value */
+#define TIMER_VALUE1 __REG(TIMER_PHYS + 0x04) /* Timer 1 current value */
+#define TIMER_CONTROL1 __REG(TIMER_PHYS + 0x08) /* Timer 1 control word */
+#define TIMER_EOI1 __REG(TIMER_PHYS + 0x0c) /* Timer 1 interrupt clear */
+
+#define TIMER_LOAD2 __REG(TIMER_PHYS + 0x20) /* Timer 2 initial value */
+#define TIMER_VALUE2 __REG(TIMER_PHYS + 0x24) /* Timer 2 current value */
+#define TIMER_CONTROL2 __REG(TIMER_PHYS + 0x28) /* Timer 2 control word */
+#define TIMER_EOI2 __REG(TIMER_PHYS + 0x2c) /* Timer 2 interrupt clear */
+
+#define TIMER_BUZZCON __REG(TIMER_PHYS + 0x40) /* Buzzer configuration */
+
+#define TIMER_LOAD3 __REG(TIMER_PHYS + 0x80) /* Timer 3 initial value */
+#define TIMER_VALUE3 __REG(TIMER_PHYS + 0x84) /* Timer 3 current value */
+#define TIMER_CONTROL3 __REG(TIMER_PHYS + 0x88) /* Timer 3 control word */
+#define TIMER_EOI3 __REG(TIMER_PHYS + 0x8c) /* Timer 3 interrupt clear */
+
+#define TIMER_C_ENABLE (1<<7)
+#define TIMER_C_PERIODIC (1<<6)
+#define TIMER_C_FREERUNNING (0)
+#define TIMER_C_2KHZ (0x00) /* 1.986 kHz */
+#define TIMER_C_508KHZ (0x08)
+
+ /* GPIO registers */
+
+#define GPIO_PFDD __REG(GPIO_PHYS + 0x34) /* PF direction */
+#define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* IRQ edge or lvl */
+#define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* IRQ activ hi/lo */
+#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIOF end of IRQ */
+#define GPIO_GPIOFINTEN __REG(GPIO_PHYS + 0x58) /* GPIOF IRQ enable */
+#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIOF IRQ latch */
+#define GPIO_RAWINTSTATUS __REG(GPIO_PHYS + 0x60) /* GPIOF IRQ raw */
+
+
+#endif /* _ASM_ARCH_REGISTERS_H */
diff --git a/arch/arm/mach-lh7a40x/include/mach/ssp.h b/arch/arm/mach-lh7a40x/include/mach/ssp.h
new file mode 100644
index 0000000..132b1c4
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/ssp.h
@@ -0,0 +1,71 @@
+/* ssp.h
+ $Id$
+
+ written by Marc Singer
+ 6 Dec 2004
+
+ Copyright (C) 2004 Marc Singer
+
+ -----------
+ DESCRIPTION
+ -----------
+
+ This SSP header is available throughout the kernel, for this
+ machine/architecture, because drivers that use it may be dispersed.
+
+ This file was cloned from the 7952x implementation. It would be
+ better to share them, but we're taking an easier approach for the
+ time being.
+
+*/
+
+#if !defined (__SSP_H__)
+# define __SSP_H__
+
+/* ----- Includes */
+
+/* ----- Types */
+
+struct ssp_driver {
+ int (*init) (void);
+ void (*exit) (void);
+ void (*acquire) (void);
+ void (*release) (void);
+ int (*configure) (int device, int mode, int speed,
+ int frame_size_write, int frame_size_read);
+ void (*chip_select) (int enable);
+ void (*set_callbacks) (void* handle,
+ irqreturn_t (*callback_tx)(void*),
+ irqreturn_t (*callback_rx)(void*));
+ void (*enable) (void);
+ void (*disable) (void);
+// int (*save_state) (void*);
+// void (*restore_state) (void*);
+ int (*read) (void);
+ int (*write) (u16 data);
+ int (*write_read) (u16 data);
+ void (*flush) (void);
+ void (*write_async) (void* pv, size_t cb);
+ size_t (*write_pos) (void);
+};
+
+ /* These modes are only available on the LH79524 */
+#define SSP_MODE_SPI (1)
+#define SSP_MODE_SSI (2)
+#define SSP_MODE_MICROWIRE (3)
+#define SSP_MODE_I2S (4)
+
+ /* CPLD SPI devices */
+#define DEVICE_EEPROM 0 /* Configuration eeprom */
+#define DEVICE_MAC 1 /* MAC eeprom (LPD79524) */
+#define DEVICE_CODEC 2 /* Audio codec */
+#define DEVICE_TOUCH 3 /* Touch screen (LPD79520) */
+
+/* ----- Globals */
+
+/* ----- Prototypes */
+
+//extern struct ssp_driver lh79520_i2s_driver;
+extern struct ssp_driver lh7a400_cpld_ssp_driver;
+
+#endif /* __SSP_H__ */
diff --git a/arch/arm/mach-lh7a40x/include/mach/system.h b/arch/arm/mach-lh7a40x/include/mach/system.h
new file mode 100644
index 0000000..fa46bb1e
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/system.h
@@ -0,0 +1,19 @@
+/* arch/arm/mach-lh7a40x/include/mach/system.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+static inline void arch_idle(void)
+{
+ cpu_do_idle ();
+}
+
+static inline void arch_reset(char mode)
+{
+ cpu_reset (0);
+}
diff --git a/arch/arm/mach-lh7a40x/include/mach/timex.h b/arch/arm/mach-lh7a40x/include/mach/timex.h
new file mode 100644
index 0000000..08028ce
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/timex.h
@@ -0,0 +1,17 @@
+/* arch/arm/mach-lh7a40x/include/mach/timex.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#include <mach/constants.h>
+
+#define CLOCK_TICK_RATE (PLL_CLOCK/6/16)
+
+/*
+#define CLOCK_TICK_RATE 3686400
+*/
diff --git a/arch/arm/mach-lh7a40x/include/mach/uncompress.h b/arch/arm/mach-lh7a40x/include/mach/uncompress.h
new file mode 100644
index 0000000..55b80d4
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/uncompress.h
@@ -0,0 +1,38 @@
+/* arch/arm/mach-lh7a40x/include/mach/uncompress.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#include <mach/registers.h>
+
+#ifndef UART_R_DATA
+# define UART_R_DATA (0x00)
+#endif
+#ifndef UART_R_STATUS
+# define UART_R_STATUS (0x10)
+#endif
+#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */
+
+ /* Access UART with physical addresses before MMU is setup */
+#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS))
+#define UART_DATA (*(volatile unsigned long*) (UART2_PHYS + UART_R_DATA))
+
+static inline void putc(int ch)
+{
+ while (UART_STATUS & nTxRdy)
+ barrier();
+ UART_DATA = ch;
+}
+
+static inline void flush(void)
+{
+}
+
+ /* NULL functions; we don't presently need them */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-lh7a40x/include/mach/vmalloc.h b/arch/arm/mach-lh7a40x/include/mach/vmalloc.h
new file mode 100644
index 0000000..3fbd494
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/include/mach/vmalloc.h
@@ -0,0 +1,10 @@
+/* arch/arm/mach-lh7a40x/include/mach/vmalloc.h
+ *
+ * Copyright (C) 2004 Coastal Environmental Systems
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+#define VMALLOC_END (0xe8000000)
diff --git a/arch/arm/mach-lh7a40x/irq-lh7a400.c b/arch/arm/mach-lh7a40x/irq-lh7a400.c
index 0e5a805..1ad3afc 100644
--- a/arch/arm/mach-lh7a40x/irq-lh7a400.c
+++ b/arch/arm/mach-lh7a40x/irq-lh7a400.c
@@ -12,10 +12,10 @@
#include <linux/module.h>
#include <linux/interrupt.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
-#include <asm/arch/irqs.h>
+#include <mach/irqs.h>
#include "common.h"
diff --git a/arch/arm/mach-lh7a40x/irq-lh7a404.c b/arch/arm/mach-lh7a40x/irq-lh7a404.c
index f3293bf..12b045b 100644
--- a/arch/arm/mach-lh7a40x/irq-lh7a404.c
+++ b/arch/arm/mach-lh7a40x/irq-lh7a404.c
@@ -12,10 +12,10 @@
#include <linux/module.h>
#include <linux/interrupt.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
-#include <asm/arch/irqs.h>
+#include <mach/irqs.h>
#include "common.h"
diff --git a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
index 41bf9f8..0d5063eb 100644
--- a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
+++ b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c
@@ -13,10 +13,10 @@
#include <linux/module.h>
#include <linux/interrupt.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
-#include <asm/arch/irqs.h>
+#include <mach/irqs.h>
#include "common.h"
diff --git a/arch/arm/mach-lh7a40x/ssp-cpld.c b/arch/arm/mach-lh7a40x/ssp-cpld.c
index 4cd31bb..51fbef9 100644
--- a/arch/arm/mach-lh7a40x/ssp-cpld.c
+++ b/arch/arm/mach-lh7a40x/ssp-cpld.c
@@ -46,9 +46,9 @@
#include <asm/io.h>
#include <asm/irq.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
-#include <asm/arch/ssp.h>
+#include <mach/ssp.h>
//#define TALK
diff --git a/arch/arm/mach-lh7a40x/time.c b/arch/arm/mach-lh7a40x/time.c
index 1c7e469..7fe9e06 100644
--- a/arch/arm/mach-lh7a40x/time.c
+++ b/arch/arm/mach-lh7a40x/time.c
@@ -14,7 +14,7 @@
#include <linux/irq.h>
#include <linux/time.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/leds.h>