perfcounters/powerpc: add support for POWER5+ processors
Impact: more hardware support
This adds the back-end for the PMU on the POWER5+ processors (i.e. GS,
including GS DD3 aka POWER5++). This doesn't use the fixed-function
PMC5 and PMC6 since they don't respect the freeze conditions and don't
generate interrupts, as on POWER6.
Signed-off-by: Paul Mackerras <paulus@samba.org>
diff --git a/arch/powerpc/kernel/perf_counter.c b/arch/powerpc/kernel/perf_counter.c
index 4fec112..162f398 100644
--- a/arch/powerpc/kernel/perf_counter.c
+++ b/arch/powerpc/kernel/perf_counter.c
@@ -826,6 +826,7 @@
extern struct power_pmu ppc970_pmu;
extern struct power_pmu power5_pmu;
+extern struct power_pmu power5p_pmu;
extern struct power_pmu power6_pmu;
static int init_perf_counters(void)
@@ -848,6 +849,9 @@
case PV_POWER5:
ppmu = &power5_pmu;
break;
+ case PV_POWER5p:
+ ppmu = &power5p_pmu;
+ break;
case 0x3e:
ppmu = &power6_pmu;
break;