)]}'
{
  "commit": "b445e26cbf784cdba10f2b6c3e2cd3ee7bab360a",
  "tree": "8c8c377a7e5cbf608d730ec45e091e4f2b826a82",
  "parents": [
    "020f46a39eb7b99a575b9f4d105fce2b142acdf1"
  ],
  "author": {
    "name": "David S. Miller",
    "email": "davem@davemloft.net",
    "time": "Mon Jun 27 15:42:04 2005 -0700"
  },
  "committer": {
    "name": "David S. Miller",
    "email": "davem@davemloft.net",
    "time": "Mon Jun 27 15:42:04 2005 -0700"
  },
  "message": "[SPARC64]: Avoid membar instructions in delay slots.\n\nIn particular, avoid membar instructions in the delay\nslot of a jmpl instruction.\n\nUltraSPARC-I, II, IIi, and IIe have a bug, documented in\nthe UltraSPARC-IIi User\u0027s Manual, Appendix K, Erratum 51\n\nThe long and short of it is that if the IMU unit misses\non a branch or jmpl, and there is a store buffer synchronizing\nmembar in the delay slot, the chip can stop fetching instructions.\n\nIf interrupts are enabled or some other trap is enabled, the\nchip will unwedge itself, but performance will suffer.\n\nWe already had a workaround for this bug in a few spots, but\nit\u0027s better to have the entire tree sanitized for this rule.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n",
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