ARM: OMAP3: clock: Convert to common clk
Convert all OMAP3 specific platform files to use COMMON clk
and keep all the changes under the CONFIG_COMMON_CLK macro check
so it does not break any existing code. At a later point switch
to COMMON clk and get rid of all old/legacy code.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index 5510d92..aeaaa87 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -45,8 +45,15 @@
* Program the DPLL M2 divider with the rounded target rate. Returns
* -EINVAL upon error, or 0 upon success.
*/
+#ifdef CONFIG_COMMON_CLK
+int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+#else
int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
{
+#endif
u32 new_div = 0;
u32 unlock_dll = 0;
u32 c;
@@ -64,7 +71,11 @@
return -EINVAL;
sdrcrate = __clk_get_rate(sdrc_ick_p);
+#ifdef CONFIG_COMMON_CLK
+ clkrate = __clk_get_rate(hw->clk);
+#else
clkrate = __clk_get_rate(clk);
+#endif
if (rate > clkrate)
sdrcrate <<= ((rate / clkrate) >> 1);
else
@@ -113,7 +124,9 @@
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
0, 0, 0, 0);
+#ifndef CONFIG_COMMON_CLK
clk->rate = rate;
+#endif
return 0;
}