blackfin: add bf60x to current framework
This patch added bf60x to current blackfin kernel framework.
Signed-off-by: Bob Liu <lliubbo@gmail.com>
diff --git a/arch/blackfin/kernel/bfin_dma.c b/arch/blackfin/kernel/bfin_dma.c
index 40c2ed6..b612324 100644
--- a/arch/blackfin/kernel/bfin_dma.c
+++ b/arch/blackfin/kernel/bfin_dma.c
@@ -45,9 +45,15 @@
atomic_set(&dma_ch[i].chan_status, 0);
dma_ch[i].regs = dma_io_base_addr[i];
}
+#ifdef CH_MEM_STREAM3_SRC
+ /* Mark MEMDMA Channel 3 as requested since we're using it internally */
+ request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy");
+ request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy");
+#else
/* Mark MEMDMA Channel 0 as requested since we're using it internally */
request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy");
request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy");
+#endif
#if defined(CONFIG_DEB_DMA_URGENT)
bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE()
@@ -204,6 +210,7 @@
# ifndef MAX_DMA_SUSPEND_CHANNELS
# define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS
# endif
+# ifndef CONFIG_BF60x
int blackfin_dma_suspend(void)
{
int i;
@@ -213,7 +220,6 @@
printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
return -EBUSY;
}
-
if (i < MAX_DMA_SUSPEND_CHANNELS)
dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
}
@@ -230,7 +236,6 @@
for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
dma_ch[i].regs->cfg = 0;
-
if (i < MAX_DMA_SUSPEND_CHANNELS)
dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
}
@@ -238,6 +243,16 @@
bfin_write_DMAC_TC_PER(0x0111);
#endif
}
+# else
+int blackfin_dma_suspend(void)
+{
+ return 0;
+}
+
+void blackfin_dma_resume(void)
+{
+}
+#endif
#endif
/**
@@ -279,10 +294,10 @@
src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
}
- if (!bfin_read16(&src_ch->cfg))
+ if (!DMA_MMR_READ(&src_ch->cfg))
break;
- else if (bfin_read16(&dst_ch->irq_status) & DMA_DONE) {
- bfin_write16(&src_ch->cfg, 0);
+ else if (DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE) {
+ DMA_MMR_WRITE(&src_ch->cfg, 0);
break;
}
}
@@ -295,22 +310,31 @@
/* Destination */
bfin_write32(&dst_ch->start_addr, dst);
- bfin_write16(&dst_ch->x_count, size >> 2);
- bfin_write16(&dst_ch->x_modify, 1 << 2);
- bfin_write16(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
+ DMA_MMR_WRITE(&dst_ch->x_count, size >> 2);
+ DMA_MMR_WRITE(&dst_ch->x_modify, 1 << 2);
+ DMA_MMR_WRITE(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
/* Source */
bfin_write32(&src_ch->start_addr, src);
- bfin_write16(&src_ch->x_count, size >> 2);
- bfin_write16(&src_ch->x_modify, 1 << 2);
- bfin_write16(&src_ch->irq_status, DMA_DONE | DMA_ERR);
+ DMA_MMR_WRITE(&src_ch->x_count, size >> 2);
+ DMA_MMR_WRITE(&src_ch->x_modify, 1 << 2);
+ DMA_MMR_WRITE(&src_ch->irq_status, DMA_DONE | DMA_ERR);
/* Enable */
- bfin_write16(&src_ch->cfg, DMAEN | WDSIZE_32);
- bfin_write16(&dst_ch->cfg, WNR | DI_EN | DMAEN | WDSIZE_32);
+ DMA_MMR_WRITE(&src_ch->cfg, DMAEN | WDSIZE_32);
+ DMA_MMR_WRITE(&dst_ch->cfg, WNR | DI_EN_X | DMAEN | WDSIZE_32);
/* Since we are atomic now, don't use the workaround ssync */
__builtin_bfin_ssync();
+
+#ifdef CONFIG_BF60x
+ /* Work around a possible MDMA anomaly. Running 2 MDMA channels to
+ * transfer DDR data to L1 SRAM may corrupt data.
+ * Should be reverted after this issue is root caused.
+ */
+ while (!(DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE))
+ continue;
+#endif
}
void __init early_dma_memcpy_done(void)
@@ -336,6 +360,42 @@
__builtin_bfin_ssync();
}
+#ifdef CH_MEM_STREAM3_SRC
+#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG
+#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG
+#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR
+#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S3_IRQ_STATUS
+#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S3_X_COUNT
+#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S3_X_MODIFY
+#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S3_Y_COUNT
+#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S3_Y_MODIFY
+#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D3_CONFIG
+#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D3_START_ADDR
+#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D3_IRQ_STATUS
+#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D3_IRQ_STATUS
+#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D3_X_COUNT
+#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D3_X_MODIFY
+#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D3_Y_COUNT
+#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D3_Y_MODIFY
+#else
+#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S0_CONFIG
+#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S0_CONFIG
+#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S0_START_ADDR
+#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S0_IRQ_STATUS
+#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S0_X_COUNT
+#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S0_X_MODIFY
+#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S0_Y_COUNT
+#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S0_Y_MODIFY
+#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D0_CONFIG
+#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D0_START_ADDR
+#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D0_IRQ_STATUS
+#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D0_IRQ_STATUS
+#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D0_X_COUNT
+#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D0_X_MODIFY
+#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D0_Y_COUNT
+#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D0_Y_MODIFY
+#endif
+
/**
* __dma_memcpy - program the MDMA registers
*
@@ -358,8 +418,8 @@
*/
__builtin_bfin_ssync();
- if (bfin_read_MDMA_S0_CONFIG())
- while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
+ if (bfin_read_MDMA_S_CONFIG())
+ while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
continue;
if (conf & DMA2D) {
@@ -374,39 +434,42 @@
u32 shift = abs(dmod) >> 1;
size_t ycnt = cnt >> (16 - shift);
cnt = 1 << (16 - shift);
- bfin_write_MDMA_D0_Y_COUNT(ycnt);
- bfin_write_MDMA_S0_Y_COUNT(ycnt);
- bfin_write_MDMA_D0_Y_MODIFY(dmod);
- bfin_write_MDMA_S0_Y_MODIFY(smod);
+ bfin_write_MDMA_D_Y_COUNT(ycnt);
+ bfin_write_MDMA_S_Y_COUNT(ycnt);
+ bfin_write_MDMA_D_Y_MODIFY(dmod);
+ bfin_write_MDMA_S_Y_MODIFY(smod);
}
- bfin_write_MDMA_D0_START_ADDR(daddr);
- bfin_write_MDMA_D0_X_COUNT(cnt);
- bfin_write_MDMA_D0_X_MODIFY(dmod);
- bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+ bfin_write_MDMA_D_START_ADDR(daddr);
+ bfin_write_MDMA_D_X_COUNT(cnt);
+ bfin_write_MDMA_D_X_MODIFY(dmod);
+ bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
- bfin_write_MDMA_S0_START_ADDR(saddr);
- bfin_write_MDMA_S0_X_COUNT(cnt);
- bfin_write_MDMA_S0_X_MODIFY(smod);
- bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+ bfin_write_MDMA_S_START_ADDR(saddr);
+ bfin_write_MDMA_S_X_COUNT(cnt);
+ bfin_write_MDMA_S_X_MODIFY(smod);
+ bfin_write_MDMA_S_IRQ_STATUS(DMA_DONE | DMA_ERR);
- bfin_write_MDMA_S0_CONFIG(DMAEN | conf);
- bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | conf);
+ bfin_write_MDMA_S_CONFIG(DMAEN | conf);
+ if (conf & DMA2D)
+ bfin_write_MDMA_D_CONFIG(WNR | DI_EN_Y | DMAEN | conf);
+ else
+ bfin_write_MDMA_D_CONFIG(WNR | DI_EN_X | DMAEN | conf);
spin_unlock_irqrestore(&mdma_lock, flags);
SSYNC();
- while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
- if (bfin_read_MDMA_S0_CONFIG())
+ while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
+ if (bfin_read_MDMA_S_CONFIG())
continue;
else
return;
- bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+ bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
- bfin_write_MDMA_S0_CONFIG(0);
- bfin_write_MDMA_D0_CONFIG(0);
+ bfin_write_MDMA_S_CONFIG(0);
+ bfin_write_MDMA_D_CONFIG(0);
}
/**
@@ -448,8 +511,10 @@
}
size >>= shift;
+#ifndef DMA_MMR_SIZE_32
if (size > 0x10000)
conf |= DMA2D;
+#endif
__dma_memcpy(dst, mod, src, mod, size, conf);
@@ -488,6 +553,9 @@
*/
void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
{
+#ifdef DMA_MMR_SIZE_32
+ _dma_memcpy(pdst, psrc, size);
+#else
size_t bulk, rest;
bulk = size & ~0xffff;
@@ -495,6 +563,7 @@
if (bulk)
_dma_memcpy(pdst, psrc, bulk);
_dma_memcpy(pdst + bulk, psrc + bulk, rest);
+#endif
return pdst;
}
EXPORT_SYMBOL(dma_memcpy_nocache);
@@ -514,14 +583,14 @@
}
EXPORT_SYMBOL(safe_dma_memcpy);
-static void _dma_out(unsigned long addr, unsigned long buf, unsigned short len,
+static void _dma_out(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
u16 size, u16 dma_size)
{
blackfin_dcache_flush_range(buf, buf + len * size);
__dma_memcpy(addr, 0, buf, size, len, dma_size);
}
-static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len,
+static void _dma_in(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
u16 size, u16 dma_size)
{
blackfin_dcache_invalidate_range(buf, buf + len * size);
@@ -529,7 +598,7 @@
}
#define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \
-void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned short len) \
+void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned DMA_MMR_SIZE_TYPE len) \
{ \
_dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \
} \