[MIPS] time: SMP-proofing of Sibyte clockevent/clocksource code.
The BCM148 has 4 cores but there are also just 4 generic timers available
so use the ZBbus cycle counter instead of it. In addition the ZBbus
counter also offers a much higher resolution and 64-bit counting so I'm
considering a later complete conversion to it once I figure out if all
members of the Sibyte SOC family support it - the docs seem to agree but
the headers files seem to disagree ...
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c
index 02b266a..436ba78 100644
--- a/arch/mips/sibyte/bcm1480/smp.c
+++ b/arch/mips/sibyte/bcm1480/smp.c
@@ -58,7 +58,7 @@
/*
* SMP init and finish on secondary CPUs
*/
-void bcm1480_smp_init(void)
+void __cpuinit bcm1480_smp_init(void)
{
unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
STATUSF_IP1 | STATUSF_IP0;
@@ -67,7 +67,7 @@
change_c0_status(ST0_IM, imask);
}
-void bcm1480_smp_finish(void)
+void __cpuinit bcm1480_smp_finish(void)
{
extern void sb1480_clockevent_init(void);