x86, apic: unify phys_pkg_id()

- unify the call signature of 64-bit to that of 32-bit

 - clean up the types all around

 - clean up namespace contamination

Signed-off-by: Ingo Molnar <mingo@elte.hu>
diff --git a/arch/x86/include/asm/bigsmp/apic.h b/arch/x86/include/asm/bigsmp/apic.h
index f49d440..b7cba5b 100644
--- a/arch/x86/include/asm/bigsmp/apic.h
+++ b/arch/x86/include/asm/bigsmp/apic.h
@@ -133,7 +133,7 @@
 	return BAD_APICID;
 }
 
-static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
+static inline int phys_pkg_id(int cpuid_apic, int index_msb)
 {
 	return cpuid_apic >> index_msb;
 }
diff --git a/arch/x86/include/asm/es7000/apic.h b/arch/x86/include/asm/es7000/apic.h
index 038c4f0..d2c6c20 100644
--- a/arch/x86/include/asm/es7000/apic.h
+++ b/arch/x86/include/asm/es7000/apic.h
@@ -221,7 +221,7 @@
 	return apicid;
 }
 
-static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
+static inline int phys_pkg_id(int cpuid_apic, int index_msb)
 {
 	return cpuid_apic >> index_msb;
 }
diff --git a/arch/x86/include/asm/genapic.h b/arch/x86/include/asm/genapic.h
index f292fd0..14b19de 100644
--- a/arch/x86/include/asm/genapic.h
+++ b/arch/x86/include/asm/genapic.h
@@ -48,11 +48,7 @@
 	void (*setup_portio_remap)(void);
 	int (*check_phys_apicid_present)(int boot_cpu_physical_apicid);
 	void (*enable_apic_mode)(void);
-#ifdef CONFIG_X86_32
-	u32 (*phys_pkg_id)(u32 cpuid_apic, int index_msb);
-#else
-	unsigned int (*phys_pkg_id)(int index_msb);
-#endif
+	int (*phys_pkg_id)(int cpuid_apic, int index_msb);
 
 	/*
 	 * When one of the next two hooks returns 1 the genapic
diff --git a/arch/x86/include/asm/mach-default/mach_apic.h b/arch/x86/include/asm/mach-default/mach_apic.h
index 3647c92..55797a3 100644
--- a/arch/x86/include/asm/mach-default/mach_apic.h
+++ b/arch/x86/include/asm/mach-default/mach_apic.h
@@ -65,7 +65,7 @@
 	return (unsigned int)(mask1 & mask2 & mask3);
 }
 
-static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
+static inline int phys_pkg_id(int cpuid_apic, int index_msb)
 {
 	return cpuid_apic >> index_msb;
 }
diff --git a/arch/x86/include/asm/numaq/apic.h b/arch/x86/include/asm/numaq/apic.h
index dc93c30..bc2c8a4 100644
--- a/arch/x86/include/asm/numaq/apic.h
+++ b/arch/x86/include/asm/numaq/apic.h
@@ -113,7 +113,7 @@
 }
 
 /* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */
-static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
+static inline int phys_pkg_id(int cpuid_apic, int index_msb)
 {
 	return cpuid_apic >> index_msb;
 }
diff --git a/arch/x86/include/asm/summit/apic.h b/arch/x86/include/asm/summit/apic.h
index 526d19e..64cd441 100644
--- a/arch/x86/include/asm/summit/apic.h
+++ b/arch/x86/include/asm/summit/apic.h
@@ -175,13 +175,14 @@
 	return apicid;
 }
 
-/* cpuid returns the value latched in the HW at reset, not the APIC ID
+/*
+ * cpuid returns the value latched in the HW at reset, not the APIC ID
  * register's value.  For any box whose BIOS changes APIC IDs, like
  * clustered APIC systems, we must use hard_smp_processor_id.
  *
  * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
  */
-static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
+static inline int phys_pkg_id(int cpuid_apic, int index_msb)
 {
 	return hard_smp_processor_id() >> index_msb;
 }