)]}'
{
  "commit": "deb9b4ce97cbbf61a150f317badbeb7531aab276",
  "tree": "c296cb097c801ef64ee182a59978d3e541e700e8",
  "parents": [
    "81bc3009e061cfd0e62e03a6761cce39c750b65e",
    "3c424f359898aff48c3d5bed608ac706f8a528c3"
  ],
  "author": {
    "name": "Linus Torvalds",
    "email": "torvalds@linux-foundation.org",
    "time": "Sat Jan 28 13:27:10 2012 -0800"
  },
  "committer": {
    "name": "Linus Torvalds",
    "email": "torvalds@linux-foundation.org",
    "time": "Sat Jan 28 13:27:10 2012 -0800"
  },
  "message": "Merge branch \u0027fixes\u0027 of git://git.linaro.org/people/rmk/linux-arm\n\n* \u0027fixes\u0027 of git://git.linaro.org/people/rmk/linux-arm: (31 commits)\n  ARM: 7304/1: ioremap: fix boundary check when reusing static mapping\n  ARM: 7301/1: Rename the T() macro to TUSER() to avoid namespace conflicts\n  ARM: 7299/1: ftrace: clear zero bit in reported IPs for Thumb-2\n  ARM: 7298/1: realview: fix mapping of MPCore private memory region\n  PCMCIA: fix sa1111 oops on remove\n  ARM: 7288/1: mach-sa1100: add missing module_init() call\n  ARM: 7297/1: smp_twd: make sure timer is stopped before registering it\n  ARM: 7296/1: proc-v7.S: remove HARVARD_CACHE preprocessor guards\n  ARM: 7295/1: cortex-a7: move proc_info out of !CONFIG_ARM_LPAE block\n  ARM: 7293/1: logical_cpu_map: decouple CPU mapping from SMP\n  ARM: 7291/1: cache: assume 64-byte L1 cachelines for ARMv7 CPUs\n  ARM: 7290/1: vmlinux.lds.S: align the exception fixup table to a 4-byte boundary\n  ARM: 7289/1: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes\n  MFD: ucb1x00-ts: fix resume failure\n  MFD: ucb1x00-core: fix gpiolib direction_output handling\n  MFD: ucb1x00-core: fix missing restore of io output data on resume\n  MFD: mcp-core: fix mcp_priv() to be more type safe\n  MFD: mcp-core: fix complaints from the genirq layer\n  Revert \"ARM: sa11x0: Implement autoloading of codec and codec pdata for mcp bus.\"\n  Revert \"ARM: sa1100: Refactor mcp-sa11x0 to use platform resources.\"\n  ...\n\nFix up conflict due to arch/arm/mach-mx5/Kconfig having been merged into\nmach-imx5 (commit 784a90c0a7d8: \"ARM i.MX: Merge i.MX5 support into\nmach-imx\"), but the ARM_L1_CACHE_SHIFT_6 entry was moved to be driven by\nthe CPU_V7 logic from it in the old location in rmk\u0027s branch (commit\na092f2b15399: \"ARM: 7291/1: cache: assume 64-byte L1 cachelines for\nARMv7 CPUs\").\n",
  "tree_diff": []
}