)]}'
{
  "commit": "e13d8f383985b7ab8c859c1fa327e9b3d201894e",
  "tree": "a342ae0e910f1e7c2e0903fcf078a359b9ff7031",
  "parents": [
    "44e51b29228cdd30bb8f54a42eb34ea0674d5f96"
  ],
  "author": {
    "name": "Nishanth Menon",
    "email": "nm@ti.com",
    "time": "Sat Jul 09 14:37:21 2011 -0700"
  },
  "committer": {
    "name": "Kevin Hilman",
    "email": "khilman@ti.com",
    "time": "Fri Aug 05 11:54:55 2011 -0700"
  },
  "message": "OMAP3+: SR: ensure pm-runtime callbacks can be invoked with IRQs disabled\n\nSmartReflex should be disabled while entering low power mode due to\na) SmartReflex values are not defined for retention voltage, further\nb) with SmartReflex enabled, if CPU enters lower c-states, FSM will try\nto bump the voltage to current OPP\u0027s voltage for which it has entered c-state;\nhence SmartReflex needs to be disabled for MPU, CORE and IVA voltage\ndomains in idle path before enabling auto retention voltage achievement\non the device.\n\nHowever, since the current pm_runtime setup for SmartReflex devices are\nsetup to allow callbacks to be invoked with interrupts enabled, calling\nSmartReflex enable/disable from other contexts such as idle paths\nwhere preemption is disabled causes warnings such as the following\nindicating of a potential race.\n[   82.023895] [\u003cc04d079c\u003e] (__irq_svc+0x3c/0x120) from [\u003cc04d0484\u003e] (_raw_spin_unlock_irq+0x28/0x2c)\n[   82.023895] [\u003cc04d0484\u003e] (_raw_spin_unlock_irq+0x28/0x2c) from [\u003cc0323234\u003e] (rpm_callback+0x4c/0x68)\n[   82.023956] [\u003cc0323234\u003e] (rpm_callback+0x4c/0x68) from [\u003cc0323f7c\u003e] (rpm_resume+0x338/0x53c)\n[   82.023956] [\u003cc0323f7c\u003e] (rpm_resume+0x338/0x53c) from [\u003cc03243f4\u003e] (__pm_runtime_resume+0x48/0x60)\n[   82.023986] [\u003cc03243f4\u003e] (__pm_runtime_resume+0x48/0x60) from [\u003cc008aee0\u003e] (sr_enable+0xa8/0x19c)\n[   82.023986] [\u003cc008aee0\u003e] (sr_enable+0xa8/0x19c) from [\u003cc008b2fc\u003e] (omap_sr_enable+0x50/0x90)\n[   82.024017] [\u003cc008b2fc\u003e] (omap_sr_enable+0x50/0x90) from [\u003cc00888c0\u003e] (omap4_enter_sleep+0x138/0x168)\n\nInstead, we use pm_runtime_irq_safe to tell the PM core that callbacks can be\ninvoked in interrupt disabled contexts.\n\nAcked-by: Rajendra Nayak \u003crnayak@ti.com\u003e\nSigned-off-by: Nishanth Menon \u003cnm@ti.com\u003e\n[khilman@ti.com: minor changelog edits]\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2ce2fb7664bc60992f7f5eebbbed3fc57345ac9e",
      "old_mode": 33188,
      "old_path": "arch/arm/mach-omap2/smartreflex.c",
      "new_id": "dc8e86a54ac57c32df1b84058cf45ea71b08b497",
      "new_mode": 33188,
      "new_path": "arch/arm/mach-omap2/smartreflex.c"
    }
  ]
}