)]}'
{
  "commit": "e84665c9cb4db963393fafad6fefe5efdd7e4a09",
  "tree": "545c4a2a63a77b853e3f34609d86b346fe61baf4",
  "parents": [
    "076d3e10a54caa2c148de5732c126c7a31381d48"
  ],
  "author": {
    "name": "Lennert Buytenhek",
    "email": "buytenh@wantstofly.org",
    "time": "Fri Mar 20 09:52:09 2009 +0000"
  },
  "committer": {
    "name": "David S. Miller",
    "email": "davem@davemloft.net",
    "time": "Sat Mar 21 19:06:54 2009 -0700"
  },
  "message": "dsa: add switch chip cascading support\n\nThe initial version of the DSA driver only supported a single switch\nchip per network interface, while DSA-capable switch chips can be\ninterconnected to form a tree of switch chips.  This patch adds support\nfor multiple switch chips on a network interface.\n\nAn example topology for a 16-port device with an embedded CPU is as\nfollows:\n\n\t+-----+          +--------+       +--------+\n\t|     |eth0    10| switch |9    10| switch |\n\t| CPU +----------+        +-------+        |\n\t|     |          | chip 0 |       | chip 1 |\n\t+-----+          +---++---+       +---++---+\n\t                     ||               ||\n\t                     ||               ||\n\t                     ||1000baseT      ||1000baseT\n\t                     ||ports 1-8      ||ports 9-16\n\nThis requires a couple of interdependent changes in the DSA layer:\n\n- The dsa platform driver data needs to be extended: there is still\n  only one netdevice per DSA driver instance (eth0 in the example\n  above), but each of the switch chips in the tree needs its own\n  mii_bus device pointer, MII management bus address, and port name\n  array. (include/net/dsa.h)  The existing in-tree dsa users need\n  some small changes to deal with this. (arch/arm)\n\n- The DSA and Ethertype DSA tagging modules need to be extended to\n  use the DSA device ID field on receive and demultiplex the packet\n  accordingly, and fill in the DSA device ID field on transmit\n  according to which switch chip the packet is heading to.\n  (net/dsa/tag_{dsa,edsa}.c)\n\n- The concept of \"CPU port\", which is the switch chip port that the\n  CPU is connected to (port 10 on switch chip 0 in the example), needs\n  to be extended with the concept of \"upstream port\", which is the\n  port on the switch chip that will bring us one hop closer to the CPU\n  (port 10 for both switch chips in the example above).\n\n- The dsa platform data needs to specify which ports on which switch\n  chips are links to other switch chips, so that we can enable DSA\n  tagging mode on them.  (For inter-switch links, we always use\n  non-EtherType DSA tagging, since it has lower overhead.  The CPU\n  link uses dsa or edsa tagging depending on what the \u0027root\u0027 switch\n  chip supports.)  This is done by specifying \"dsa\" for the given\n  port in the port array.\n\n- The dsa platform data needs to be extended with information on via\n  which port to reach any given switch chip from any given switch chip.\n  This info is specified via the per-switch chip data struct -\u003ertable[]\n  array, which gives the nexthop ports for each of the other switches\n  in the tree.\n\nFor the example topology above, the dsa platform data would look\nsomething like this:\n\n\tstatic struct dsa_chip_data sw[2] \u003d {\n\t\t{\n\t\t\t.mii_bus\t\u003d \u0026foo,\n\t\t\t.sw_addr\t\u003d 1,\n\t\t\t.port_names[0]\t\u003d \"p1\",\n\t\t\t.port_names[1]\t\u003d \"p2\",\n\t\t\t.port_names[2]\t\u003d \"p3\",\n\t\t\t.port_names[3]\t\u003d \"p4\",\n\t\t\t.port_names[4]\t\u003d \"p5\",\n\t\t\t.port_names[5]\t\u003d \"p6\",\n\t\t\t.port_names[6]\t\u003d \"p7\",\n\t\t\t.port_names[7]\t\u003d \"p8\",\n\t\t\t.port_names[9]\t\u003d \"dsa\",\n\t\t\t.port_names[10]\t\u003d \"cpu\",\n\t\t\t.rtable\t\t\u003d (s8 []){ -1, 9, },\n\t\t}, {\n\t\t\t.mii_bus\t\u003d \u0026foo,\n\t\t\t.sw_addr\t\u003d 2,\n\t\t\t.port_names[0]\t\u003d \"p9\",\n\t\t\t.port_names[1]\t\u003d \"p10\",\n\t\t\t.port_names[2]\t\u003d \"p11\",\n\t\t\t.port_names[3]\t\u003d \"p12\",\n\t\t\t.port_names[4]\t\u003d \"p13\",\n\t\t\t.port_names[5]\t\u003d \"p14\",\n\t\t\t.port_names[6]\t\u003d \"p15\",\n\t\t\t.port_names[7]\t\u003d \"p16\",\n\t\t\t.port_names[10]\t\u003d \"dsa\",\n\t\t\t.rtable\t\t\u003d (s8 []){ 10, -1, },\n\t\t},\n\t},\n\n\tstatic struct dsa_platform_data pd \u003d {\n\t\t.netdev\t\t\u003d \u0026foo,\n\t\t.nr_switches\t\u003d 2,\n\t\t.sw\t\t\u003d sw,\n\t};\n\nSigned-off-by: Lennert Buytenhek \u003cbuytenh@marvell.com\u003e\nTested-by: Gary Thomas \u003cgary@mlbassoc.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n",
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