)]}'
{
  "commit": "f1050a35cd99d6cfded7ce1273757dca84e92f9b",
  "tree": "cff53ccb259acaae0fe25f3caf396cc5df6426a7",
  "parents": [
    "8bb7c7af1ff2a9e9e0936dbdd15901c80329c7af"
  ],
  "author": {
    "name": "Kenji Kaneshige",
    "email": "kaneshige.kenji@jp.fujitsu.com",
    "time": "Thu Dec 20 19:45:09 2007 +0900"
  },
  "committer": {
    "name": "Greg Kroah-Hartman",
    "email": "gregkh@suse.de",
    "time": "Fri Feb 01 15:04:28 2008 -0800"
  },
  "message": "pciehp: workaround against Bad DLLP during power off\n\nSet Bad DLLP Mask bit in Correctable Error Mask Register during\nturning power off the slot.\n\nThis is the workaround against Bad DLLP error that sometimes happen\nduring turning power off on the slot which conforms to PCI Express\n1.0a spec. The cause of this error seems that PCI Express 1.0a spec\ndoesn\u0027t have the following consideration that was added to PCI Express\n1.1 spec.\n\n    \"If the port is associated with a hot-pluggable slot (Hot-Plug\n    Capable bit in the Slot Capabilities register set to 1b), and\n    Power Controller Control bit in Slot Control register is 1b(Off),\n    then any transition to DL Inactive must not be considered an\n    error.\"\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Kristen Carlson Accardi \u003ckristen.c.accardi@intel.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b2cde04ede1ad793a1c58d0a0cfcaa6691e75d33",
      "old_mode": 33188,
      "old_path": "drivers/pci/hotplug/pciehp_hpc.c",
      "new_id": "6eba9b2cfb90b359fc1fb92b45408846b4694f6f",
      "new_mode": 33188,
      "new_path": "drivers/pci/hotplug/pciehp_hpc.c"
    }
  ]
}