| /* |
| * phyCORE-MPC5200B-tiny (pcm030) board Device Tree Source |
| * |
| * Copyright 2006 Pengutronix |
| * Sascha Hauer <s.hauer@pengutronix.de> |
| * Copyright 2007 Pengutronix |
| * Juergen Beisert <j.beisert@pengutronix.de> |
| * |
| * This program is free software; you can redistribute it and/or modify it |
| * under the terms of the GNU General Public License as published by the |
| * Free Software Foundation; either version 2 of the License, or (at your |
| * option) any later version. |
| */ |
| |
| /dts-v1/; |
| |
| / { |
| model = "phytec,pcm030"; |
| compatible = "phytec,pcm030"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| interrupt-parent = <&mpc5200_pic>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| PowerPC,5200@0 { |
| device_type = "cpu"; |
| reg = <0>; |
| d-cache-line-size = <32>; |
| i-cache-line-size = <32>; |
| d-cache-size = <0x4000>; // L1, 16K |
| i-cache-size = <0x4000>; // L1, 16K |
| timebase-frequency = <0>; // from bootloader |
| bus-frequency = <0>; // from bootloader |
| clock-frequency = <0>; // from bootloader |
| }; |
| }; |
| |
| memory { |
| device_type = "memory"; |
| reg = <0x00000000 0x04000000>; // 64MB |
| }; |
| |
| soc5200@f0000000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "fsl,mpc5200b-immr"; |
| ranges = <0 0xf0000000 0x0000c000>; |
| bus-frequency = <0>; // from bootloader |
| system-frequency = <0>; // from bootloader |
| |
| cdm@200 { |
| compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; |
| reg = <0x200 0x38>; |
| }; |
| |
| mpc5200_pic: interrupt-controller@500 { |
| // 5200 interrupts are encoded into two levels; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; |
| reg = <0x500 0x80>; |
| }; |
| |
| timer@600 { // General Purpose Timer |
| compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| reg = <0x600 0x10>; |
| interrupts = <1 9 0>; |
| fsl,has-wdt; |
| }; |
| |
| timer@610 { // General Purpose Timer |
| compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; |
| reg = <0x610 0x10>; |
| interrupts = <1 10 0>; |
| }; |
| |
| gpt2: timer@620 { // General Purpose Timer in GPIO mode |
| compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; |
| reg = <0x620 0x10>; |
| interrupts = <1 11 0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| gpt3: timer@630 { // General Purpose Timer in GPIO mode |
| compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; |
| reg = <0x630 0x10>; |
| interrupts = <1 12 0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| gpt4: timer@640 { // General Purpose Timer in GPIO mode |
| compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; |
| reg = <0x640 0x10>; |
| interrupts = <1 13 0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| gpt5: timer@650 { // General Purpose Timer in GPIO mode |
| compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; |
| reg = <0x650 0x10>; |
| interrupts = <1 14 0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| gpt6: timer@660 { // General Purpose Timer in GPIO mode |
| compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; |
| reg = <0x660 0x10>; |
| interrupts = <1 15 0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| gpt7: timer@670 { // General Purpose Timer in GPIO mode |
| compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; |
| reg = <0x670 0x10>; |
| interrupts = <1 16 0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| rtc@800 { // Real time clock |
| compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; |
| reg = <0x800 0x100>; |
| interrupts = <1 5 0 1 6 0>; |
| }; |
| |
| can@900 { |
| compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; |
| interrupts = <2 17 0>; |
| reg = <0x900 0x80>; |
| }; |
| |
| can@980 { |
| compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; |
| interrupts = <2 18 0>; |
| reg = <0x980 0x80>; |
| }; |
| |
| gpio_simple: gpio@b00 { |
| compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; |
| reg = <0xb00 0x40>; |
| interrupts = <1 7 0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| gpio_wkup: gpio@c00 { |
| compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; |
| reg = <0xc00 0x40>; |
| interrupts = <1 8 0 0 3 0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| spi@f00 { |
| compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; |
| reg = <0xf00 0x20>; |
| interrupts = <2 13 0 2 14 0>; |
| }; |
| |
| usb@1000 { |
| compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; |
| reg = <0x1000 0xff>; |
| interrupts = <2 6 0>; |
| }; |
| |
| dma-controller@1200 { |
| compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; |
| reg = <0x1200 0x80>; |
| interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 |
| 3 4 0 3 5 0 3 6 0 3 7 0 |
| 3 8 0 3 9 0 3 10 0 3 11 0 |
| 3 12 0 3 13 0 3 14 0 3 15 0>; |
| }; |
| |
| xlb@1f00 { |
| compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; |
| reg = <0x1f00 0x100>; |
| }; |
| |
| ac97@2000 { /* PSC1 in ac97 mode */ |
| compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97"; |
| cell-index = <0>; |
| reg = <0x2000 0x100>; |
| interrupts = <2 1 0>; |
| }; |
| |
| /* PSC2 port is used by CAN1/2 */ |
| |
| serial@2400 { /* PSC3 in UART mode */ |
| compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; |
| cell-index = <2>; |
| reg = <0x2400 0x100>; |
| interrupts = <2 3 0>; |
| }; |
| |
| /* PSC4 is ??? */ |
| |
| /* PSC5 is ??? */ |
| |
| serial@2c00 { /* PSC6 in UART mode */ |
| compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; |
| cell-index = <5>; |
| reg = <0x2c00 0x100>; |
| interrupts = <2 4 0>; |
| }; |
| |
| ethernet@3000 { |
| compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; |
| reg = <0x3000 0x400>; |
| local-mac-address = [ 00 00 00 00 00 00 ]; |
| interrupts = <2 5 0>; |
| phy-handle = <&phy0>; |
| }; |
| |
| mdio@3000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; |
| reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts |
| interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. |
| |
| phy0: ethernet-phy@0 { |
| reg = <0>; |
| }; |
| }; |
| |
| ata@3a00 { |
| compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; |
| reg = <0x3a00 0x100>; |
| interrupts = <2 7 0>; |
| }; |
| |
| i2c@3d00 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; |
| reg = <0x3d00 0x40>; |
| interrupts = <2 15 0>; |
| fsl5200-clocking; |
| }; |
| |
| i2c@3d40 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; |
| reg = <0x3d40 0x40>; |
| interrupts = <2 16 0>; |
| fsl5200-clocking; |
| rtc@51 { |
| compatible = "nxp,pcf8563"; |
| reg = <0x51>; |
| }; |
| eeprom@52 { |
| compatible = "catalyst,24c32"; |
| reg = <0x52>; |
| }; |
| }; |
| |
| sram@8000 { |
| compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; |
| reg = <0x8000 0x4000>; |
| }; |
| }; |
| |
| pci@f0000d00 { |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| device_type = "pci"; |
| compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; |
| reg = <0xf0000d00 0x100>; |
| interrupt-map-mask = <0xf800 0 0 7>; |
| interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot |
| 0xc000 0 0 2 &mpc5200_pic 1 1 3 |
| 0xc000 0 0 3 &mpc5200_pic 1 2 3 |
| 0xc000 0 0 4 &mpc5200_pic 1 3 3 |
| |
| 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot |
| 0xc800 0 0 2 &mpc5200_pic 1 2 3 |
| 0xc800 0 0 3 &mpc5200_pic 1 3 3 |
| 0xc800 0 0 4 &mpc5200_pic 0 0 3>; |
| clock-frequency = <0>; // From boot loader |
| interrupts = <2 8 0 2 9 0 2 10 0>; |
| bus-range = <0 0>; |
| ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 |
| 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 |
| 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; |
| }; |
| }; |