ARM: tegra: Switch to new pinctrl driver
* Rename old pinmux and new pinctrl platform driver and DT match table
entries, so the new driver gets instantiated.
* Re-write board-pinmux.c, so that it uses pinctrl APIs to configura the
pinmux.
* Re-write board-*-pinmux.c so that the pinmux configuration tables are
in pinctrl format.
Ventana's pin mux table needed some edits on top of the basic format
conversion, since some mux options that were previously marked as
reserved are now valid in the new pinctrl driver. Attempting to use the
old reserved names will result in a failure. Specifically, groups lpw0,
lpw2, lsc1, lsck, and lsda were changed from function rsvd4 to displaya,
and group pta was changed from function rsvd2 to hdmi.
All boards' pin mux tables needed some edits on top of the based format
conversion, since function i2c was split into i2c1 (first general I2C
controller) and i2cp (power I2C controller) to better align function
definitions with HW blocks.
Due to the split of mux tables into pure mux and pull/tristate tables,
many entries in the separate Seaboard/Ventana tables could be merged
into the common table, since the entries differed only in the portion
in one of the tables, not both.
Most pin groups allow configuration of mux, tri-state, and pull. However,
some don't allow pull configuration, which is instead configured by new
groups that only allow pull configuration. This is a reflection of the
true HW capabilities, which weren't fully represented by the old pinmux
driver. This required adding new pull table entries for those new groups,
and setting many other entries' pull configuration to
TEGRA_PINCONFIG_DONT_SET.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 3ebe2c8..83d420f 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -2,6 +2,7 @@
* arch/arm/mach-tegra/board-harmony-pinmux.c
*
* Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -15,136 +16,138 @@
*/
#include <linux/kernel.h>
-#include <linux/of.h>
-
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>
#include "board-harmony.h"
#include "board-pinmux.h"
-static struct tegra_pingroup_config harmony_pinmux[] = {
- {TEGRA_PINGROUP_ATA, TEGRA_MUX_IDE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DTA, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DTB, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DTC, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DTD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GPU, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_KBCA, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCB, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCD, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LCSN, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
- {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+static struct pinctrl_map harmony_map[] = {
+ TEGRA_MAP_MUXCONF("ata", "ide", none, driven),
+ TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
+ TEGRA_MAP_MUXCONF("atc", "nand", none, driven),
+ TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
+ TEGRA_MAP_MUXCONF("ate", "gmi", none, driven),
+ TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
+ TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate),
+ TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
+ TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate),
+ TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
+ TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate),
+ TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
+ TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
+ TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
+ TEGRA_MAP_MUXCONF("dta", "sdio2", up, driven),
+ TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, driven),
+ TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate),
+ TEGRA_MAP_MUXCONF("dtd", "sdio2", up, driven),
+ TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate),
+ TEGRA_MAP_MUXCONF("dtf", "i2c3", none, tristate),
+ TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
+ TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven),
+ TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven),
+ TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven),
+ TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
+ TEGRA_MAP_MUXCONF("gpu", "gmi", none, tristate),
+ TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
+ TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
+ TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
+ TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
+ TEGRA_MAP_MUXCONF("irrx", "uarta", up, tristate),
+ TEGRA_MAP_MUXCONF("irtx", "uarta", up, tristate),
+ TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
+ TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven),
+ TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
+ TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven),
+ TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
+ TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
+ TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
+ TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate),
+ TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
+ TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
+ TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
+ TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
+ TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
+ TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
+ TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
+ TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
+ TEGRA_MAP_MUXCONF("owc", "rsvd2", na, tristate),
+ TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
+ TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
+ TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
+ TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate),
+ TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven),
+ TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate),
+ TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, tristate),
+ TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven),
+ TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate),
+ TEGRA_MAP_MUXCONF("slxd", "spdif", none, tristate),
+ TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
+ TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate),
+ TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, tristate),
+ TEGRA_MAP_MUXCONF("spia", "gmi", none, driven),
+ TEGRA_MAP_MUXCONF("spib", "gmi", none, driven),
+ TEGRA_MAP_MUXCONF("spic", "gmi", up, tristate),
+ TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate),
+ TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate),
+ TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
+ TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate),
+ TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
+ TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate),
+ TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate),
+ TEGRA_MAP_MUXCONF("uac", "rsvd2", none, tristate),
+ TEGRA_MAP_MUXCONF("uad", "irda", up, tristate),
+ TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
+ TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
+ TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate),
+ TEGRA_MAP_CONF("ck32", none, na),
+ TEGRA_MAP_CONF("ddrc", none, na),
+ TEGRA_MAP_CONF("pmca", none, na),
+ TEGRA_MAP_CONF("pmcb", none, na),
+ TEGRA_MAP_CONF("pmcc", none, na),
+ TEGRA_MAP_CONF("pmcd", none, na),
+ TEGRA_MAP_CONF("pmce", none, na),
+ TEGRA_MAP_CONF("xm2c", none, na),
+ TEGRA_MAP_CONF("xm2d", none, na),
+ TEGRA_MAP_CONF("ls", up, na),
+ TEGRA_MAP_CONF("lc", up, na),
+ TEGRA_MAP_CONF("ld17_0", down, na),
+ TEGRA_MAP_CONF("ld19_18", down, na),
+ TEGRA_MAP_CONF("ld21_20", down, na),
+ TEGRA_MAP_CONF("ld23_22", down, na),
};
static struct tegra_board_pinmux_conf conf = {
- .pgs = harmony_pinmux,
- .pg_count = ARRAY_SIZE(harmony_pinmux),
+ .maps = harmony_map,
+ .map_count = ARRAY_SIZE(harmony_map),
};
void harmony_pinmux_init(void)