drm/radeon: fix endian bugs in radeon_atom_get_clock_dividers() (v3)
v2: fix copy paste typo.
v3: clarify new union member
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index 4b04ba3..0ee5737 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -458,6 +458,7 @@
union
{
ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
+ ULONG ulClockParams; //ULONG access for BE
ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
};
UCHAR ucRefDiv; //Output Parameter
@@ -490,6 +491,7 @@
union
{
ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
+ ULONG ulClockParams; //ULONG access for BE
ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
};
UCHAR ucRefDiv; //Output Parameter
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 8c1779c..0dd87c0 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -2710,8 +2710,7 @@
dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
} else {
if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
- args.v3.ulClock.ulComputeClockFlag = clock_type;
- args.v3.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
+ args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
@@ -2726,8 +2725,7 @@
dividers->vco_mode = (args.v3.ucCntlFlag &
ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
} else {
- args.v5.ulClock.ulComputeClockFlag = clock_type;
- args.v5.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
+ args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
if (strobe_mode)
args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;