arch/tile: Enable more sophisticated IRQ model for 32-bit chips.
This model is based on the on-chip interrupt model used by the
TILE-Gx next-generation hardware, and interacts much more cleanly
with the Linux generic IRQ layer.
The change includes modifications to the Tilera hypervisor, which
are reflected in the hypervisor headers in arch/tile/include/arch/.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
diff --git a/arch/tile/include/asm/smp.h b/arch/tile/include/asm/smp.h
index da24858..532124a 100644
--- a/arch/tile/include/asm/smp.h
+++ b/arch/tile/include/asm/smp.h
@@ -20,6 +20,7 @@
#include <asm/processor.h>
#include <linux/cpumask.h>
#include <linux/irqreturn.h>
+#include <hv/hypervisor.h>
/* Set up this tile to support receiving hypervisor messages */
void init_messaging(void);
@@ -39,9 +40,6 @@
/* Process an IPI message */
void evaluate_message(int tag);
-/* Process an IRQ_RESCHEDULE IPI. */
-irqreturn_t handle_reschedule_ipi(int irq, void *token);
-
/* Boot a secondary cpu */
void online_secondary(void);
@@ -56,6 +54,20 @@
#define smp_height (smp_topology.height)
#define smp_width (smp_topology.width)
+/* Convenience functions for converting cpu <-> coords. */
+static inline int cpu_x(int cpu)
+{
+ return cpu % smp_width;
+}
+static inline int cpu_y(int cpu)
+{
+ return cpu / smp_width;
+}
+static inline int xy_to_cpu(int x, int y)
+{
+ return y * smp_width + x;
+}
+
/* Hypervisor message tags sent via the tile send_IPI*() routines. */
#define MSG_TAG_START_CPU 1
#define MSG_TAG_STOP_CPU 2
@@ -85,6 +97,9 @@
#define smp_master_cpu 0
#define smp_height 1
#define smp_width 1
+#define cpu_x(cpu) 0
+#define cpu_y(cpu) 0
+#define xy_to_cpu(x, y) 0
#endif /* !CONFIG_SMP */
@@ -123,4 +138,10 @@
return bitmap_parselist_crop(buf, cpumask_bits(dstp), nbits);
}
+/* Initialize the IPI subsystem. */
+void ipi_init(void);
+
+/* Function for start-cpu message to cause us to jump to. */
+extern unsigned long start_cpu_function_addr;
+
#endif /* _ASM_TILE_SMP_H */