MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.
Some CPUs have implementation dependent rdhwr registers. Allow them
to be enabled on a per CPU basis.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 1cba4b2..8ab1d12 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -234,4 +234,8 @@
#define cpu_scache_line_size() cpu_data[0].scache.linesz
#endif
+#ifndef cpu_hwrena_impl_bits
+#define cpu_hwrena_impl_bits 0
+#endif
+
#endif /* __ASM_CPU_FEATURES_H */