[SPARC64]: Add explicit register args to trap state loading macros.
This, as well as making the code cleaner, allows a simplification in
the TSB miss handling path.
Signed-off-by: David S. Miller <davem@davemloft.net>
diff --git a/arch/sparc64/kernel/rtrap.S b/arch/sparc64/kernel/rtrap.S
index 64bc036..61bd45e 100644
--- a/arch/sparc64/kernel/rtrap.S
+++ b/arch/sparc64/kernel/rtrap.S
@@ -226,7 +226,7 @@
brz,pt %l3, 1f
nop
/* Must do this before thread reg is clobbered below. */
- LOAD_PER_CPU_BASE(%i0, %i1, %i2)
+ LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
1:
ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7