Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Based on arch/arm/kernel/process.c |
| 3 | * |
| 4 | * Original Copyright (C) 1995 Linus Torvalds |
| 5 | * Copyright (C) 1996-2000 Russell King - Converted to ARM. |
| 6 | * Copyright (C) 2012 ARM Ltd. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include <stdarg.h> |
| 22 | |
| 23 | #include <linux/export.h> |
| 24 | #include <linux/sched.h> |
| 25 | #include <linux/kernel.h> |
| 26 | #include <linux/mm.h> |
| 27 | #include <linux/stddef.h> |
| 28 | #include <linux/unistd.h> |
| 29 | #include <linux/user.h> |
| 30 | #include <linux/delay.h> |
| 31 | #include <linux/reboot.h> |
| 32 | #include <linux/interrupt.h> |
| 33 | #include <linux/kallsyms.h> |
| 34 | #include <linux/init.h> |
| 35 | #include <linux/cpu.h> |
| 36 | #include <linux/elfcore.h> |
| 37 | #include <linux/pm.h> |
| 38 | #include <linux/tick.h> |
| 39 | #include <linux/utsname.h> |
| 40 | #include <linux/uaccess.h> |
| 41 | #include <linux/random.h> |
| 42 | #include <linux/hw_breakpoint.h> |
| 43 | #include <linux/personality.h> |
| 44 | #include <linux/notifier.h> |
| 45 | |
| 46 | #include <asm/compat.h> |
| 47 | #include <asm/cacheflush.h> |
Will Deacon | ec45d1c | 2013-01-17 12:31:45 +0000 | [diff] [blame] | 48 | #include <asm/fpsimd.h> |
| 49 | #include <asm/mmu_context.h> |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 50 | #include <asm/processor.h> |
| 51 | #include <asm/stacktrace.h> |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 52 | |
| 53 | static void setup_restart(void) |
| 54 | { |
| 55 | /* |
| 56 | * Tell the mm system that we are going to reboot - |
| 57 | * we may need it to insert some 1:1 mappings so that |
| 58 | * soft boot works. |
| 59 | */ |
| 60 | setup_mm_for_reboot(); |
| 61 | |
| 62 | /* Clean and invalidate caches */ |
| 63 | flush_cache_all(); |
| 64 | |
| 65 | /* Turn D-cache off */ |
| 66 | cpu_cache_off(); |
| 67 | |
| 68 | /* Push out any further dirty data, and ensure cache is empty */ |
| 69 | flush_cache_all(); |
| 70 | } |
| 71 | |
| 72 | void soft_restart(unsigned long addr) |
| 73 | { |
| 74 | setup_restart(); |
| 75 | cpu_reset(addr); |
| 76 | } |
| 77 | |
| 78 | /* |
| 79 | * Function pointers to optional machine specific functions |
| 80 | */ |
| 81 | void (*pm_power_off)(void); |
| 82 | EXPORT_SYMBOL_GPL(pm_power_off); |
| 83 | |
| 84 | void (*pm_restart)(const char *cmd); |
| 85 | EXPORT_SYMBOL_GPL(pm_restart); |
| 86 | |
Thomas Gleixner | 0087298 | 2013-03-21 22:49:39 +0100 | [diff] [blame^] | 87 | void arch_cpu_idle_prepare(void) |
| 88 | { |
| 89 | local_fiq_enable(); |
| 90 | } |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 91 | |
| 92 | /* |
| 93 | * This is our default idle handler. |
| 94 | */ |
Thomas Gleixner | 0087298 | 2013-03-21 22:49:39 +0100 | [diff] [blame^] | 95 | void arch_cpu_idle(void) |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 96 | { |
| 97 | /* |
| 98 | * This should do all the clock switching and wait for interrupt |
| 99 | * tricks |
| 100 | */ |
| 101 | cpu_do_idle(); |
| 102 | local_irq_enable(); |
| 103 | } |
| 104 | |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 105 | void machine_shutdown(void) |
| 106 | { |
| 107 | #ifdef CONFIG_SMP |
| 108 | smp_send_stop(); |
| 109 | #endif |
| 110 | } |
| 111 | |
| 112 | void machine_halt(void) |
| 113 | { |
| 114 | machine_shutdown(); |
| 115 | while (1); |
| 116 | } |
| 117 | |
| 118 | void machine_power_off(void) |
| 119 | { |
| 120 | machine_shutdown(); |
| 121 | if (pm_power_off) |
| 122 | pm_power_off(); |
| 123 | } |
| 124 | |
| 125 | void machine_restart(char *cmd) |
| 126 | { |
| 127 | machine_shutdown(); |
| 128 | |
| 129 | /* Disable interrupts first */ |
| 130 | local_irq_disable(); |
| 131 | local_fiq_disable(); |
| 132 | |
| 133 | /* Now call the architecture specific reboot code. */ |
| 134 | if (pm_restart) |
| 135 | pm_restart(cmd); |
| 136 | |
| 137 | /* |
| 138 | * Whoops - the architecture was unable to reboot. |
| 139 | */ |
| 140 | printk("Reboot failed -- System halted\n"); |
| 141 | while (1); |
| 142 | } |
| 143 | |
| 144 | void __show_regs(struct pt_regs *regs) |
| 145 | { |
| 146 | int i; |
| 147 | |
| 148 | printk("CPU: %d %s (%s %.*s)\n", |
| 149 | raw_smp_processor_id(), print_tainted(), |
| 150 | init_utsname()->release, |
| 151 | (int)strcspn(init_utsname()->version, " "), |
| 152 | init_utsname()->version); |
| 153 | print_symbol("PC is at %s\n", instruction_pointer(regs)); |
| 154 | print_symbol("LR is at %s\n", regs->regs[30]); |
| 155 | printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n", |
| 156 | regs->pc, regs->regs[30], regs->pstate); |
| 157 | printk("sp : %016llx\n", regs->sp); |
| 158 | for (i = 29; i >= 0; i--) { |
| 159 | printk("x%-2d: %016llx ", i, regs->regs[i]); |
| 160 | if (i % 2 == 0) |
| 161 | printk("\n"); |
| 162 | } |
| 163 | printk("\n"); |
| 164 | } |
| 165 | |
| 166 | void show_regs(struct pt_regs * regs) |
| 167 | { |
| 168 | printk("\n"); |
| 169 | printk("Pid: %d, comm: %20s\n", task_pid_nr(current), current->comm); |
| 170 | __show_regs(regs); |
| 171 | } |
| 172 | |
| 173 | /* |
| 174 | * Free current thread data structures etc.. |
| 175 | */ |
| 176 | void exit_thread(void) |
| 177 | { |
| 178 | } |
| 179 | |
| 180 | void flush_thread(void) |
| 181 | { |
| 182 | fpsimd_flush_thread(); |
| 183 | flush_ptrace_hw_breakpoint(current); |
| 184 | } |
| 185 | |
| 186 | void release_thread(struct task_struct *dead_task) |
| 187 | { |
| 188 | } |
| 189 | |
| 190 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
| 191 | { |
| 192 | fpsimd_save_state(¤t->thread.fpsimd_state); |
| 193 | *dst = *src; |
| 194 | return 0; |
| 195 | } |
| 196 | |
| 197 | asmlinkage void ret_from_fork(void) asm("ret_from_fork"); |
| 198 | |
| 199 | int copy_thread(unsigned long clone_flags, unsigned long stack_start, |
Al Viro | afa86fc | 2012-10-22 22:51:14 -0400 | [diff] [blame] | 200 | unsigned long stk_sz, struct task_struct *p) |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 201 | { |
| 202 | struct pt_regs *childregs = task_pt_regs(p); |
| 203 | unsigned long tls = p->thread.tp_value; |
| 204 | |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 205 | memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context)); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 206 | |
Al Viro | 9ac0800 | 2012-10-21 15:56:52 -0400 | [diff] [blame] | 207 | if (likely(!(p->flags & PF_KTHREAD))) { |
| 208 | *childregs = *current_pt_regs(); |
Catalin Marinas | c34501d | 2012-10-05 12:31:20 +0100 | [diff] [blame] | 209 | childregs->regs[0] = 0; |
| 210 | if (is_compat_thread(task_thread_info(p))) { |
Al Viro | e0fd18c | 2012-10-18 00:55:54 -0400 | [diff] [blame] | 211 | if (stack_start) |
| 212 | childregs->compat_sp = stack_start; |
Catalin Marinas | c34501d | 2012-10-05 12:31:20 +0100 | [diff] [blame] | 213 | } else { |
| 214 | /* |
| 215 | * Read the current TLS pointer from tpidr_el0 as it may be |
| 216 | * out-of-sync with the saved value. |
| 217 | */ |
| 218 | asm("mrs %0, tpidr_el0" : "=r" (tls)); |
Al Viro | e0fd18c | 2012-10-18 00:55:54 -0400 | [diff] [blame] | 219 | if (stack_start) { |
| 220 | /* 16-byte aligned stack mandatory on AArch64 */ |
| 221 | if (stack_start & 15) |
| 222 | return -EINVAL; |
| 223 | childregs->sp = stack_start; |
| 224 | } |
Catalin Marinas | c34501d | 2012-10-05 12:31:20 +0100 | [diff] [blame] | 225 | } |
| 226 | /* |
| 227 | * If a TLS pointer was passed to clone (4th argument), use it |
| 228 | * for the new thread. |
| 229 | */ |
| 230 | if (clone_flags & CLONE_SETTLS) |
Al Viro | 9ac0800 | 2012-10-21 15:56:52 -0400 | [diff] [blame] | 231 | tls = childregs->regs[3]; |
Catalin Marinas | c34501d | 2012-10-05 12:31:20 +0100 | [diff] [blame] | 232 | } else { |
| 233 | memset(childregs, 0, sizeof(struct pt_regs)); |
| 234 | childregs->pstate = PSR_MODE_EL1h; |
| 235 | p->thread.cpu_context.x19 = stack_start; |
| 236 | p->thread.cpu_context.x20 = stk_sz; |
| 237 | } |
| 238 | p->thread.cpu_context.pc = (unsigned long)ret_from_fork; |
| 239 | p->thread.cpu_context.sp = (unsigned long)childregs; |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 240 | p->thread.tp_value = tls; |
| 241 | |
| 242 | ptrace_hw_copy_thread(p); |
| 243 | |
| 244 | return 0; |
| 245 | } |
| 246 | |
| 247 | static void tls_thread_switch(struct task_struct *next) |
| 248 | { |
| 249 | unsigned long tpidr, tpidrro; |
| 250 | |
| 251 | if (!is_compat_task()) { |
| 252 | asm("mrs %0, tpidr_el0" : "=r" (tpidr)); |
| 253 | current->thread.tp_value = tpidr; |
| 254 | } |
| 255 | |
| 256 | if (is_compat_thread(task_thread_info(next))) { |
| 257 | tpidr = 0; |
| 258 | tpidrro = next->thread.tp_value; |
| 259 | } else { |
| 260 | tpidr = next->thread.tp_value; |
| 261 | tpidrro = 0; |
| 262 | } |
| 263 | |
| 264 | asm( |
| 265 | " msr tpidr_el0, %0\n" |
| 266 | " msr tpidrro_el0, %1" |
| 267 | : : "r" (tpidr), "r" (tpidrro)); |
| 268 | } |
| 269 | |
| 270 | /* |
| 271 | * Thread switching. |
| 272 | */ |
| 273 | struct task_struct *__switch_to(struct task_struct *prev, |
| 274 | struct task_struct *next) |
| 275 | { |
| 276 | struct task_struct *last; |
| 277 | |
| 278 | fpsimd_thread_switch(next); |
| 279 | tls_thread_switch(next); |
| 280 | hw_breakpoint_thread_switch(next); |
| 281 | |
| 282 | /* the actual thread switch */ |
| 283 | last = cpu_switch_to(prev, next); |
| 284 | |
Will Deacon | ec45d1c | 2013-01-17 12:31:45 +0000 | [diff] [blame] | 285 | contextidr_thread_switch(next); |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 286 | return last; |
| 287 | } |
| 288 | |
Catalin Marinas | b3901d5 | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 289 | unsigned long get_wchan(struct task_struct *p) |
| 290 | { |
| 291 | struct stackframe frame; |
| 292 | int count = 0; |
| 293 | if (!p || p == current || p->state == TASK_RUNNING) |
| 294 | return 0; |
| 295 | |
| 296 | frame.fp = thread_saved_fp(p); |
| 297 | frame.sp = thread_saved_sp(p); |
| 298 | frame.pc = thread_saved_pc(p); |
| 299 | do { |
| 300 | int ret = unwind_frame(&frame); |
| 301 | if (ret < 0) |
| 302 | return 0; |
| 303 | if (!in_sched_functions(frame.pc)) |
| 304 | return frame.pc; |
| 305 | } while (count ++ < 16); |
| 306 | return 0; |
| 307 | } |
| 308 | |
| 309 | unsigned long arch_align_stack(unsigned long sp) |
| 310 | { |
| 311 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) |
| 312 | sp -= get_random_int() & ~PAGE_MASK; |
| 313 | return sp & ~0xf; |
| 314 | } |
| 315 | |
| 316 | static unsigned long randomize_base(unsigned long base) |
| 317 | { |
| 318 | unsigned long range_end = base + (STACK_RND_MASK << PAGE_SHIFT) + 1; |
| 319 | return randomize_range(base, range_end, 0) ? : base; |
| 320 | } |
| 321 | |
| 322 | unsigned long arch_randomize_brk(struct mm_struct *mm) |
| 323 | { |
| 324 | return randomize_base(mm->brk); |
| 325 | } |
| 326 | |
| 327 | unsigned long randomize_et_dyn(unsigned long base) |
| 328 | { |
| 329 | return randomize_base(base); |
| 330 | } |