Blame - include/linux/mfd/wm831x/irq.h - android_kernel_oneplus_msm8996

Mark Brown

7d4d0a3

2009-07-27 14:45:53 +0100

[diff] [blame]

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/*

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* include/linux/mfd/wm831x/irq.h -- Interrupt controller for WM831x

*

*

* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>

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*

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* This program is free software; you can redistribute it and/or modify it

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* under the terms of the GNU General Public License as published by the

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* Free Software Foundation; either version 2 of the License, or (at your

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* option) any later version.

*

*/

#ifndef __MFD_WM831X_IRQ_H__

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#define __MFD_WM831X_IRQ_H__

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/* Interrupt number assignments within Linux */

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#define WM831X_IRQ_TEMP_THW 0

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#define WM831X_IRQ_GPIO_1 1

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#define WM831X_IRQ_GPIO_2 2

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#define WM831X_IRQ_GPIO_3 3

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#define WM831X_IRQ_GPIO_4 4

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#define WM831X_IRQ_GPIO_5 5

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#define WM831X_IRQ_GPIO_6 6

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#define WM831X_IRQ_GPIO_7 7

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#define WM831X_IRQ_GPIO_8 8

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#define WM831X_IRQ_GPIO_9 9

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#define WM831X_IRQ_GPIO_10 10

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#define WM831X_IRQ_GPIO_11 11

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#define WM831X_IRQ_GPIO_12 12

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#define WM831X_IRQ_GPIO_13 13

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#define WM831X_IRQ_GPIO_14 14

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#define WM831X_IRQ_GPIO_15 15

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#define WM831X_IRQ_GPIO_16 16

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#define WM831X_IRQ_ON 17

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#define WM831X_IRQ_PPM_SYSLO 18

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#define WM831X_IRQ_PPM_PWR_SRC 19

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#define WM831X_IRQ_PPM_USB_CURR 20

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#define WM831X_IRQ_WDOG_TO 21

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#define WM831X_IRQ_RTC_PER 22

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#define WM831X_IRQ_RTC_ALM 23

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#define WM831X_IRQ_CHG_BATT_HOT 24

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#define WM831X_IRQ_CHG_BATT_COLD 25

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#define WM831X_IRQ_CHG_BATT_FAIL 26

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#define WM831X_IRQ_CHG_OV 27

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#define WM831X_IRQ_CHG_END 29

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#define WM831X_IRQ_CHG_TO 30

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#define WM831X_IRQ_CHG_MODE 31

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#define WM831X_IRQ_CHG_START 32

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#define WM831X_IRQ_TCHDATA 33

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#define WM831X_IRQ_TCHPD 34

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#define WM831X_IRQ_AUXADC_DATA 35

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#define WM831X_IRQ_AUXADC_DCOMP1 36

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#define WM831X_IRQ_AUXADC_DCOMP2 37

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#define WM831X_IRQ_AUXADC_DCOMP3 38

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#define WM831X_IRQ_AUXADC_DCOMP4 39

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#define WM831X_IRQ_CS1 40

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#define WM831X_IRQ_CS2 41

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#define WM831X_IRQ_HC_DC1 42

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#define WM831X_IRQ_HC_DC2 43

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#define WM831X_IRQ_UV_LDO1 44

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#define WM831X_IRQ_UV_LDO2 45

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#define WM831X_IRQ_UV_LDO3 46

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#define WM831X_IRQ_UV_LDO4 47

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#define WM831X_IRQ_UV_LDO5 48

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#define WM831X_IRQ_UV_LDO6 49

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#define WM831X_IRQ_UV_LDO7 50

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#define WM831X_IRQ_UV_LDO8 51

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#define WM831X_IRQ_UV_LDO9 52

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#define WM831X_IRQ_UV_LDO10 53

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#define WM831X_IRQ_UV_DC1 54

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#define WM831X_IRQ_UV_DC2 55

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#define WM831X_IRQ_UV_DC3 56

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#define WM831X_IRQ_UV_DC4 57

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#define WM831X_NUM_IRQS 58

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/*

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* R16400 (0x4010) - System Interrupts

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*/

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#define WM831X_PS_INT 0x8000 /* PS_INT */

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#define WM831X_PS_INT_MASK 0x8000 /* PS_INT */

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#define WM831X_PS_INT_SHIFT 15 /* PS_INT */

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#define WM831X_PS_INT_WIDTH 1 /* PS_INT */

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#define WM831X_TEMP_INT 0x4000 /* TEMP_INT */

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#define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */

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#define WM831X_TEMP_INT_SHIFT 14 /* TEMP_INT */

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#define WM831X_TEMP_INT_WIDTH 1 /* TEMP_INT */

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#define WM831X_GP_INT 0x2000 /* GP_INT */

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#define WM831X_GP_INT_MASK 0x2000 /* GP_INT */

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#define WM831X_GP_INT_SHIFT 13 /* GP_INT */

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#define WM831X_GP_INT_WIDTH 1 /* GP_INT */

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#define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */

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#define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */

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#define WM831X_ON_PIN_INT_SHIFT 12 /* ON_PIN_INT */

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#define WM831X_ON_PIN_INT_WIDTH 1 /* ON_PIN_INT */

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#define WM831X_WDOG_INT 0x0800 /* WDOG_INT */

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#define WM831X_WDOG_INT_MASK 0x0800 /* WDOG_INT */

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#define WM831X_WDOG_INT_SHIFT 11 /* WDOG_INT */

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#define WM831X_WDOG_INT_WIDTH 1 /* WDOG_INT */

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#define WM831X_TCHDATA_INT 0x0400 /* TCHDATA_INT */

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#define WM831X_TCHDATA_INT_MASK 0x0400 /* TCHDATA_INT */

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#define WM831X_TCHDATA_INT_SHIFT 10 /* TCHDATA_INT */

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#define WM831X_TCHDATA_INT_WIDTH 1 /* TCHDATA_INT */

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#define WM831X_TCHPD_INT 0x0200 /* TCHPD_INT */

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#define WM831X_TCHPD_INT_MASK 0x0200 /* TCHPD_INT */

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#define WM831X_TCHPD_INT_SHIFT 9 /* TCHPD_INT */

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#define WM831X_TCHPD_INT_WIDTH 1 /* TCHPD_INT */

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#define WM831X_AUXADC_INT 0x0100 /* AUXADC_INT */

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#define WM831X_AUXADC_INT_MASK 0x0100 /* AUXADC_INT */

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#define WM831X_AUXADC_INT_SHIFT 8 /* AUXADC_INT */

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#define WM831X_AUXADC_INT_WIDTH 1 /* AUXADC_INT */

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#define WM831X_PPM_INT 0x0080 /* PPM_INT */

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#define WM831X_PPM_INT_MASK 0x0080 /* PPM_INT */

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#define WM831X_PPM_INT_SHIFT 7 /* PPM_INT */

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#define WM831X_PPM_INT_WIDTH 1 /* PPM_INT */

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#define WM831X_CS_INT 0x0040 /* CS_INT */

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#define WM831X_CS_INT_MASK 0x0040 /* CS_INT */

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#define WM831X_CS_INT_SHIFT 6 /* CS_INT */

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#define WM831X_CS_INT_WIDTH 1 /* CS_INT */

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#define WM831X_RTC_INT 0x0020 /* RTC_INT */

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#define WM831X_RTC_INT_MASK 0x0020 /* RTC_INT */

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#define WM831X_RTC_INT_SHIFT 5 /* RTC_INT */

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#define WM831X_RTC_INT_WIDTH 1 /* RTC_INT */

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#define WM831X_OTP_INT 0x0010 /* OTP_INT */

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#define WM831X_OTP_INT_MASK 0x0010 /* OTP_INT */

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#define WM831X_OTP_INT_SHIFT 4 /* OTP_INT */

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#define WM831X_OTP_INT_WIDTH 1 /* OTP_INT */

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#define WM831X_CHILD_INT 0x0008 /* CHILD_INT */

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#define WM831X_CHILD_INT_MASK 0x0008 /* CHILD_INT */

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#define WM831X_CHILD_INT_SHIFT 3 /* CHILD_INT */

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#define WM831X_CHILD_INT_WIDTH 1 /* CHILD_INT */

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#define WM831X_CHG_INT 0x0004 /* CHG_INT */

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#define WM831X_CHG_INT_MASK 0x0004 /* CHG_INT */

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#define WM831X_CHG_INT_SHIFT 2 /* CHG_INT */

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#define WM831X_CHG_INT_WIDTH 1 /* CHG_INT */

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#define WM831X_HC_INT 0x0002 /* HC_INT */

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#define WM831X_HC_INT_MASK 0x0002 /* HC_INT */

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#define WM831X_HC_INT_SHIFT 1 /* HC_INT */

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#define WM831X_HC_INT_WIDTH 1 /* HC_INT */

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#define WM831X_UV_INT 0x0001 /* UV_INT */

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#define WM831X_UV_INT_MASK 0x0001 /* UV_INT */

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#define WM831X_UV_INT_SHIFT 0 /* UV_INT */

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#define WM831X_UV_INT_WIDTH 1 /* UV_INT */

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/*

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* R16401 (0x4011) - Interrupt Status 1

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*/

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#define WM831X_PPM_SYSLO_EINT 0x8000 /* PPM_SYSLO_EINT */

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#define WM831X_PPM_SYSLO_EINT_MASK 0x8000 /* PPM_SYSLO_EINT */

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#define WM831X_PPM_SYSLO_EINT_SHIFT 15 /* PPM_SYSLO_EINT */

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#define WM831X_PPM_SYSLO_EINT_WIDTH 1 /* PPM_SYSLO_EINT */

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#define WM831X_PPM_PWR_SRC_EINT 0x4000 /* PPM_PWR_SRC_EINT */

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#define WM831X_PPM_PWR_SRC_EINT_MASK 0x4000 /* PPM_PWR_SRC_EINT */

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#define WM831X_PPM_PWR_SRC_EINT_SHIFT 14 /* PPM_PWR_SRC_EINT */

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#define WM831X_PPM_PWR_SRC_EINT_WIDTH 1 /* PPM_PWR_SRC_EINT */

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#define WM831X_PPM_USB_CURR_EINT 0x2000 /* PPM_USB_CURR_EINT */

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#define WM831X_PPM_USB_CURR_EINT_MASK 0x2000 /* PPM_USB_CURR_EINT */

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#define WM831X_PPM_USB_CURR_EINT_SHIFT 13 /* PPM_USB_CURR_EINT */

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#define WM831X_PPM_USB_CURR_EINT_WIDTH 1 /* PPM_USB_CURR_EINT */

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#define WM831X_ON_PIN_EINT 0x1000 /* ON_PIN_EINT */

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#define WM831X_ON_PIN_EINT_MASK 0x1000 /* ON_PIN_EINT */

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#define WM831X_ON_PIN_EINT_SHIFT 12 /* ON_PIN_EINT */

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#define WM831X_ON_PIN_EINT_WIDTH 1 /* ON_PIN_EINT */

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#define WM831X_WDOG_TO_EINT 0x0800 /* WDOG_TO_EINT */

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#define WM831X_WDOG_TO_EINT_MASK 0x0800 /* WDOG_TO_EINT */

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#define WM831X_WDOG_TO_EINT_SHIFT 11 /* WDOG_TO_EINT */

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#define WM831X_WDOG_TO_EINT_WIDTH 1 /* WDOG_TO_EINT */

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#define WM831X_TCHDATA_EINT 0x0400 /* TCHDATA_EINT */

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#define WM831X_TCHDATA_EINT_MASK 0x0400 /* TCHDATA_EINT */

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#define WM831X_TCHDATA_EINT_SHIFT 10 /* TCHDATA_EINT */

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#define WM831X_TCHDATA_EINT_WIDTH 1 /* TCHDATA_EINT */

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#define WM831X_TCHPD_EINT 0x0200 /* TCHPD_EINT */

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#define WM831X_TCHPD_EINT_MASK 0x0200 /* TCHPD_EINT */

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#define WM831X_TCHPD_EINT_SHIFT 9 /* TCHPD_EINT */

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#define WM831X_TCHPD_EINT_WIDTH 1 /* TCHPD_EINT */

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#define WM831X_AUXADC_DATA_EINT 0x0100 /* AUXADC_DATA_EINT */

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#define WM831X_AUXADC_DATA_EINT_MASK 0x0100 /* AUXADC_DATA_EINT */

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#define WM831X_AUXADC_DATA_EINT_SHIFT 8 /* AUXADC_DATA_EINT */

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#define WM831X_AUXADC_DATA_EINT_WIDTH 1 /* AUXADC_DATA_EINT */

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#define WM831X_AUXADC_DCOMP4_EINT 0x0080 /* AUXADC_DCOMP4_EINT */

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#define WM831X_AUXADC_DCOMP4_EINT_MASK 0x0080 /* AUXADC_DCOMP4_EINT */

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#define WM831X_AUXADC_DCOMP4_EINT_SHIFT 7 /* AUXADC_DCOMP4_EINT */

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#define WM831X_AUXADC_DCOMP4_EINT_WIDTH 1 /* AUXADC_DCOMP4_EINT */

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#define WM831X_AUXADC_DCOMP3_EINT 0x0040 /* AUXADC_DCOMP3_EINT */

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#define WM831X_AUXADC_DCOMP3_EINT_MASK 0x0040 /* AUXADC_DCOMP3_EINT */

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#define WM831X_AUXADC_DCOMP3_EINT_SHIFT 6 /* AUXADC_DCOMP3_EINT */

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#define WM831X_AUXADC_DCOMP3_EINT_WIDTH 1 /* AUXADC_DCOMP3_EINT */

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#define WM831X_AUXADC_DCOMP2_EINT 0x0020 /* AUXADC_DCOMP2_EINT */

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#define WM831X_AUXADC_DCOMP2_EINT_MASK 0x0020 /* AUXADC_DCOMP2_EINT */

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#define WM831X_AUXADC_DCOMP2_EINT_SHIFT 5 /* AUXADC_DCOMP2_EINT */

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#define WM831X_AUXADC_DCOMP2_EINT_WIDTH 1 /* AUXADC_DCOMP2_EINT */

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#define WM831X_AUXADC_DCOMP1_EINT 0x0010 /* AUXADC_DCOMP1_EINT */

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#define WM831X_AUXADC_DCOMP1_EINT_MASK 0x0010 /* AUXADC_DCOMP1_EINT */

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#define WM831X_AUXADC_DCOMP1_EINT_SHIFT 4 /* AUXADC_DCOMP1_EINT */

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#define WM831X_AUXADC_DCOMP1_EINT_WIDTH 1 /* AUXADC_DCOMP1_EINT */

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#define WM831X_RTC_PER_EINT 0x0008 /* RTC_PER_EINT */

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#define WM831X_RTC_PER_EINT_MASK 0x0008 /* RTC_PER_EINT */

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#define WM831X_RTC_PER_EINT_SHIFT 3 /* RTC_PER_EINT */

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#define WM831X_RTC_PER_EINT_WIDTH 1 /* RTC_PER_EINT */

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#define WM831X_RTC_ALM_EINT 0x0004 /* RTC_ALM_EINT */

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#define WM831X_RTC_ALM_EINT_MASK 0x0004 /* RTC_ALM_EINT */

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#define WM831X_RTC_ALM_EINT_SHIFT 2 /* RTC_ALM_EINT */

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#define WM831X_RTC_ALM_EINT_WIDTH 1 /* RTC_ALM_EINT */

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#define WM831X_TEMP_THW_EINT 0x0002 /* TEMP_THW_EINT */

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#define WM831X_TEMP_THW_EINT_MASK 0x0002 /* TEMP_THW_EINT */

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#define WM831X_TEMP_THW_EINT_SHIFT 1 /* TEMP_THW_EINT */

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#define WM831X_TEMP_THW_EINT_WIDTH 1 /* TEMP_THW_EINT */

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/*

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* R16402 (0x4012) - Interrupt Status 2

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*/

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#define WM831X_CHG_BATT_HOT_EINT 0x8000 /* CHG_BATT_HOT_EINT */

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#define WM831X_CHG_BATT_HOT_EINT_MASK 0x8000 /* CHG_BATT_HOT_EINT */

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#define WM831X_CHG_BATT_HOT_EINT_SHIFT 15 /* CHG_BATT_HOT_EINT */

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#define WM831X_CHG_BATT_HOT_EINT_WIDTH 1 /* CHG_BATT_HOT_EINT */

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#define WM831X_CHG_BATT_COLD_EINT 0x4000 /* CHG_BATT_COLD_EINT */

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#define WM831X_CHG_BATT_COLD_EINT_MASK 0x4000 /* CHG_BATT_COLD_EINT */

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#define WM831X_CHG_BATT_COLD_EINT_SHIFT 14 /* CHG_BATT_COLD_EINT */

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#define WM831X_CHG_BATT_COLD_EINT_WIDTH 1 /* CHG_BATT_COLD_EINT */

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#define WM831X_CHG_BATT_FAIL_EINT 0x2000 /* CHG_BATT_FAIL_EINT */

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#define WM831X_CHG_BATT_FAIL_EINT_MASK 0x2000 /* CHG_BATT_FAIL_EINT */

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#define WM831X_CHG_BATT_FAIL_EINT_SHIFT 13 /* CHG_BATT_FAIL_EINT */

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#define WM831X_CHG_BATT_FAIL_EINT_WIDTH 1 /* CHG_BATT_FAIL_EINT */

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#define WM831X_CHG_OV_EINT 0x1000 /* CHG_OV_EINT */

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#define WM831X_CHG_OV_EINT_MASK 0x1000 /* CHG_OV_EINT */

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#define WM831X_CHG_OV_EINT_SHIFT 12 /* CHG_OV_EINT */

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#define WM831X_CHG_OV_EINT_WIDTH 1 /* CHG_OV_EINT */

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#define WM831X_CHG_END_EINT 0x0800 /* CHG_END_EINT */

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#define WM831X_CHG_END_EINT_MASK 0x0800 /* CHG_END_EINT */

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#define WM831X_CHG_END_EINT_SHIFT 11 /* CHG_END_EINT */

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#define WM831X_CHG_END_EINT_WIDTH 1 /* CHG_END_EINT */

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#define WM831X_CHG_TO_EINT 0x0400 /* CHG_TO_EINT */

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#define WM831X_CHG_TO_EINT_MASK 0x0400 /* CHG_TO_EINT */

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#define WM831X_CHG_TO_EINT_SHIFT 10 /* CHG_TO_EINT */

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#define WM831X_CHG_TO_EINT_WIDTH 1 /* CHG_TO_EINT */

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#define WM831X_CHG_MODE_EINT 0x0200 /* CHG_MODE_EINT */

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#define WM831X_CHG_MODE_EINT_MASK 0x0200 /* CHG_MODE_EINT */

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#define WM831X_CHG_MODE_EINT_SHIFT 9 /* CHG_MODE_EINT */

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#define WM831X_CHG_MODE_EINT_WIDTH 1 /* CHG_MODE_EINT */

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#define WM831X_CHG_START_EINT 0x0100 /* CHG_START_EINT */

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#define WM831X_CHG_START_EINT_MASK 0x0100 /* CHG_START_EINT */

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#define WM831X_CHG_START_EINT_SHIFT 8 /* CHG_START_EINT */

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#define WM831X_CHG_START_EINT_WIDTH 1 /* CHG_START_EINT */

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#define WM831X_CS2_EINT 0x0080 /* CS2_EINT */

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#define WM831X_CS2_EINT_MASK 0x0080 /* CS2_EINT */

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#define WM831X_CS2_EINT_SHIFT 7 /* CS2_EINT */

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#define WM831X_CS2_EINT_WIDTH 1 /* CS2_EINT */

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#define WM831X_CS1_EINT 0x0040 /* CS1_EINT */

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#define WM831X_CS1_EINT_MASK 0x0040 /* CS1_EINT */

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#define WM831X_CS1_EINT_SHIFT 6 /* CS1_EINT */

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#define WM831X_CS1_EINT_WIDTH 1 /* CS1_EINT */

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#define WM831X_OTP_CMD_END_EINT 0x0020 /* OTP_CMD_END_EINT */

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#define WM831X_OTP_CMD_END_EINT_MASK 0x0020 /* OTP_CMD_END_EINT */

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#define WM831X_OTP_CMD_END_EINT_SHIFT 5 /* OTP_CMD_END_EINT */

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#define WM831X_OTP_CMD_END_EINT_WIDTH 1 /* OTP_CMD_END_EINT */

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#define WM831X_OTP_ERR_EINT 0x0010 /* OTP_ERR_EINT */

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#define WM831X_OTP_ERR_EINT_MASK 0x0010 /* OTP_ERR_EINT */

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#define WM831X_OTP_ERR_EINT_SHIFT 4 /* OTP_ERR_EINT */

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#define WM831X_OTP_ERR_EINT_WIDTH 1 /* OTP_ERR_EINT */

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#define WM831X_PS_POR_EINT 0x0004 /* PS_POR_EINT */

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#define WM831X_PS_POR_EINT_MASK 0x0004 /* PS_POR_EINT */

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#define WM831X_PS_POR_EINT_SHIFT 2 /* PS_POR_EINT */

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#define WM831X_PS_POR_EINT_WIDTH 1 /* PS_POR_EINT */

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#define WM831X_PS_SLEEP_OFF_EINT 0x0002 /* PS_SLEEP_OFF_EINT */

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#define WM831X_PS_SLEEP_OFF_EINT_MASK 0x0002 /* PS_SLEEP_OFF_EINT */

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#define WM831X_PS_SLEEP_OFF_EINT_SHIFT 1 /* PS_SLEEP_OFF_EINT */

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#define WM831X_PS_SLEEP_OFF_EINT_WIDTH 1 /* PS_SLEEP_OFF_EINT */

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#define WM831X_PS_ON_WAKE_EINT 0x0001 /* PS_ON_WAKE_EINT */

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#define WM831X_PS_ON_WAKE_EINT_MASK 0x0001 /* PS_ON_WAKE_EINT */

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#define WM831X_PS_ON_WAKE_EINT_SHIFT 0 /* PS_ON_WAKE_EINT */

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#define WM831X_PS_ON_WAKE_EINT_WIDTH 1 /* PS_ON_WAKE_EINT */

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/*

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* R16403 (0x4013) - Interrupt Status 3

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*/

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#define WM831X_UV_LDO10_EINT 0x0200 /* UV_LDO10_EINT */

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#define WM831X_UV_LDO10_EINT_MASK 0x0200 /* UV_LDO10_EINT */

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#define WM831X_UV_LDO10_EINT_SHIFT 9 /* UV_LDO10_EINT */

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#define WM831X_UV_LDO10_EINT_WIDTH 1 /* UV_LDO10_EINT */

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#define WM831X_UV_LDO9_EINT 0x0100 /* UV_LDO9_EINT */

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#define WM831X_UV_LDO9_EINT_MASK 0x0100 /* UV_LDO9_EINT */

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#define WM831X_UV_LDO9_EINT_SHIFT 8 /* UV_LDO9_EINT */

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#define WM831X_UV_LDO9_EINT_WIDTH 1 /* UV_LDO9_EINT */

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#define WM831X_UV_LDO8_EINT 0x0080 /* UV_LDO8_EINT */

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#define WM831X_UV_LDO8_EINT_MASK 0x0080 /* UV_LDO8_EINT */

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#define WM831X_UV_LDO8_EINT_SHIFT 7 /* UV_LDO8_EINT */

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#define WM831X_UV_LDO8_EINT_WIDTH 1 /* UV_LDO8_EINT */

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#define WM831X_UV_LDO7_EINT 0x0040 /* UV_LDO7_EINT */

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#define WM831X_UV_LDO7_EINT_MASK 0x0040 /* UV_LDO7_EINT */

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#define WM831X_UV_LDO7_EINT_SHIFT 6 /* UV_LDO7_EINT */

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#define WM831X_UV_LDO7_EINT_WIDTH 1 /* UV_LDO7_EINT */

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#define WM831X_UV_LDO6_EINT 0x0020 /* UV_LDO6_EINT */

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#define WM831X_UV_LDO6_EINT_MASK 0x0020 /* UV_LDO6_EINT */

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#define WM831X_UV_LDO6_EINT_SHIFT 5 /* UV_LDO6_EINT */

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#define WM831X_UV_LDO6_EINT_WIDTH 1 /* UV_LDO6_EINT */

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#define WM831X_UV_LDO5_EINT 0x0010 /* UV_LDO5_EINT */

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#define WM831X_UV_LDO5_EINT_MASK 0x0010 /* UV_LDO5_EINT */

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#define WM831X_UV_LDO5_EINT_SHIFT 4 /* UV_LDO5_EINT */

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#define WM831X_UV_LDO5_EINT_WIDTH 1 /* UV_LDO5_EINT */

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#define WM831X_UV_LDO4_EINT 0x0008 /* UV_LDO4_EINT */

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#define WM831X_UV_LDO4_EINT_MASK 0x0008 /* UV_LDO4_EINT */

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#define WM831X_UV_LDO4_EINT_SHIFT 3 /* UV_LDO4_EINT */

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#define WM831X_UV_LDO4_EINT_WIDTH 1 /* UV_LDO4_EINT */

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#define WM831X_UV_LDO3_EINT 0x0004 /* UV_LDO3_EINT */

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#define WM831X_UV_LDO3_EINT_MASK 0x0004 /* UV_LDO3_EINT */

308

#define WM831X_UV_LDO3_EINT_SHIFT 2 /* UV_LDO3_EINT */

309

#define WM831X_UV_LDO3_EINT_WIDTH 1 /* UV_LDO3_EINT */

310

#define WM831X_UV_LDO2_EINT 0x0002 /* UV_LDO2_EINT */

311

#define WM831X_UV_LDO2_EINT_MASK 0x0002 /* UV_LDO2_EINT */

312

#define WM831X_UV_LDO2_EINT_SHIFT 1 /* UV_LDO2_EINT */

313

#define WM831X_UV_LDO2_EINT_WIDTH 1 /* UV_LDO2_EINT */

314

#define WM831X_UV_LDO1_EINT 0x0001 /* UV_LDO1_EINT */

315

#define WM831X_UV_LDO1_EINT_MASK 0x0001 /* UV_LDO1_EINT */

316

#define WM831X_UV_LDO1_EINT_SHIFT 0 /* UV_LDO1_EINT */

317

#define WM831X_UV_LDO1_EINT_WIDTH 1 /* UV_LDO1_EINT */

318

319

/*

320

* R16404 (0x4014) - Interrupt Status 4

321

*/

322

#define WM831X_HC_DC2_EINT 0x0200 /* HC_DC2_EINT */

323

#define WM831X_HC_DC2_EINT_MASK 0x0200 /* HC_DC2_EINT */

324

#define WM831X_HC_DC2_EINT_SHIFT 9 /* HC_DC2_EINT */

325

#define WM831X_HC_DC2_EINT_WIDTH 1 /* HC_DC2_EINT */

326

#define WM831X_HC_DC1_EINT 0x0100 /* HC_DC1_EINT */

327

#define WM831X_HC_DC1_EINT_MASK 0x0100 /* HC_DC1_EINT */

328

#define WM831X_HC_DC1_EINT_SHIFT 8 /* HC_DC1_EINT */

329

#define WM831X_HC_DC1_EINT_WIDTH 1 /* HC_DC1_EINT */

330

#define WM831X_UV_DC4_EINT 0x0008 /* UV_DC4_EINT */

331

#define WM831X_UV_DC4_EINT_MASK 0x0008 /* UV_DC4_EINT */

332

#define WM831X_UV_DC4_EINT_SHIFT 3 /* UV_DC4_EINT */

333

#define WM831X_UV_DC4_EINT_WIDTH 1 /* UV_DC4_EINT */

334

#define WM831X_UV_DC3_EINT 0x0004 /* UV_DC3_EINT */

335

#define WM831X_UV_DC3_EINT_MASK 0x0004 /* UV_DC3_EINT */

336

#define WM831X_UV_DC3_EINT_SHIFT 2 /* UV_DC3_EINT */

337

#define WM831X_UV_DC3_EINT_WIDTH 1 /* UV_DC3_EINT */

338

#define WM831X_UV_DC2_EINT 0x0002 /* UV_DC2_EINT */

339

#define WM831X_UV_DC2_EINT_MASK 0x0002 /* UV_DC2_EINT */

340

#define WM831X_UV_DC2_EINT_SHIFT 1 /* UV_DC2_EINT */

341

#define WM831X_UV_DC2_EINT_WIDTH 1 /* UV_DC2_EINT */

342

#define WM831X_UV_DC1_EINT 0x0001 /* UV_DC1_EINT */

343

#define WM831X_UV_DC1_EINT_MASK 0x0001 /* UV_DC1_EINT */

344

#define WM831X_UV_DC1_EINT_SHIFT 0 /* UV_DC1_EINT */

345

#define WM831X_UV_DC1_EINT_WIDTH 1 /* UV_DC1_EINT */

346

347

/*

348

* R16405 (0x4015) - Interrupt Status 5

349

*/

350

#define WM831X_GP16_EINT 0x8000 /* GP16_EINT */

351

#define WM831X_GP16_EINT_MASK 0x8000 /* GP16_EINT */

352

#define WM831X_GP16_EINT_SHIFT 15 /* GP16_EINT */

353

#define WM831X_GP16_EINT_WIDTH 1 /* GP16_EINT */

354

#define WM831X_GP15_EINT 0x4000 /* GP15_EINT */

355

#define WM831X_GP15_EINT_MASK 0x4000 /* GP15_EINT */

356

#define WM831X_GP15_EINT_SHIFT 14 /* GP15_EINT */

357

#define WM831X_GP15_EINT_WIDTH 1 /* GP15_EINT */

358

#define WM831X_GP14_EINT 0x2000 /* GP14_EINT */

359

#define WM831X_GP14_EINT_MASK 0x2000 /* GP14_EINT */

360

#define WM831X_GP14_EINT_SHIFT 13 /* GP14_EINT */

361

#define WM831X_GP14_EINT_WIDTH 1 /* GP14_EINT */

362

#define WM831X_GP13_EINT 0x1000 /* GP13_EINT */

363

#define WM831X_GP13_EINT_MASK 0x1000 /* GP13_EINT */

364

#define WM831X_GP13_EINT_SHIFT 12 /* GP13_EINT */

365

#define WM831X_GP13_EINT_WIDTH 1 /* GP13_EINT */

366

#define WM831X_GP12_EINT 0x0800 /* GP12_EINT */

367

#define WM831X_GP12_EINT_MASK 0x0800 /* GP12_EINT */

368

#define WM831X_GP12_EINT_SHIFT 11 /* GP12_EINT */

369

#define WM831X_GP12_EINT_WIDTH 1 /* GP12_EINT */

370

#define WM831X_GP11_EINT 0x0400 /* GP11_EINT */

371

#define WM831X_GP11_EINT_MASK 0x0400 /* GP11_EINT */

372

#define WM831X_GP11_EINT_SHIFT 10 /* GP11_EINT */

373

#define WM831X_GP11_EINT_WIDTH 1 /* GP11_EINT */

374

#define WM831X_GP10_EINT 0x0200 /* GP10_EINT */

375

#define WM831X_GP10_EINT_MASK 0x0200 /* GP10_EINT */

376

#define WM831X_GP10_EINT_SHIFT 9 /* GP10_EINT */

377

#define WM831X_GP10_EINT_WIDTH 1 /* GP10_EINT */

378

#define WM831X_GP9_EINT 0x0100 /* GP9_EINT */

379

#define WM831X_GP9_EINT_MASK 0x0100 /* GP9_EINT */

380

#define WM831X_GP9_EINT_SHIFT 8 /* GP9_EINT */

381

#define WM831X_GP9_EINT_WIDTH 1 /* GP9_EINT */

382

#define WM831X_GP8_EINT 0x0080 /* GP8_EINT */

383

#define WM831X_GP8_EINT_MASK 0x0080 /* GP8_EINT */

384

#define WM831X_GP8_EINT_SHIFT 7 /* GP8_EINT */

385

#define WM831X_GP8_EINT_WIDTH 1 /* GP8_EINT */

386

#define WM831X_GP7_EINT 0x0040 /* GP7_EINT */

387

#define WM831X_GP7_EINT_MASK 0x0040 /* GP7_EINT */

388

#define WM831X_GP7_EINT_SHIFT 6 /* GP7_EINT */

389

#define WM831X_GP7_EINT_WIDTH 1 /* GP7_EINT */

390

#define WM831X_GP6_EINT 0x0020 /* GP6_EINT */

391

#define WM831X_GP6_EINT_MASK 0x0020 /* GP6_EINT */

392

#define WM831X_GP6_EINT_SHIFT 5 /* GP6_EINT */

393

#define WM831X_GP6_EINT_WIDTH 1 /* GP6_EINT */

394

#define WM831X_GP5_EINT 0x0010 /* GP5_EINT */

395

#define WM831X_GP5_EINT_MASK 0x0010 /* GP5_EINT */

396

#define WM831X_GP5_EINT_SHIFT 4 /* GP5_EINT */

397

#define WM831X_GP5_EINT_WIDTH 1 /* GP5_EINT */

398

#define WM831X_GP4_EINT 0x0008 /* GP4_EINT */

399

#define WM831X_GP4_EINT_MASK 0x0008 /* GP4_EINT */

400

#define WM831X_GP4_EINT_SHIFT 3 /* GP4_EINT */

401

#define WM831X_GP4_EINT_WIDTH 1 /* GP4_EINT */

402

#define WM831X_GP3_EINT 0x0004 /* GP3_EINT */

403

#define WM831X_GP3_EINT_MASK 0x0004 /* GP3_EINT */

404

#define WM831X_GP3_EINT_SHIFT 2 /* GP3_EINT */

405

#define WM831X_GP3_EINT_WIDTH 1 /* GP3_EINT */

406

#define WM831X_GP2_EINT 0x0002 /* GP2_EINT */

407

#define WM831X_GP2_EINT_MASK 0x0002 /* GP2_EINT */

408

#define WM831X_GP2_EINT_SHIFT 1 /* GP2_EINT */

409

#define WM831X_GP2_EINT_WIDTH 1 /* GP2_EINT */

410

#define WM831X_GP1_EINT 0x0001 /* GP1_EINT */

411

#define WM831X_GP1_EINT_MASK 0x0001 /* GP1_EINT */

412

#define WM831X_GP1_EINT_SHIFT 0 /* GP1_EINT */

413

#define WM831X_GP1_EINT_WIDTH 1 /* GP1_EINT */

414

415

/*

416

* R16407 (0x4017) - IRQ Config

417

*/

418

#define WM831X_IRQ_OD 0x0002 /* IRQ_OD */

419

#define WM831X_IRQ_OD_MASK 0x0002 /* IRQ_OD */

420

#define WM831X_IRQ_OD_SHIFT 1 /* IRQ_OD */

421

#define WM831X_IRQ_OD_WIDTH 1 /* IRQ_OD */

422

#define WM831X_IM_IRQ 0x0001 /* IM_IRQ */

423

#define WM831X_IM_IRQ_MASK 0x0001 /* IM_IRQ */

424

#define WM831X_IM_IRQ_SHIFT 0 /* IM_IRQ */

425

#define WM831X_IM_IRQ_WIDTH 1 /* IM_IRQ */

426

427

/*

428

* R16408 (0x4018) - System Interrupts Mask

429

*/

430

#define WM831X_IM_PS_INT 0x8000 /* IM_PS_INT */

431

#define WM831X_IM_PS_INT_MASK 0x8000 /* IM_PS_INT */

432

#define WM831X_IM_PS_INT_SHIFT 15 /* IM_PS_INT */

433

#define WM831X_IM_PS_INT_WIDTH 1 /* IM_PS_INT */

434

#define WM831X_IM_TEMP_INT 0x4000 /* IM_TEMP_INT */

435

#define WM831X_IM_TEMP_INT_MASK 0x4000 /* IM_TEMP_INT */

436

#define WM831X_IM_TEMP_INT_SHIFT 14 /* IM_TEMP_INT */

437

#define WM831X_IM_TEMP_INT_WIDTH 1 /* IM_TEMP_INT */

438

#define WM831X_IM_GP_INT 0x2000 /* IM_GP_INT */

439

#define WM831X_IM_GP_INT_MASK 0x2000 /* IM_GP_INT */

440

#define WM831X_IM_GP_INT_SHIFT 13 /* IM_GP_INT */

441

#define WM831X_IM_GP_INT_WIDTH 1 /* IM_GP_INT */

442

#define WM831X_IM_ON_PIN_INT 0x1000 /* IM_ON_PIN_INT */

443

#define WM831X_IM_ON_PIN_INT_MASK 0x1000 /* IM_ON_PIN_INT */

444

#define WM831X_IM_ON_PIN_INT_SHIFT 12 /* IM_ON_PIN_INT */

445

#define WM831X_IM_ON_PIN_INT_WIDTH 1 /* IM_ON_PIN_INT */

446

#define WM831X_IM_WDOG_INT 0x0800 /* IM_WDOG_INT */

447

#define WM831X_IM_WDOG_INT_MASK 0x0800 /* IM_WDOG_INT */

448

#define WM831X_IM_WDOG_INT_SHIFT 11 /* IM_WDOG_INT */

449

#define WM831X_IM_WDOG_INT_WIDTH 1 /* IM_WDOG_INT */

450

#define WM831X_IM_TCHDATA_INT 0x0400 /* IM_TCHDATA_INT */

451

#define WM831X_IM_TCHDATA_INT_MASK 0x0400 /* IM_TCHDATA_INT */

452

#define WM831X_IM_TCHDATA_INT_SHIFT 10 /* IM_TCHDATA_INT */

453

#define WM831X_IM_TCHDATA_INT_WIDTH 1 /* IM_TCHDATA_INT */

454

#define WM831X_IM_TCHPD_INT 0x0200 /* IM_TCHPD_INT */

455

#define WM831X_IM_TCHPD_INT_MASK 0x0200 /* IM_TCHPD_INT */

456

#define WM831X_IM_TCHPD_INT_SHIFT 9 /* IM_TCHPD_INT */

457

#define WM831X_IM_TCHPD_INT_WIDTH 1 /* IM_TCHPD_INT */

458

#define WM831X_IM_AUXADC_INT 0x0100 /* IM_AUXADC_INT */

459

#define WM831X_IM_AUXADC_INT_MASK 0x0100 /* IM_AUXADC_INT */

460

#define WM831X_IM_AUXADC_INT_SHIFT 8 /* IM_AUXADC_INT */

461

#define WM831X_IM_AUXADC_INT_WIDTH 1 /* IM_AUXADC_INT */

462

#define WM831X_IM_PPM_INT 0x0080 /* IM_PPM_INT */

463

#define WM831X_IM_PPM_INT_MASK 0x0080 /* IM_PPM_INT */

464

#define WM831X_IM_PPM_INT_SHIFT 7 /* IM_PPM_INT */

465

#define WM831X_IM_PPM_INT_WIDTH 1 /* IM_PPM_INT */

466

#define WM831X_IM_CS_INT 0x0040 /* IM_CS_INT */

467

#define WM831X_IM_CS_INT_MASK 0x0040 /* IM_CS_INT */

468

#define WM831X_IM_CS_INT_SHIFT 6 /* IM_CS_INT */

469

#define WM831X_IM_CS_INT_WIDTH 1 /* IM_CS_INT */

470

#define WM831X_IM_RTC_INT 0x0020 /* IM_RTC_INT */

471

#define WM831X_IM_RTC_INT_MASK 0x0020 /* IM_RTC_INT */

472

#define WM831X_IM_RTC_INT_SHIFT 5 /* IM_RTC_INT */

473

#define WM831X_IM_RTC_INT_WIDTH 1 /* IM_RTC_INT */

474

#define WM831X_IM_OTP_INT 0x0010 /* IM_OTP_INT */

475

#define WM831X_IM_OTP_INT_MASK 0x0010 /* IM_OTP_INT */

476

#define WM831X_IM_OTP_INT_SHIFT 4 /* IM_OTP_INT */

477

#define WM831X_IM_OTP_INT_WIDTH 1 /* IM_OTP_INT */

478

#define WM831X_IM_CHILD_INT 0x0008 /* IM_CHILD_INT */

479

#define WM831X_IM_CHILD_INT_MASK 0x0008 /* IM_CHILD_INT */

480

#define WM831X_IM_CHILD_INT_SHIFT 3 /* IM_CHILD_INT */

481

#define WM831X_IM_CHILD_INT_WIDTH 1 /* IM_CHILD_INT */

482

#define WM831X_IM_CHG_INT 0x0004 /* IM_CHG_INT */

483

#define WM831X_IM_CHG_INT_MASK 0x0004 /* IM_CHG_INT */

484

#define WM831X_IM_CHG_INT_SHIFT 2 /* IM_CHG_INT */

485

#define WM831X_IM_CHG_INT_WIDTH 1 /* IM_CHG_INT */

486

#define WM831X_IM_HC_INT 0x0002 /* IM_HC_INT */

487

#define WM831X_IM_HC_INT_MASK 0x0002 /* IM_HC_INT */

488

#define WM831X_IM_HC_INT_SHIFT 1 /* IM_HC_INT */

489

#define WM831X_IM_HC_INT_WIDTH 1 /* IM_HC_INT */

490

#define WM831X_IM_UV_INT 0x0001 /* IM_UV_INT */

491

#define WM831X_IM_UV_INT_MASK 0x0001 /* IM_UV_INT */

492

#define WM831X_IM_UV_INT_SHIFT 0 /* IM_UV_INT */

493

#define WM831X_IM_UV_INT_WIDTH 1 /* IM_UV_INT */

494

495

/*

496

* R16409 (0x4019) - Interrupt Status 1 Mask

497

*/

498

#define WM831X_IM_PPM_SYSLO_EINT 0x8000 /* IM_PPM_SYSLO_EINT */

499

#define WM831X_IM_PPM_SYSLO_EINT_MASK 0x8000 /* IM_PPM_SYSLO_EINT */

500

#define WM831X_IM_PPM_SYSLO_EINT_SHIFT 15 /* IM_PPM_SYSLO_EINT */

501

#define WM831X_IM_PPM_SYSLO_EINT_WIDTH 1 /* IM_PPM_SYSLO_EINT */

502

#define WM831X_IM_PPM_PWR_SRC_EINT 0x4000 /* IM_PPM_PWR_SRC_EINT */

503

#define WM831X_IM_PPM_PWR_SRC_EINT_MASK 0x4000 /* IM_PPM_PWR_SRC_EINT */

504

#define WM831X_IM_PPM_PWR_SRC_EINT_SHIFT 14 /* IM_PPM_PWR_SRC_EINT */

505

#define WM831X_IM_PPM_PWR_SRC_EINT_WIDTH 1 /* IM_PPM_PWR_SRC_EINT */

506

#define WM831X_IM_PPM_USB_CURR_EINT 0x2000 /* IM_PPM_USB_CURR_EINT */

507

#define WM831X_IM_PPM_USB_CURR_EINT_MASK 0x2000 /* IM_PPM_USB_CURR_EINT */

508

#define WM831X_IM_PPM_USB_CURR_EINT_SHIFT 13 /* IM_PPM_USB_CURR_EINT */

509

#define WM831X_IM_PPM_USB_CURR_EINT_WIDTH 1 /* IM_PPM_USB_CURR_EINT */

510

#define WM831X_IM_ON_PIN_EINT 0x1000 /* IM_ON_PIN_EINT */

511

#define WM831X_IM_ON_PIN_EINT_MASK 0x1000 /* IM_ON_PIN_EINT */

512

#define WM831X_IM_ON_PIN_EINT_SHIFT 12 /* IM_ON_PIN_EINT */

513

#define WM831X_IM_ON_PIN_EINT_WIDTH 1 /* IM_ON_PIN_EINT */

514

#define WM831X_IM_WDOG_TO_EINT 0x0800 /* IM_WDOG_TO_EINT */

515

#define WM831X_IM_WDOG_TO_EINT_MASK 0x0800 /* IM_WDOG_TO_EINT */

516

#define WM831X_IM_WDOG_TO_EINT_SHIFT 11 /* IM_WDOG_TO_EINT */

517

#define WM831X_IM_WDOG_TO_EINT_WIDTH 1 /* IM_WDOG_TO_EINT */

518

#define WM831X_IM_TCHDATA_EINT 0x0400 /* IM_TCHDATA_EINT */

519

#define WM831X_IM_TCHDATA_EINT_MASK 0x0400 /* IM_TCHDATA_EINT */

520

#define WM831X_IM_TCHDATA_EINT_SHIFT 10 /* IM_TCHDATA_EINT */

521

#define WM831X_IM_TCHDATA_EINT_WIDTH 1 /* IM_TCHDATA_EINT */

522

#define WM831X_IM_TCHPD_EINT 0x0200 /* IM_TCHPD_EINT */

523

#define WM831X_IM_TCHPD_EINT_MASK 0x0200 /* IM_TCHPD_EINT */

524

#define WM831X_IM_TCHPD_EINT_SHIFT 9 /* IM_TCHPD_EINT */

525

#define WM831X_IM_TCHPD_EINT_WIDTH 1 /* IM_TCHPD_EINT */

526

#define WM831X_IM_AUXADC_DATA_EINT 0x0100 /* IM_AUXADC_DATA_EINT */

527

#define WM831X_IM_AUXADC_DATA_EINT_MASK 0x0100 /* IM_AUXADC_DATA_EINT */

528

#define WM831X_IM_AUXADC_DATA_EINT_SHIFT 8 /* IM_AUXADC_DATA_EINT */

529

#define WM831X_IM_AUXADC_DATA_EINT_WIDTH 1 /* IM_AUXADC_DATA_EINT */

530

#define WM831X_IM_AUXADC_DCOMP4_EINT 0x0080 /* IM_AUXADC_DCOMP4_EINT */

531

#define WM831X_IM_AUXADC_DCOMP4_EINT_MASK 0x0080 /* IM_AUXADC_DCOMP4_EINT */

532

#define WM831X_IM_AUXADC_DCOMP4_EINT_SHIFT 7 /* IM_AUXADC_DCOMP4_EINT */

533

#define WM831X_IM_AUXADC_DCOMP4_EINT_WIDTH 1 /* IM_AUXADC_DCOMP4_EINT */

534

#define WM831X_IM_AUXADC_DCOMP3_EINT 0x0040 /* IM_AUXADC_DCOMP3_EINT */

535

#define WM831X_IM_AUXADC_DCOMP3_EINT_MASK 0x0040 /* IM_AUXADC_DCOMP3_EINT */

536

#define WM831X_IM_AUXADC_DCOMP3_EINT_SHIFT 6 /* IM_AUXADC_DCOMP3_EINT */

537

#define WM831X_IM_AUXADC_DCOMP3_EINT_WIDTH 1 /* IM_AUXADC_DCOMP3_EINT */

538

#define WM831X_IM_AUXADC_DCOMP2_EINT 0x0020 /* IM_AUXADC_DCOMP2_EINT */

539

#define WM831X_IM_AUXADC_DCOMP2_EINT_MASK 0x0020 /* IM_AUXADC_DCOMP2_EINT */

540

#define WM831X_IM_AUXADC_DCOMP2_EINT_SHIFT 5 /* IM_AUXADC_DCOMP2_EINT */

541

#define WM831X_IM_AUXADC_DCOMP2_EINT_WIDTH 1 /* IM_AUXADC_DCOMP2_EINT */

542

#define WM831X_IM_AUXADC_DCOMP1_EINT 0x0010 /* IM_AUXADC_DCOMP1_EINT */

543

#define WM831X_IM_AUXADC_DCOMP1_EINT_MASK 0x0010 /* IM_AUXADC_DCOMP1_EINT */

544

#define WM831X_IM_AUXADC_DCOMP1_EINT_SHIFT 4 /* IM_AUXADC_DCOMP1_EINT */

545

#define WM831X_IM_AUXADC_DCOMP1_EINT_WIDTH 1 /* IM_AUXADC_DCOMP1_EINT */

546

#define WM831X_IM_RTC_PER_EINT 0x0008 /* IM_RTC_PER_EINT */

547

#define WM831X_IM_RTC_PER_EINT_MASK 0x0008 /* IM_RTC_PER_EINT */

548

#define WM831X_IM_RTC_PER_EINT_SHIFT 3 /* IM_RTC_PER_EINT */

549

#define WM831X_IM_RTC_PER_EINT_WIDTH 1 /* IM_RTC_PER_EINT */

550

#define WM831X_IM_RTC_ALM_EINT 0x0004 /* IM_RTC_ALM_EINT */

551

#define WM831X_IM_RTC_ALM_EINT_MASK 0x0004 /* IM_RTC_ALM_EINT */

552

#define WM831X_IM_RTC_ALM_EINT_SHIFT 2 /* IM_RTC_ALM_EINT */

553

#define WM831X_IM_RTC_ALM_EINT_WIDTH 1 /* IM_RTC_ALM_EINT */

554

#define WM831X_IM_TEMP_THW_EINT 0x0002 /* IM_TEMP_THW_EINT */

555

#define WM831X_IM_TEMP_THW_EINT_MASK 0x0002 /* IM_TEMP_THW_EINT */

556

#define WM831X_IM_TEMP_THW_EINT_SHIFT 1 /* IM_TEMP_THW_EINT */

557

#define WM831X_IM_TEMP_THW_EINT_WIDTH 1 /* IM_TEMP_THW_EINT */

558

559

/*

560

* R16410 (0x401A) - Interrupt Status 2 Mask

561

*/

562

#define WM831X_IM_CHG_BATT_HOT_EINT 0x8000 /* IM_CHG_BATT_HOT_EINT */

563

#define WM831X_IM_CHG_BATT_HOT_EINT_MASK 0x8000 /* IM_CHG_BATT_HOT_EINT */

564

#define WM831X_IM_CHG_BATT_HOT_EINT_SHIFT 15 /* IM_CHG_BATT_HOT_EINT */

565

#define WM831X_IM_CHG_BATT_HOT_EINT_WIDTH 1 /* IM_CHG_BATT_HOT_EINT */

566

#define WM831X_IM_CHG_BATT_COLD_EINT 0x4000 /* IM_CHG_BATT_COLD_EINT */

567

#define WM831X_IM_CHG_BATT_COLD_EINT_MASK 0x4000 /* IM_CHG_BATT_COLD_EINT */

568

#define WM831X_IM_CHG_BATT_COLD_EINT_SHIFT 14 /* IM_CHG_BATT_COLD_EINT */

569

#define WM831X_IM_CHG_BATT_COLD_EINT_WIDTH 1 /* IM_CHG_BATT_COLD_EINT */

570

#define WM831X_IM_CHG_BATT_FAIL_EINT 0x2000 /* IM_CHG_BATT_FAIL_EINT */

571

#define WM831X_IM_CHG_BATT_FAIL_EINT_MASK 0x2000 /* IM_CHG_BATT_FAIL_EINT */

572

#define WM831X_IM_CHG_BATT_FAIL_EINT_SHIFT 13 /* IM_CHG_BATT_FAIL_EINT */

573

#define WM831X_IM_CHG_BATT_FAIL_EINT_WIDTH 1 /* IM_CHG_BATT_FAIL_EINT */

574

#define WM831X_IM_CHG_OV_EINT 0x1000 /* IM_CHG_OV_EINT */

575

#define WM831X_IM_CHG_OV_EINT_MASK 0x1000 /* IM_CHG_OV_EINT */

576

#define WM831X_IM_CHG_OV_EINT_SHIFT 12 /* IM_CHG_OV_EINT */

577

#define WM831X_IM_CHG_OV_EINT_WIDTH 1 /* IM_CHG_OV_EINT */

578

#define WM831X_IM_CHG_END_EINT 0x0800 /* IM_CHG_END_EINT */

579

#define WM831X_IM_CHG_END_EINT_MASK 0x0800 /* IM_CHG_END_EINT */

580

#define WM831X_IM_CHG_END_EINT_SHIFT 11 /* IM_CHG_END_EINT */

581

#define WM831X_IM_CHG_END_EINT_WIDTH 1 /* IM_CHG_END_EINT */

582

#define WM831X_IM_CHG_TO_EINT 0x0400 /* IM_CHG_TO_EINT */

583

#define WM831X_IM_CHG_TO_EINT_MASK 0x0400 /* IM_CHG_TO_EINT */

584

#define WM831X_IM_CHG_TO_EINT_SHIFT 10 /* IM_CHG_TO_EINT */

585

#define WM831X_IM_CHG_TO_EINT_WIDTH 1 /* IM_CHG_TO_EINT */

586

#define WM831X_IM_CHG_MODE_EINT 0x0200 /* IM_CHG_MODE_EINT */

587

#define WM831X_IM_CHG_MODE_EINT_MASK 0x0200 /* IM_CHG_MODE_EINT */

588

#define WM831X_IM_CHG_MODE_EINT_SHIFT 9 /* IM_CHG_MODE_EINT */

589

#define WM831X_IM_CHG_MODE_EINT_WIDTH 1 /* IM_CHG_MODE_EINT */

590

#define WM831X_IM_CHG_START_EINT 0x0100 /* IM_CHG_START_EINT */

591

#define WM831X_IM_CHG_START_EINT_MASK 0x0100 /* IM_CHG_START_EINT */

592

#define WM831X_IM_CHG_START_EINT_SHIFT 8 /* IM_CHG_START_EINT */

593

#define WM831X_IM_CHG_START_EINT_WIDTH 1 /* IM_CHG_START_EINT */

594

#define WM831X_IM_CS2_EINT 0x0080 /* IM_CS2_EINT */

595

#define WM831X_IM_CS2_EINT_MASK 0x0080 /* IM_CS2_EINT */

596

#define WM831X_IM_CS2_EINT_SHIFT 7 /* IM_CS2_EINT */

597

#define WM831X_IM_CS2_EINT_WIDTH 1 /* IM_CS2_EINT */

598

#define WM831X_IM_CS1_EINT 0x0040 /* IM_CS1_EINT */

599

#define WM831X_IM_CS1_EINT_MASK 0x0040 /* IM_CS1_EINT */

600

#define WM831X_IM_CS1_EINT_SHIFT 6 /* IM_CS1_EINT */

601

#define WM831X_IM_CS1_EINT_WIDTH 1 /* IM_CS1_EINT */

602

#define WM831X_IM_OTP_CMD_END_EINT 0x0020 /* IM_OTP_CMD_END_EINT */

603

#define WM831X_IM_OTP_CMD_END_EINT_MASK 0x0020 /* IM_OTP_CMD_END_EINT */

604

#define WM831X_IM_OTP_CMD_END_EINT_SHIFT 5 /* IM_OTP_CMD_END_EINT */

605

#define WM831X_IM_OTP_CMD_END_EINT_WIDTH 1 /* IM_OTP_CMD_END_EINT */

606

#define WM831X_IM_OTP_ERR_EINT 0x0010 /* IM_OTP_ERR_EINT */

607

#define WM831X_IM_OTP_ERR_EINT_MASK 0x0010 /* IM_OTP_ERR_EINT */

608

#define WM831X_IM_OTP_ERR_EINT_SHIFT 4 /* IM_OTP_ERR_EINT */

609

#define WM831X_IM_OTP_ERR_EINT_WIDTH 1 /* IM_OTP_ERR_EINT */

610

#define WM831X_IM_PS_POR_EINT 0x0004 /* IM_PS_POR_EINT */

611

#define WM831X_IM_PS_POR_EINT_MASK 0x0004 /* IM_PS_POR_EINT */

612

#define WM831X_IM_PS_POR_EINT_SHIFT 2 /* IM_PS_POR_EINT */

613

#define WM831X_IM_PS_POR_EINT_WIDTH 1 /* IM_PS_POR_EINT */

614

#define WM831X_IM_PS_SLEEP_OFF_EINT 0x0002 /* IM_PS_SLEEP_OFF_EINT */

615

#define WM831X_IM_PS_SLEEP_OFF_EINT_MASK 0x0002 /* IM_PS_SLEEP_OFF_EINT */

616

#define WM831X_IM_PS_SLEEP_OFF_EINT_SHIFT 1 /* IM_PS_SLEEP_OFF_EINT */

617

#define WM831X_IM_PS_SLEEP_OFF_EINT_WIDTH 1 /* IM_PS_SLEEP_OFF_EINT */

618

#define WM831X_IM_PS_ON_WAKE_EINT 0x0001 /* IM_PS_ON_WAKE_EINT */

619

#define WM831X_IM_PS_ON_WAKE_EINT_MASK 0x0001 /* IM_PS_ON_WAKE_EINT */

620

#define WM831X_IM_PS_ON_WAKE_EINT_SHIFT 0 /* IM_PS_ON_WAKE_EINT */

621

#define WM831X_IM_PS_ON_WAKE_EINT_WIDTH 1 /* IM_PS_ON_WAKE_EINT */

622

623

/*

624

* R16411 (0x401B) - Interrupt Status 3 Mask

625

*/

626

#define WM831X_IM_UV_LDO10_EINT 0x0200 /* IM_UV_LDO10_EINT */

627

#define WM831X_IM_UV_LDO10_EINT_MASK 0x0200 /* IM_UV_LDO10_EINT */

628

#define WM831X_IM_UV_LDO10_EINT_SHIFT 9 /* IM_UV_LDO10_EINT */

629

#define WM831X_IM_UV_LDO10_EINT_WIDTH 1 /* IM_UV_LDO10_EINT */

630

#define WM831X_IM_UV_LDO9_EINT 0x0100 /* IM_UV_LDO9_EINT */

631

#define WM831X_IM_UV_LDO9_EINT_MASK 0x0100 /* IM_UV_LDO9_EINT */

632

#define WM831X_IM_UV_LDO9_EINT_SHIFT 8 /* IM_UV_LDO9_EINT */

633

#define WM831X_IM_UV_LDO9_EINT_WIDTH 1 /* IM_UV_LDO9_EINT */

634

#define WM831X_IM_UV_LDO8_EINT 0x0080 /* IM_UV_LDO8_EINT */

635

#define WM831X_IM_UV_LDO8_EINT_MASK 0x0080 /* IM_UV_LDO8_EINT */

636

#define WM831X_IM_UV_LDO8_EINT_SHIFT 7 /* IM_UV_LDO8_EINT */

637

#define WM831X_IM_UV_LDO8_EINT_WIDTH 1 /* IM_UV_LDO8_EINT */

638

#define WM831X_IM_UV_LDO7_EINT 0x0040 /* IM_UV_LDO7_EINT */

639

#define WM831X_IM_UV_LDO7_EINT_MASK 0x0040 /* IM_UV_LDO7_EINT */

640

#define WM831X_IM_UV_LDO7_EINT_SHIFT 6 /* IM_UV_LDO7_EINT */

641

#define WM831X_IM_UV_LDO7_EINT_WIDTH 1 /* IM_UV_LDO7_EINT */

642

#define WM831X_IM_UV_LDO6_EINT 0x0020 /* IM_UV_LDO6_EINT */

643

#define WM831X_IM_UV_LDO6_EINT_MASK 0x0020 /* IM_UV_LDO6_EINT */

644

#define WM831X_IM_UV_LDO6_EINT_SHIFT 5 /* IM_UV_LDO6_EINT */

645

#define WM831X_IM_UV_LDO6_EINT_WIDTH 1 /* IM_UV_LDO6_EINT */

646

#define WM831X_IM_UV_LDO5_EINT 0x0010 /* IM_UV_LDO5_EINT */

647

#define WM831X_IM_UV_LDO5_EINT_MASK 0x0010 /* IM_UV_LDO5_EINT */

648

#define WM831X_IM_UV_LDO5_EINT_SHIFT 4 /* IM_UV_LDO5_EINT */

649

#define WM831X_IM_UV_LDO5_EINT_WIDTH 1 /* IM_UV_LDO5_EINT */

650

#define WM831X_IM_UV_LDO4_EINT 0x0008 /* IM_UV_LDO4_EINT */

651

#define WM831X_IM_UV_LDO4_EINT_MASK 0x0008 /* IM_UV_LDO4_EINT */

652

#define WM831X_IM_UV_LDO4_EINT_SHIFT 3 /* IM_UV_LDO4_EINT */

653

#define WM831X_IM_UV_LDO4_EINT_WIDTH 1 /* IM_UV_LDO4_EINT */

654

#define WM831X_IM_UV_LDO3_EINT 0x0004 /* IM_UV_LDO3_EINT */

655

#define WM831X_IM_UV_LDO3_EINT_MASK 0x0004 /* IM_UV_LDO3_EINT */

656

#define WM831X_IM_UV_LDO3_EINT_SHIFT 2 /* IM_UV_LDO3_EINT */

657

#define WM831X_IM_UV_LDO3_EINT_WIDTH 1 /* IM_UV_LDO3_EINT */

658

#define WM831X_IM_UV_LDO2_EINT 0x0002 /* IM_UV_LDO2_EINT */

659

#define WM831X_IM_UV_LDO2_EINT_MASK 0x0002 /* IM_UV_LDO2_EINT */

660

#define WM831X_IM_UV_LDO2_EINT_SHIFT 1 /* IM_UV_LDO2_EINT */

661

#define WM831X_IM_UV_LDO2_EINT_WIDTH 1 /* IM_UV_LDO2_EINT */

662

#define WM831X_IM_UV_LDO1_EINT 0x0001 /* IM_UV_LDO1_EINT */

663

#define WM831X_IM_UV_LDO1_EINT_MASK 0x0001 /* IM_UV_LDO1_EINT */

664

#define WM831X_IM_UV_LDO1_EINT_SHIFT 0 /* IM_UV_LDO1_EINT */

665

#define WM831X_IM_UV_LDO1_EINT_WIDTH 1 /* IM_UV_LDO1_EINT */

666

667

/*

668

* R16412 (0x401C) - Interrupt Status 4 Mask

669

*/

670

#define WM831X_IM_HC_DC2_EINT 0x0200 /* IM_HC_DC2_EINT */

671

#define WM831X_IM_HC_DC2_EINT_MASK 0x0200 /* IM_HC_DC2_EINT */

672

#define WM831X_IM_HC_DC2_EINT_SHIFT 9 /* IM_HC_DC2_EINT */

673

#define WM831X_IM_HC_DC2_EINT_WIDTH 1 /* IM_HC_DC2_EINT */

674

#define WM831X_IM_HC_DC1_EINT 0x0100 /* IM_HC_DC1_EINT */

675

#define WM831X_IM_HC_DC1_EINT_MASK 0x0100 /* IM_HC_DC1_EINT */

676

#define WM831X_IM_HC_DC1_EINT_SHIFT 8 /* IM_HC_DC1_EINT */

677

#define WM831X_IM_HC_DC1_EINT_WIDTH 1 /* IM_HC_DC1_EINT */

678

#define WM831X_IM_UV_DC4_EINT 0x0008 /* IM_UV_DC4_EINT */

679

#define WM831X_IM_UV_DC4_EINT_MASK 0x0008 /* IM_UV_DC4_EINT */

680

#define WM831X_IM_UV_DC4_EINT_SHIFT 3 /* IM_UV_DC4_EINT */

681

#define WM831X_IM_UV_DC4_EINT_WIDTH 1 /* IM_UV_DC4_EINT */

682

#define WM831X_IM_UV_DC3_EINT 0x0004 /* IM_UV_DC3_EINT */

683

#define WM831X_IM_UV_DC3_EINT_MASK 0x0004 /* IM_UV_DC3_EINT */

684

#define WM831X_IM_UV_DC3_EINT_SHIFT 2 /* IM_UV_DC3_EINT */

685

#define WM831X_IM_UV_DC3_EINT_WIDTH 1 /* IM_UV_DC3_EINT */

686

#define WM831X_IM_UV_DC2_EINT 0x0002 /* IM_UV_DC2_EINT */

687

#define WM831X_IM_UV_DC2_EINT_MASK 0x0002 /* IM_UV_DC2_EINT */

688

#define WM831X_IM_UV_DC2_EINT_SHIFT 1 /* IM_UV_DC2_EINT */

689

#define WM831X_IM_UV_DC2_EINT_WIDTH 1 /* IM_UV_DC2_EINT */

690

#define WM831X_IM_UV_DC1_EINT 0x0001 /* IM_UV_DC1_EINT */

691

#define WM831X_IM_UV_DC1_EINT_MASK 0x0001 /* IM_UV_DC1_EINT */

692

#define WM831X_IM_UV_DC1_EINT_SHIFT 0 /* IM_UV_DC1_EINT */

693

#define WM831X_IM_UV_DC1_EINT_WIDTH 1 /* IM_UV_DC1_EINT */

694

695

/*

696

* R16413 (0x401D) - Interrupt Status 5 Mask

697

*/

698

#define WM831X_IM_GP16_EINT 0x8000 /* IM_GP16_EINT */

699

#define WM831X_IM_GP16_EINT_MASK 0x8000 /* IM_GP16_EINT */

700

#define WM831X_IM_GP16_EINT_SHIFT 15 /* IM_GP16_EINT */

701

#define WM831X_IM_GP16_EINT_WIDTH 1 /* IM_GP16_EINT */

702

#define WM831X_IM_GP15_EINT 0x4000 /* IM_GP15_EINT */

703

#define WM831X_IM_GP15_EINT_MASK 0x4000 /* IM_GP15_EINT */

704

#define WM831X_IM_GP15_EINT_SHIFT 14 /* IM_GP15_EINT */

705

#define WM831X_IM_GP15_EINT_WIDTH 1 /* IM_GP15_EINT */

706

#define WM831X_IM_GP14_EINT 0x2000 /* IM_GP14_EINT */

707

#define WM831X_IM_GP14_EINT_MASK 0x2000 /* IM_GP14_EINT */

708

#define WM831X_IM_GP14_EINT_SHIFT 13 /* IM_GP14_EINT */

709

#define WM831X_IM_GP14_EINT_WIDTH 1 /* IM_GP14_EINT */

710

#define WM831X_IM_GP13_EINT 0x1000 /* IM_GP13_EINT */

711

#define WM831X_IM_GP13_EINT_MASK 0x1000 /* IM_GP13_EINT */

712

#define WM831X_IM_GP13_EINT_SHIFT 12 /* IM_GP13_EINT */

713

#define WM831X_IM_GP13_EINT_WIDTH 1 /* IM_GP13_EINT */

714

#define WM831X_IM_GP12_EINT 0x0800 /* IM_GP12_EINT */

715

#define WM831X_IM_GP12_EINT_MASK 0x0800 /* IM_GP12_EINT */

716

#define WM831X_IM_GP12_EINT_SHIFT 11 /* IM_GP12_EINT */

717

#define WM831X_IM_GP12_EINT_WIDTH 1 /* IM_GP12_EINT */

718

#define WM831X_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */

719

#define WM831X_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */

720

#define WM831X_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */

721

#define WM831X_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */

722

#define WM831X_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */

723

#define WM831X_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */

724

#define WM831X_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */

725

#define WM831X_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */

726

#define WM831X_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */

727

#define WM831X_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */

728

#define WM831X_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */

729

#define WM831X_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */

730

#define WM831X_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */

731

#define WM831X_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */

732

#define WM831X_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */

733

#define WM831X_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */

734

#define WM831X_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */

735

#define WM831X_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */

736

#define WM831X_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */

737

#define WM831X_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */

738

#define WM831X_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */

739

#define WM831X_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */

740

#define WM831X_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */

741

#define WM831X_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */

742

#define WM831X_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */

743

#define WM831X_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */

744

#define WM831X_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */

745

#define WM831X_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */

746

#define WM831X_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */

747

#define WM831X_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */

748

#define WM831X_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */

749

#define WM831X_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */

750

#define WM831X_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */

751

#define WM831X_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */

752

#define WM831X_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */

753

#define WM831X_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */

754

#define WM831X_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */

755

#define WM831X_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */

756

#define WM831X_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */

757

#define WM831X_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */

758

#define WM831X_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */

759

#define WM831X_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */

760

#define WM831X_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */

761

#define WM831X_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */

762

763

764

#endif