| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* | 
 | 2 |  * Permedia2 framebuffer driver definitions. | 
 | 3 |  * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT) | 
 | 4 |  * -------------------------------------------------------------------------- | 
 | 5 |  * $Id: pm2fb.h,v 1.26 2000/09/19 00:11:53 illo Exp $ | 
 | 6 |  * -------------------------------------------------------------------------- | 
 | 7 |  * This file is subject to the terms and conditions of the GNU General Public | 
 | 8 |  * License.  See the file COPYING in the main directory of this archive | 
 | 9 |  * for more details. | 
 | 10 |  */ | 
 | 11 |  | 
 | 12 | #ifndef PM2FB_H | 
 | 13 | #define PM2FB_H | 
 | 14 |  | 
 | 15 | #define PM2_REFERENCE_CLOCK	14318			/* in KHz */ | 
 | 16 | #define PM2_MAX_PIXCLOCK	230000			/* in KHz */ | 
 | 17 | #define PM2_REGS_SIZE		0x10000 | 
 | 18 |  | 
 | 19 | #define PM2TAG(r) (u32 )(((r)-0x8000)>>3) | 
 | 20 |  | 
 | 21 | /***************************************************************************** | 
 | 22 |  * Permedia2 registers used in the framebuffer | 
 | 23 |  *****************************************************************************/ | 
 | 24 |   | 
 | 25 | #define PM2R_RESET_STATUS				0x0000 | 
 | 26 | #define PM2R_IN_FIFO_SPACE				0x0018 | 
 | 27 | #define PM2R_OUT_FIFO_WORDS				0x0020 | 
 | 28 | #define PM2R_APERTURE_ONE				0x0050 | 
 | 29 | #define PM2R_APERTURE_TWO				0x0058 | 
 | 30 | #define PM2R_FIFO_DISCON				0x0068 | 
 | 31 | #define PM2R_CHIP_CONFIG				0x0070 | 
 | 32 |  | 
 | 33 | #define PM2R_REBOOT					0x1000 | 
 | 34 | #define PM2R_MEM_CONTROL				0x1040 | 
 | 35 | #define PM2R_BOOT_ADDRESS				0x1080 | 
 | 36 | #define PM2R_MEM_CONFIG					0x10c0 | 
 | 37 | #define PM2R_BYPASS_WRITE_MASK				0x1100 | 
 | 38 | #define PM2R_FRAMEBUFFER_WRITE_MASK			0x1140 | 
 | 39 |  | 
 | 40 | #define PM2R_OUT_FIFO					0x2000 | 
 | 41 |  | 
 | 42 | #define PM2R_SCREEN_BASE				0x3000 | 
 | 43 | #define PM2R_SCREEN_STRIDE				0x3008 | 
 | 44 | #define PM2R_H_TOTAL					0x3010 | 
 | 45 | #define PM2R_HG_END					0x3018 | 
 | 46 | #define PM2R_HB_END					0x3020 | 
 | 47 | #define PM2R_HS_START					0x3028 | 
 | 48 | #define PM2R_HS_END					0x3030 | 
 | 49 | #define PM2R_V_TOTAL					0x3038 | 
 | 50 | #define PM2R_VB_END					0x3040 | 
 | 51 | #define PM2R_VS_START					0x3048 | 
 | 52 | #define PM2R_VS_END					0x3050 | 
 | 53 | #define PM2R_VIDEO_CONTROL				0x3058 | 
 | 54 | #define PM2R_LINE_COUNT					0x3070 | 
 | 55 | #define PM2R_FIFO_CONTROL				0x3078 | 
 | 56 |  | 
 | 57 | #define PM2R_RD_PALETTE_WRITE_ADDRESS			0x4000 | 
 | 58 | #define PM2R_RD_PALETTE_DATA				0x4008 | 
 | 59 | #define PM2R_RD_PIXEL_MASK				0x4010 | 
 | 60 | #define PM2R_RD_PALETTE_READ_ADDRESS			0x4018 | 
| Krzysztof Helt | 2a36f9c | 2007-10-16 01:29:16 -0700 | [diff] [blame] | 61 | #define PM2R_RD_CURSOR_COLOR_ADDRESS		        0x4020 | 
 | 62 | #define PM2R_RD_CURSOR_COLOR_DATA		        0x4028 | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 63 | #define PM2R_RD_INDEXED_DATA				0x4050 | 
| Krzysztof Helt | 2a36f9c | 2007-10-16 01:29:16 -0700 | [diff] [blame] | 64 | #define PM2R_RD_CURSOR_DATA				0x4058 | 
 | 65 | #define PM2R_RD_CURSOR_X_LSB				0x4060 | 
 | 66 | #define PM2R_RD_CURSOR_X_MSB				0x4068 | 
 | 67 | #define PM2R_RD_CURSOR_Y_LSB				0x4070 | 
 | 68 | #define PM2R_RD_CURSOR_Y_MSB				0x4078 | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 69 |  | 
 | 70 | #define PM2R_START_X_DOM				0x8000 | 
 | 71 | #define PM2R_D_X_DOM					0x8008 | 
 | 72 | #define PM2R_START_X_SUB				0x8010 | 
 | 73 | #define PM2R_D_X_SUB					0x8018 | 
 | 74 | #define PM2R_START_Y					0x8020 | 
 | 75 | #define PM2R_D_Y					0x8028 | 
 | 76 | #define PM2R_COUNT					0x8030 | 
 | 77 | #define PM2R_RENDER					0x8038 | 
| Krzysztof Helt | 91b3a6f | 2007-10-16 01:28:34 -0700 | [diff] [blame] | 78 | #define PM2R_BIT_MASK_PATTERN				0x8068 | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 79 | #define PM2R_RASTERIZER_MODE				0x80a0 | 
 | 80 | #define PM2R_RECTANGLE_ORIGIN				0x80d0 | 
 | 81 | #define PM2R_RECTANGLE_SIZE				0x80d8 | 
 | 82 | #define PM2R_PACKED_DATA_LIMITS				0x8150 | 
 | 83 | #define PM2R_SCISSOR_MODE				0x8180 | 
| Krzysztof Helt | 91b3a6f | 2007-10-16 01:28:34 -0700 | [diff] [blame] | 84 | #define PM2R_SCISSOR_MIN_XY				0x8188 | 
 | 85 | #define PM2R_SCISSOR_MAX_XY				0x8190 | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | #define PM2R_SCREEN_SIZE				0x8198 | 
 | 87 | #define PM2R_AREA_STIPPLE_MODE				0x81a0 | 
 | 88 | #define PM2R_WINDOW_ORIGIN				0x81c8 | 
 | 89 | #define PM2R_TEXTURE_ADDRESS_MODE			0x8380 | 
 | 90 | #define PM2R_TEXTURE_MAP_FORMAT				0x8588 | 
 | 91 | #define PM2R_TEXTURE_DATA_FORMAT			0x8590 | 
 | 92 | #define PM2R_TEXTURE_READ_MODE				0x8670 | 
 | 93 | #define PM2R_TEXEL_LUT_MODE				0x8678 | 
 | 94 | #define PM2R_TEXTURE_COLOR_MODE				0x8680 | 
 | 95 | #define PM2R_FOG_MODE					0x8690 | 
| Krzysztof Helt | 91b3a6f | 2007-10-16 01:28:34 -0700 | [diff] [blame] | 96 | #define PM2R_TEXEL0					0x8760 | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 97 | #define PM2R_COLOR_DDA_MODE				0x87e0 | 
| Krzysztof Helt | 91b3a6f | 2007-10-16 01:28:34 -0700 | [diff] [blame] | 98 | #define PM2R_CONSTANT_COLOR				0x87e8 | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 99 | #define PM2R_ALPHA_BLEND_MODE				0x8810 | 
 | 100 | #define PM2R_DITHER_MODE				0x8818 | 
 | 101 | #define PM2R_FB_SOFT_WRITE_MASK				0x8820 | 
 | 102 | #define PM2R_LOGICAL_OP_MODE				0x8828 | 
 | 103 | #define PM2R_LB_READ_MODE				0x8880 | 
 | 104 | #define PM2R_LB_READ_FORMAT				0x8888 | 
 | 105 | #define PM2R_LB_SOURCE_OFFSET				0x8890 | 
 | 106 | #define PM2R_LB_WINDOW_BASE				0x88b8 | 
 | 107 | #define PM2R_LB_WRITE_FORMAT				0x88c8 | 
 | 108 | #define PM2R_STENCIL_MODE				0x8988 | 
 | 109 | #define PM2R_DEPTH_MODE					0x89a0 | 
 | 110 | #define PM2R_FB_READ_MODE				0x8a80 | 
 | 111 | #define PM2R_FB_SOURCE_OFFSET				0x8a88 | 
 | 112 | #define PM2R_FB_PIXEL_OFFSET				0x8a90 | 
 | 113 | #define PM2R_FB_WINDOW_BASE				0x8ab0 | 
 | 114 | #define PM2R_FB_WRITE_MODE				0x8ab8 | 
 | 115 | #define PM2R_FB_HARD_WRITE_MASK				0x8ac0 | 
 | 116 | #define PM2R_FB_BLOCK_COLOR				0x8ac8 | 
 | 117 | #define PM2R_FB_READ_PIXEL				0x8ad0 | 
 | 118 | #define PM2R_FILTER_MODE				0x8c00 | 
 | 119 | #define PM2R_SYNC					0x8c40 | 
 | 120 | #define PM2R_YUV_MODE					0x8f00 | 
 | 121 | #define PM2R_STATISTICS_MODE				0x8c08 | 
 | 122 | #define PM2R_FB_SOURCE_DELTA				0x8d88 | 
 | 123 | #define PM2R_CONFIG					0x8d90 | 
 | 124 | #define PM2R_DELTA_MODE					0x9300 | 
 | 125 |  | 
 | 126 | /* Permedia2v */ | 
 | 127 | #define PM2VR_RD_INDEX_LOW				0x4020 | 
 | 128 | #define PM2VR_RD_INDEX_HIGH				0x4028 | 
 | 129 | #define PM2VR_RD_INDEXED_DATA				0x4030 | 
 | 130 |  | 
 | 131 | /* Permedia2 RAMDAC indexed registers */ | 
 | 132 | #define PM2I_RD_CURSOR_CONTROL				0x06 | 
 | 133 | #define PM2I_RD_COLOR_MODE				0x18 | 
 | 134 | #define PM2I_RD_MODE_CONTROL				0x19 | 
 | 135 | #define PM2I_RD_MISC_CONTROL				0x1e | 
 | 136 | #define PM2I_RD_PIXEL_CLOCK_A1				0x20 | 
 | 137 | #define PM2I_RD_PIXEL_CLOCK_A2				0x21 | 
 | 138 | #define PM2I_RD_PIXEL_CLOCK_A3				0x22 | 
 | 139 | #define PM2I_RD_PIXEL_CLOCK_STATUS			0x29 | 
 | 140 | #define PM2I_RD_MEMORY_CLOCK_1				0x30 | 
 | 141 | #define PM2I_RD_MEMORY_CLOCK_2				0x31 | 
 | 142 | #define PM2I_RD_MEMORY_CLOCK_3				0x32 | 
 | 143 | #define PM2I_RD_MEMORY_CLOCK_STATUS			0x33 | 
 | 144 | #define PM2I_RD_COLOR_KEY_CONTROL			0x40 | 
 | 145 | #define PM2I_RD_OVERLAY_KEY				0x41 | 
 | 146 | #define PM2I_RD_RED_KEY					0x42 | 
 | 147 | #define PM2I_RD_GREEN_KEY				0x43 | 
 | 148 | #define PM2I_RD_BLUE_KEY				0x44 | 
 | 149 |  | 
 | 150 | /* Permedia2v extensions */ | 
 | 151 | #define PM2VI_RD_MISC_CONTROL				0x000 | 
 | 152 | #define PM2VI_RD_SYNC_CONTROL				0x001 | 
 | 153 | #define PM2VI_RD_DAC_CONTROL				0x002 | 
 | 154 | #define PM2VI_RD_PIXEL_SIZE				0x003 | 
 | 155 | #define PM2VI_RD_COLOR_FORMAT				0x004 | 
 | 156 | #define PM2VI_RD_CURSOR_MODE				0x005 | 
 | 157 | #define PM2VI_RD_CURSOR_X_LOW				0x007 | 
 | 158 | #define PM2VI_RD_CURSOR_X_HIGH				0x008 | 
 | 159 | #define PM2VI_RD_CURSOR_Y_LOW				0x009 | 
 | 160 | #define PM2VI_RD_CURSOR_Y_HIGH				0x00A | 
 | 161 | #define PM2VI_RD_CURSOR_X_HOT				0x00B | 
 | 162 | #define PM2VI_RD_CURSOR_Y_HOT				0x00C | 
| Krzysztof Helt | 138a451 | 2007-10-16 01:28:36 -0700 | [diff] [blame] | 163 | #define PM2VI_RD_OVERLAY_KEY				0x00D | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | #define PM2VI_RD_CLK0_PRESCALE				0x201 | 
 | 165 | #define PM2VI_RD_CLK0_FEEDBACK				0x202 | 
 | 166 | #define PM2VI_RD_CLK0_POSTSCALE				0x203 | 
 | 167 | #define PM2VI_RD_CLK1_PRESCALE				0x204 | 
 | 168 | #define PM2VI_RD_CLK1_FEEDBACK				0x205 | 
 | 169 | #define PM2VI_RD_CLK1_POSTSCALE				0x206 | 
| Krzysztof Helt | e5d809d | 2007-05-08 00:39:32 -0700 | [diff] [blame] | 170 | #define PM2VI_RD_MCLK_CONTROL				0x20D | 
 | 171 | #define PM2VI_RD_MCLK_PRESCALE				0x20E | 
 | 172 | #define PM2VI_RD_MCLK_FEEDBACK				0x20F | 
 | 173 | #define PM2VI_RD_MCLK_POSTSCALE				0x210 | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 174 | #define PM2VI_RD_CURSOR_PALETTE				0x303 | 
 | 175 | #define PM2VI_RD_CURSOR_PATTERN				0x400 | 
 | 176 |  | 
 | 177 | /* Fields and flags */ | 
 | 178 | #define PM2F_RENDER_AREASTIPPLE				(1L<<0) | 
 | 179 | #define PM2F_RENDER_FASTFILL				(1L<<3) | 
 | 180 | #define PM2F_RENDER_PRIMITIVE_MASK			(3L<<6) | 
 | 181 | #define PM2F_RENDER_LINE				0 | 
 | 182 | #define PM2F_RENDER_TRAPEZOID				(1L<<6) | 
 | 183 | #define PM2F_RENDER_POINT				(2L<<6) | 
 | 184 | #define PM2F_RENDER_RECTANGLE				(3L<<6) | 
| Krzysztof Helt | 91b3a6f | 2007-10-16 01:28:34 -0700 | [diff] [blame] | 185 | #define PM2F_RENDER_SYNC_ON_BIT_MASK			(1L<<11) | 
 | 186 | #define PM2F_RENDER_TEXTURE_ENABLE			(1L<<13) | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 187 | #define PM2F_SYNCHRONIZATION				(1L<<10) | 
 | 188 | #define PM2F_PLL_LOCKED					0x10 | 
 | 189 | #define PM2F_BEING_RESET				(1L<<31) | 
 | 190 | #define PM2F_DATATYPE_COLOR				0x8000 | 
 | 191 | #define PM2F_VGA_ENABLE					0x02 | 
 | 192 | #define PM2F_VGA_FIXED					0x04 | 
 | 193 | #define PM2F_FB_WRITE_ENABLE				0x01 | 
 | 194 | #define PM2F_FB_READ_SOURCE_ENABLE			0x0200 | 
 | 195 | #define PM2F_RD_PALETTE_WIDTH_8				0x02 | 
 | 196 | #define PM2F_PART_PROD_MASK				0x01ff | 
 | 197 | #define PM2F_SCREEN_SCISSOR_ENABLE			0x02 | 
 | 198 | #define PM2F_DATA_64_ENABLE				0x00010000 | 
 | 199 | #define PM2F_BLANK_LOW					0x02 | 
 | 200 | #define PM2F_HSYNC_MASK					0x18 | 
 | 201 | #define PM2F_VSYNC_MASK					0x60 | 
 | 202 | #define PM2F_HSYNC_ACT_HIGH				0x08 | 
 | 203 | #define PM2F_HSYNC_FORCED_LOW				0x10 | 
 | 204 | #define PM2F_HSYNC_ACT_LOW				0x18 | 
 | 205 | #define PM2F_VSYNC_ACT_HIGH				0x20 | 
 | 206 | #define PM2F_VSYNC_FORCED_LOW				0x40 | 
 | 207 | #define PM2F_VSYNC_ACT_LOW				0x60 | 
 | 208 | #define PM2F_LINE_DOUBLE				0x04 | 
 | 209 | #define PM2F_VIDEO_ENABLE				0x01 | 
 | 210 | #define PM2F_RD_PIXELFORMAT_SVGA			0x01 | 
 | 211 | #define PM2F_RD_PIXELFORMAT_RGB232OFFSET		0x02 | 
 | 212 | #define PM2F_RD_PIXELFORMAT_RGBA2321			0x03 | 
 | 213 | #define PM2F_RD_PIXELFORMAT_RGBA5551			0x04 | 
 | 214 | #define PM2F_RD_PIXELFORMAT_RGBA4444			0x05 | 
 | 215 | #define PM2F_RD_PIXELFORMAT_RGB565			0x06 | 
 | 216 | #define PM2F_RD_PIXELFORMAT_RGBA8888			0x08 | 
 | 217 | #define PM2F_RD_PIXELFORMAT_RGB888			0x09 | 
 | 218 | #define PM2F_RD_GUI_ACTIVE				0x10 | 
 | 219 | #define PM2F_RD_COLOR_MODE_RGB				0x20 | 
 | 220 | #define PM2F_DELTA_ORDER_RGB				(1L<<18) | 
 | 221 | #define PM2F_RD_TRUECOLOR				0x80 | 
 | 222 | #define PM2F_NO_ALPHA_BUFFER				0x10 | 
 | 223 | #define PM2F_TEXTEL_SIZE_16				0x00080000 | 
 | 224 | #define PM2F_TEXTEL_SIZE_32				0x00100000 | 
 | 225 | #define PM2F_TEXTEL_SIZE_4				0x00180000 | 
 | 226 | #define PM2F_TEXTEL_SIZE_24				0x00200000 | 
 | 227 | #define PM2F_INCREASE_X					(1L<<21) | 
 | 228 | #define PM2F_INCREASE_Y					(1L<<22) | 
 | 229 | #define PM2F_CONFIG_FB_WRITE_ENABLE			(1L<<3) | 
 | 230 | #define PM2F_CONFIG_FB_PACKED_DATA			(1L<<2) | 
 | 231 | #define PM2F_CONFIG_FB_READ_DEST_ENABLE			(1L<<1) | 
 | 232 | #define PM2F_CONFIG_FB_READ_SOURCE_ENABLE		(1L<<0) | 
 | 233 | #define PM2F_COLOR_KEY_TEST_OFF				(1L<<4) | 
 | 234 | #define PM2F_MEM_CONFIG_RAM_MASK			(3L<<29) | 
 | 235 | #define PM2F_MEM_BANKS_1				0L | 
 | 236 | #define PM2F_MEM_BANKS_2				(1L<<29) | 
 | 237 | #define PM2F_MEM_BANKS_3				(2L<<29) | 
 | 238 | #define PM2F_MEM_BANKS_4				(3L<<29) | 
 | 239 | #define PM2F_APERTURE_STANDARD				0 | 
 | 240 | #define PM2F_APERTURE_BYTESWAP				1 | 
 | 241 | #define PM2F_APERTURE_HALFWORDSWAP			2 | 
| Krzysztof Helt | 8f5d050 | 2007-10-16 01:28:53 -0700 | [diff] [blame] | 242 | #define PM2F_CURSORMODE_CURSOR_ENABLE			(1 << 0) | 
 | 243 | #define PM2F_CURSORMODE_TYPE_X				(1 << 4) | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 244 |  | 
 | 245 | typedef enum { | 
 | 246 | 	PM2_TYPE_PERMEDIA2, | 
 | 247 | 	PM2_TYPE_PERMEDIA2V | 
 | 248 | } pm2type_t; | 
 | 249 |  | 
 | 250 | #endif /* PM2FB_H */ | 
 | 251 |  | 
 | 252 | /***************************************************************************** | 
 | 253 |  * That's all folks! | 
 | 254 |  *****************************************************************************/ |