blob: 5d60c9c259648b96d71dd5944576290b8e20622b [file] [log] [blame]
Jamie Iles1b8873a2010-02-02 20:25:44 +01001#undef DEBUG
2
3/*
4 * ARM performance counter support.
5 *
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
Will Deacon43eab872010-11-13 19:04:32 +00007 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
Jean PIHET796d1292010-01-26 18:51:05 +01008 *
Jamie Iles1b8873a2010-02-02 20:25:44 +01009 * This code is based on the sparc64 perf event code, which is in turn based
10 * on the x86 code. Callchain code is based on the ARM OProfile backtrace
11 * code.
12 */
13#define pr_fmt(fmt) "hw perfevents: " fmt
14
15#include <linux/interrupt.h>
16#include <linux/kernel.h>
Will Deacon181193f2010-04-30 11:32:44 +010017#include <linux/module.h>
Jamie Iles1b8873a2010-02-02 20:25:44 +010018#include <linux/perf_event.h>
Will Deacon49c006b2010-04-29 17:13:24 +010019#include <linux/platform_device.h>
Jamie Iles1b8873a2010-02-02 20:25:44 +010020#include <linux/spinlock.h>
21#include <linux/uaccess.h>
22
23#include <asm/cputype.h>
24#include <asm/irq.h>
25#include <asm/irq_regs.h>
26#include <asm/pmu.h>
27#include <asm/stacktrace.h>
28
Will Deacon49c006b2010-04-29 17:13:24 +010029static struct platform_device *pmu_device;
Jamie Iles1b8873a2010-02-02 20:25:44 +010030
31/*
32 * Hardware lock to serialize accesses to PMU registers. Needed for the
33 * read/modify/write sequences.
34 */
Will Deacon961ec6da2010-12-02 18:01:49 +010035static DEFINE_RAW_SPINLOCK(pmu_lock);
Jamie Iles1b8873a2010-02-02 20:25:44 +010036
37/*
Will Deaconecf5a892011-07-19 22:43:28 +010038 * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
Jamie Iles1b8873a2010-02-02 20:25:44 +010039 * another platform that supports more, we need to increase this to be the
40 * largest of all platforms.
Jean PIHET796d1292010-01-26 18:51:05 +010041 *
42 * ARMv7 supports up to 32 events:
43 * cycle counter CCNT + 31 events counters CNT0..30.
44 * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
Jamie Iles1b8873a2010-02-02 20:25:44 +010045 */
Will Deaconecf5a892011-07-19 22:43:28 +010046#define ARMPMU_MAX_HWEVENTS 32
Jamie Iles1b8873a2010-02-02 20:25:44 +010047
48/* The events for a given CPU. */
49struct cpu_hw_events {
50 /*
Will Deaconecf5a892011-07-19 22:43:28 +010051 * The events that are active on the CPU for the given index.
Jamie Iles1b8873a2010-02-02 20:25:44 +010052 */
53 struct perf_event *events[ARMPMU_MAX_HWEVENTS];
54
55 /*
56 * A 1 bit for an index indicates that the counter is being used for
57 * an event. A 0 means that the counter can be used.
58 */
59 unsigned long used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
60
61 /*
62 * A 1 bit for an index indicates that the counter is actively being
63 * used.
64 */
65 unsigned long active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
66};
Will Deacon4d6b7a72010-11-30 18:15:53 +010067static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
Will Deacon181193f2010-04-30 11:32:44 +010068
Jamie Iles1b8873a2010-02-02 20:25:44 +010069struct arm_pmu {
Will Deacon181193f2010-04-30 11:32:44 +010070 enum arm_perf_pmu_ids id;
Will Deacon0b390e22011-07-27 15:18:59 +010071 cpumask_t active_irqs;
Will Deacon62994832010-11-13 18:45:27 +000072 const char *name;
Jamie Iles1b8873a2010-02-02 20:25:44 +010073 irqreturn_t (*handle_irq)(int irq_num, void *dev);
74 void (*enable)(struct hw_perf_event *evt, int idx);
75 void (*disable)(struct hw_perf_event *evt, int idx);
Jamie Iles1b8873a2010-02-02 20:25:44 +010076 int (*get_event_idx)(struct cpu_hw_events *cpuc,
77 struct hw_perf_event *hwc);
Will Deacon05d22fd2011-07-19 11:57:30 +010078 int (*set_event_filter)(struct hw_perf_event *evt,
79 struct perf_event_attr *attr);
Jamie Iles1b8873a2010-02-02 20:25:44 +010080 u32 (*read_counter)(int idx);
81 void (*write_counter)(int idx, u32 val);
82 void (*start)(void);
83 void (*stop)(void);
Will Deacon574b69c2011-03-25 13:13:34 +010084 void (*reset)(void *);
Will Deacon84fee972010-11-13 17:13:56 +000085 const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
86 [PERF_COUNT_HW_CACHE_OP_MAX]
87 [PERF_COUNT_HW_CACHE_RESULT_MAX];
88 const unsigned (*event_map)[PERF_COUNT_HW_MAX];
89 u32 raw_event_mask;
Jamie Iles1b8873a2010-02-02 20:25:44 +010090 int num_events;
91 u64 max_period;
92};
93
94/* Set at runtime when we know what CPU type we are. */
Mark Rutlanda6c93af2011-04-15 11:14:38 +010095static struct arm_pmu *armpmu;
Jamie Iles1b8873a2010-02-02 20:25:44 +010096
Will Deacon181193f2010-04-30 11:32:44 +010097enum arm_perf_pmu_ids
98armpmu_get_pmu_id(void)
99{
100 int id = -ENODEV;
101
102 if (armpmu != NULL)
103 id = armpmu->id;
104
105 return id;
106}
107EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
108
Will Deacon929f5192010-04-30 11:34:26 +0100109int
110armpmu_get_max_events(void)
111{
112 int max_events = 0;
113
114 if (armpmu != NULL)
115 max_events = armpmu->num_events;
116
117 return max_events;
118}
119EXPORT_SYMBOL_GPL(armpmu_get_max_events);
120
Matt Fleming3bf101b2010-09-27 20:22:24 +0100121int perf_num_counters(void)
122{
123 return armpmu_get_max_events();
124}
125EXPORT_SYMBOL_GPL(perf_num_counters);
126
Jamie Iles1b8873a2010-02-02 20:25:44 +0100127#define HW_OP_UNSUPPORTED 0xFFFF
128
129#define C(_x) \
130 PERF_COUNT_HW_CACHE_##_x
131
132#define CACHE_OP_UNSUPPORTED 0xFFFF
133
Jamie Iles1b8873a2010-02-02 20:25:44 +0100134static int
135armpmu_map_cache_event(u64 config)
136{
137 unsigned int cache_type, cache_op, cache_result, ret;
138
139 cache_type = (config >> 0) & 0xff;
140 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
141 return -EINVAL;
142
143 cache_op = (config >> 8) & 0xff;
144 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
145 return -EINVAL;
146
147 cache_result = (config >> 16) & 0xff;
148 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
149 return -EINVAL;
150
Will Deacon84fee972010-11-13 17:13:56 +0000151 ret = (int)(*armpmu->cache_map)[cache_type][cache_op][cache_result];
Jamie Iles1b8873a2010-02-02 20:25:44 +0100152
153 if (ret == CACHE_OP_UNSUPPORTED)
154 return -ENOENT;
155
156 return ret;
157}
158
159static int
Will Deacon84fee972010-11-13 17:13:56 +0000160armpmu_map_event(u64 config)
161{
162 int mapping = (*armpmu->event_map)[config];
163 return mapping == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : mapping;
164}
165
166static int
167armpmu_map_raw_event(u64 config)
168{
169 return (int)(config & armpmu->raw_event_mask);
170}
171
172static int
Jamie Iles1b8873a2010-02-02 20:25:44 +0100173armpmu_event_set_period(struct perf_event *event,
174 struct hw_perf_event *hwc,
175 int idx)
176{
Peter Zijlstrae7850592010-05-21 14:43:08 +0200177 s64 left = local64_read(&hwc->period_left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100178 s64 period = hwc->sample_period;
179 int ret = 0;
180
181 if (unlikely(left <= -period)) {
182 left = period;
Peter Zijlstrae7850592010-05-21 14:43:08 +0200183 local64_set(&hwc->period_left, left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100184 hwc->last_period = period;
185 ret = 1;
186 }
187
188 if (unlikely(left <= 0)) {
189 left += period;
Peter Zijlstrae7850592010-05-21 14:43:08 +0200190 local64_set(&hwc->period_left, left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100191 hwc->last_period = period;
192 ret = 1;
193 }
194
195 if (left > (s64)armpmu->max_period)
196 left = armpmu->max_period;
197
Peter Zijlstrae7850592010-05-21 14:43:08 +0200198 local64_set(&hwc->prev_count, (u64)-left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100199
200 armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
201
202 perf_event_update_userpage(event);
203
204 return ret;
205}
206
207static u64
208armpmu_event_update(struct perf_event *event,
209 struct hw_perf_event *hwc,
Will Deacona7378232011-03-25 17:12:37 +0100210 int idx, int overflow)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100211{
Will Deacona7378232011-03-25 17:12:37 +0100212 u64 delta, prev_raw_count, new_raw_count;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100213
214again:
Peter Zijlstrae7850592010-05-21 14:43:08 +0200215 prev_raw_count = local64_read(&hwc->prev_count);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100216 new_raw_count = armpmu->read_counter(idx);
217
Peter Zijlstrae7850592010-05-21 14:43:08 +0200218 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
Jamie Iles1b8873a2010-02-02 20:25:44 +0100219 new_raw_count) != prev_raw_count)
220 goto again;
221
Will Deacona7378232011-03-25 17:12:37 +0100222 new_raw_count &= armpmu->max_period;
223 prev_raw_count &= armpmu->max_period;
224
225 if (overflow)
Will Deacon67597882011-04-05 14:01:24 +0100226 delta = armpmu->max_period - prev_raw_count + new_raw_count + 1;
Will Deacona7378232011-03-25 17:12:37 +0100227 else
228 delta = new_raw_count - prev_raw_count;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100229
Peter Zijlstrae7850592010-05-21 14:43:08 +0200230 local64_add(delta, &event->count);
231 local64_sub(delta, &hwc->period_left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100232
233 return new_raw_count;
234}
235
236static void
Jamie Iles1b8873a2010-02-02 20:25:44 +0100237armpmu_read(struct perf_event *event)
238{
239 struct hw_perf_event *hwc = &event->hw;
240
241 /* Don't read disabled counters! */
242 if (hwc->idx < 0)
243 return;
244
Will Deacona7378232011-03-25 17:12:37 +0100245 armpmu_event_update(event, hwc, hwc->idx, 0);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100246}
247
248static void
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200249armpmu_stop(struct perf_event *event, int flags)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100250{
251 struct hw_perf_event *hwc = &event->hw;
252
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200253 if (!armpmu)
254 return;
255
256 /*
257 * ARM pmu always has to update the counter, so ignore
258 * PERF_EF_UPDATE, see comments in armpmu_start().
259 */
260 if (!(hwc->state & PERF_HES_STOPPED)) {
261 armpmu->disable(hwc, hwc->idx);
262 barrier(); /* why? */
Will Deacona7378232011-03-25 17:12:37 +0100263 armpmu_event_update(event, hwc, hwc->idx, 0);
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200264 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
265 }
266}
267
268static void
269armpmu_start(struct perf_event *event, int flags)
270{
271 struct hw_perf_event *hwc = &event->hw;
272
273 if (!armpmu)
274 return;
275
276 /*
277 * ARM pmu always has to reprogram the period, so ignore
278 * PERF_EF_RELOAD, see the comment below.
279 */
280 if (flags & PERF_EF_RELOAD)
281 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
282
283 hwc->state = 0;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100284 /*
285 * Set the period again. Some counters can't be stopped, so when we
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200286 * were stopped we simply disabled the IRQ source and the counter
Jamie Iles1b8873a2010-02-02 20:25:44 +0100287 * may have been left counting. If we don't do this step then we may
288 * get an interrupt too soon or *way* too late if the overflow has
289 * happened since disabling.
290 */
291 armpmu_event_set_period(event, hwc, hwc->idx);
292 armpmu->enable(hwc, hwc->idx);
293}
294
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200295static void
296armpmu_del(struct perf_event *event, int flags)
297{
298 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
299 struct hw_perf_event *hwc = &event->hw;
300 int idx = hwc->idx;
301
302 WARN_ON(idx < 0);
303
304 clear_bit(idx, cpuc->active_mask);
305 armpmu_stop(event, PERF_EF_UPDATE);
306 cpuc->events[idx] = NULL;
307 clear_bit(idx, cpuc->used_mask);
308
309 perf_event_update_userpage(event);
310}
311
Jamie Iles1b8873a2010-02-02 20:25:44 +0100312static int
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200313armpmu_add(struct perf_event *event, int flags)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100314{
315 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
316 struct hw_perf_event *hwc = &event->hw;
317 int idx;
318 int err = 0;
319
Peter Zijlstra33696fc2010-06-14 08:49:00 +0200320 perf_pmu_disable(event->pmu);
Peter Zijlstra24cd7f52010-06-11 17:32:03 +0200321
Jamie Iles1b8873a2010-02-02 20:25:44 +0100322 /* If we don't have a space for the counter then finish early. */
323 idx = armpmu->get_event_idx(cpuc, hwc);
324 if (idx < 0) {
325 err = idx;
326 goto out;
327 }
328
329 /*
330 * If there is an event in the counter we are going to use then make
331 * sure it is disabled.
332 */
333 event->hw.idx = idx;
334 armpmu->disable(hwc, idx);
335 cpuc->events[idx] = event;
336 set_bit(idx, cpuc->active_mask);
337
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200338 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
339 if (flags & PERF_EF_START)
340 armpmu_start(event, PERF_EF_RELOAD);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100341
342 /* Propagate our changes to the userspace mapping. */
343 perf_event_update_userpage(event);
344
345out:
Peter Zijlstra33696fc2010-06-14 08:49:00 +0200346 perf_pmu_enable(event->pmu);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100347 return err;
348}
349
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200350static struct pmu pmu;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100351
352static int
353validate_event(struct cpu_hw_events *cpuc,
354 struct perf_event *event)
355{
356 struct hw_perf_event fake_event = event->hw;
357
Will Deacon65b47112010-09-02 09:32:08 +0100358 if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF)
359 return 1;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100360
361 return armpmu->get_event_idx(cpuc, &fake_event) >= 0;
362}
363
364static int
365validate_group(struct perf_event *event)
366{
367 struct perf_event *sibling, *leader = event->group_leader;
368 struct cpu_hw_events fake_pmu;
369
370 memset(&fake_pmu, 0, sizeof(fake_pmu));
371
372 if (!validate_event(&fake_pmu, leader))
373 return -ENOSPC;
374
375 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
376 if (!validate_event(&fake_pmu, sibling))
377 return -ENOSPC;
378 }
379
380 if (!validate_event(&fake_pmu, event))
381 return -ENOSPC;
382
383 return 0;
384}
385
Rabin Vincent0e25a5c2011-02-08 09:24:36 +0530386static irqreturn_t armpmu_platform_irq(int irq, void *dev)
387{
388 struct arm_pmu_platdata *plat = dev_get_platdata(&pmu_device->dev);
389
390 return plat->handle_irq(irq, dev, armpmu->handle_irq);
391}
392
Will Deacon0b390e22011-07-27 15:18:59 +0100393static void
394armpmu_release_hardware(void)
395{
396 int i, irq, irqs;
397
398 irqs = min(pmu_device->num_resources, num_possible_cpus());
399
400 for (i = 0; i < irqs; ++i) {
401 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
402 continue;
403 irq = platform_get_irq(pmu_device, i);
404 if (irq >= 0)
405 free_irq(irq, NULL);
406 }
407
408 armpmu->stop();
409 release_pmu(ARM_PMU_DEVICE_CPU);
410}
411
Jamie Iles1b8873a2010-02-02 20:25:44 +0100412static int
413armpmu_reserve_hardware(void)
414{
Rabin Vincent0e25a5c2011-02-08 09:24:36 +0530415 struct arm_pmu_platdata *plat;
416 irq_handler_t handle_irq;
Will Deaconb0e89592011-07-26 22:10:28 +0100417 int i, err, irq, irqs;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100418
Will Deaconb0e89592011-07-26 22:10:28 +0100419 err = reserve_pmu(ARM_PMU_DEVICE_CPU);
420 if (err) {
Jamie Iles1b8873a2010-02-02 20:25:44 +0100421 pr_warning("unable to reserve pmu\n");
Will Deaconb0e89592011-07-26 22:10:28 +0100422 return err;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100423 }
424
Rabin Vincent0e25a5c2011-02-08 09:24:36 +0530425 plat = dev_get_platdata(&pmu_device->dev);
426 if (plat && plat->handle_irq)
427 handle_irq = armpmu_platform_irq;
428 else
429 handle_irq = armpmu->handle_irq;
430
Will Deacon0b390e22011-07-27 15:18:59 +0100431 irqs = min(pmu_device->num_resources, num_possible_cpus());
Will Deaconb0e89592011-07-26 22:10:28 +0100432 if (irqs < 1) {
Jamie Iles1b8873a2010-02-02 20:25:44 +0100433 pr_err("no irqs for PMUs defined\n");
434 return -ENODEV;
435 }
436
Will Deaconb0e89592011-07-26 22:10:28 +0100437 for (i = 0; i < irqs; ++i) {
Will Deacon0b390e22011-07-27 15:18:59 +0100438 err = 0;
Will Deacon49c006b2010-04-29 17:13:24 +0100439 irq = platform_get_irq(pmu_device, i);
440 if (irq < 0)
441 continue;
442
Will Deaconb0e89592011-07-26 22:10:28 +0100443 /*
444 * If we have a single PMU interrupt that we can't shift,
445 * assume that we're running on a uniprocessor machine and
Will Deacon0b390e22011-07-27 15:18:59 +0100446 * continue. Otherwise, continue without this interrupt.
Will Deaconb0e89592011-07-26 22:10:28 +0100447 */
Will Deacon0b390e22011-07-27 15:18:59 +0100448 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
449 pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
450 irq, i);
451 continue;
Will Deaconb0e89592011-07-26 22:10:28 +0100452 }
453
Rabin Vincent0e25a5c2011-02-08 09:24:36 +0530454 err = request_irq(irq, handle_irq,
Will Deaconddee87f2010-02-25 15:04:14 +0100455 IRQF_DISABLED | IRQF_NOBALANCING,
Will Deaconb0e89592011-07-26 22:10:28 +0100456 "arm-pmu", NULL);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100457 if (err) {
Will Deaconb0e89592011-07-26 22:10:28 +0100458 pr_err("unable to request IRQ%d for ARM PMU counters\n",
459 irq);
Will Deacon0b390e22011-07-27 15:18:59 +0100460 armpmu_release_hardware();
461 return err;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100462 }
Will Deacon0b390e22011-07-27 15:18:59 +0100463
464 cpumask_set_cpu(i, &armpmu->active_irqs);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100465 }
466
Will Deacon0b390e22011-07-27 15:18:59 +0100467 return 0;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100468}
469
470static atomic_t active_events = ATOMIC_INIT(0);
471static DEFINE_MUTEX(pmu_reserve_mutex);
472
473static void
474hw_perf_event_destroy(struct perf_event *event)
475{
476 if (atomic_dec_and_mutex_lock(&active_events, &pmu_reserve_mutex)) {
477 armpmu_release_hardware();
478 mutex_unlock(&pmu_reserve_mutex);
479 }
480}
481
482static int
Will Deacon05d22fd2011-07-19 11:57:30 +0100483event_requires_mode_exclusion(struct perf_event_attr *attr)
484{
485 return attr->exclude_idle || attr->exclude_user ||
486 attr->exclude_kernel || attr->exclude_hv;
487}
488
489static int
Jamie Iles1b8873a2010-02-02 20:25:44 +0100490__hw_perf_event_init(struct perf_event *event)
491{
492 struct hw_perf_event *hwc = &event->hw;
493 int mapping, err;
494
495 /* Decode the generic type into an ARM event identifier. */
496 if (PERF_TYPE_HARDWARE == event->attr.type) {
Will Deacon84fee972010-11-13 17:13:56 +0000497 mapping = armpmu_map_event(event->attr.config);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100498 } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
499 mapping = armpmu_map_cache_event(event->attr.config);
500 } else if (PERF_TYPE_RAW == event->attr.type) {
Will Deacon84fee972010-11-13 17:13:56 +0000501 mapping = armpmu_map_raw_event(event->attr.config);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100502 } else {
503 pr_debug("event type %x not supported\n", event->attr.type);
504 return -EOPNOTSUPP;
505 }
506
507 if (mapping < 0) {
508 pr_debug("event %x:%llx not supported\n", event->attr.type,
509 event->attr.config);
510 return mapping;
511 }
512
513 /*
Will Deacon05d22fd2011-07-19 11:57:30 +0100514 * We don't assign an index until we actually place the event onto
515 * hardware. Use -1 to signify that we haven't decided where to put it
516 * yet. For SMP systems, each core has it's own PMU so we can't do any
517 * clever allocation or constraints checking at this point.
Jamie Iles1b8873a2010-02-02 20:25:44 +0100518 */
Will Deacon05d22fd2011-07-19 11:57:30 +0100519 hwc->idx = -1;
520 hwc->config_base = 0;
521 hwc->config = 0;
522 hwc->event_base = 0;
523
524 /*
525 * Check whether we need to exclude the counter from certain modes.
526 */
527 if ((!armpmu->set_event_filter ||
528 armpmu->set_event_filter(hwc, &event->attr)) &&
529 event_requires_mode_exclusion(&event->attr)) {
Jamie Iles1b8873a2010-02-02 20:25:44 +0100530 pr_debug("ARM performance counters do not support "
531 "mode exclusion\n");
532 return -EPERM;
533 }
534
535 /*
Will Deacon05d22fd2011-07-19 11:57:30 +0100536 * Store the event encoding into the config_base field.
Jamie Iles1b8873a2010-02-02 20:25:44 +0100537 */
Will Deacon05d22fd2011-07-19 11:57:30 +0100538 hwc->config_base |= (unsigned long)mapping;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100539
540 if (!hwc->sample_period) {
541 hwc->sample_period = armpmu->max_period;
542 hwc->last_period = hwc->sample_period;
Peter Zijlstrae7850592010-05-21 14:43:08 +0200543 local64_set(&hwc->period_left, hwc->sample_period);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100544 }
545
546 err = 0;
547 if (event->group_leader != event) {
548 err = validate_group(event);
549 if (err)
550 return -EINVAL;
551 }
552
553 return err;
554}
555
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200556static int armpmu_event_init(struct perf_event *event)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100557{
558 int err = 0;
559
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200560 switch (event->attr.type) {
561 case PERF_TYPE_RAW:
562 case PERF_TYPE_HARDWARE:
563 case PERF_TYPE_HW_CACHE:
564 break;
565
566 default:
567 return -ENOENT;
568 }
569
Jamie Iles1b8873a2010-02-02 20:25:44 +0100570 if (!armpmu)
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200571 return -ENODEV;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100572
573 event->destroy = hw_perf_event_destroy;
574
575 if (!atomic_inc_not_zero(&active_events)) {
Jamie Iles1b8873a2010-02-02 20:25:44 +0100576 mutex_lock(&pmu_reserve_mutex);
577 if (atomic_read(&active_events) == 0) {
578 err = armpmu_reserve_hardware();
579 }
580
581 if (!err)
582 atomic_inc(&active_events);
583 mutex_unlock(&pmu_reserve_mutex);
584 }
585
586 if (err)
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200587 return err;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100588
589 err = __hw_perf_event_init(event);
590 if (err)
591 hw_perf_event_destroy(event);
592
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200593 return err;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100594}
595
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200596static void armpmu_enable(struct pmu *pmu)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100597{
598 /* Enable all of the perf events on hardware. */
Will Deaconf4f38432011-07-01 14:38:12 +0100599 int idx, enabled = 0;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100600 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
601
602 if (!armpmu)
603 return;
604
Will Deaconecf5a892011-07-19 22:43:28 +0100605 for (idx = 0; idx < armpmu->num_events; ++idx) {
Jamie Iles1b8873a2010-02-02 20:25:44 +0100606 struct perf_event *event = cpuc->events[idx];
607
608 if (!event)
609 continue;
610
611 armpmu->enable(&event->hw, idx);
Will Deaconf4f38432011-07-01 14:38:12 +0100612 enabled = 1;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100613 }
614
Will Deaconf4f38432011-07-01 14:38:12 +0100615 if (enabled)
616 armpmu->start();
Jamie Iles1b8873a2010-02-02 20:25:44 +0100617}
618
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200619static void armpmu_disable(struct pmu *pmu)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100620{
621 if (armpmu)
622 armpmu->stop();
623}
624
Peter Zijlstra33696fc2010-06-14 08:49:00 +0200625static struct pmu pmu = {
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200626 .pmu_enable = armpmu_enable,
627 .pmu_disable = armpmu_disable,
628 .event_init = armpmu_event_init,
629 .add = armpmu_add,
630 .del = armpmu_del,
631 .start = armpmu_start,
632 .stop = armpmu_stop,
633 .read = armpmu_read,
Peter Zijlstra33696fc2010-06-14 08:49:00 +0200634};
635
Will Deacon43eab872010-11-13 19:04:32 +0000636/* Include the PMU-specific implementations. */
637#include "perf_event_xscale.c"
638#include "perf_event_v6.c"
639#include "perf_event_v7.c"
Will Deacon49e6a322010-04-30 11:33:33 +0100640
Will Deacon574b69c2011-03-25 13:13:34 +0100641/*
642 * Ensure the PMU has sane values out of reset.
643 * This requires SMP to be available, so exists as a separate initcall.
644 */
645static int __init
646armpmu_reset(void)
647{
648 if (armpmu && armpmu->reset)
649 return on_each_cpu(armpmu->reset, NULL, 1);
650 return 0;
651}
652arch_initcall(armpmu_reset);
653
Will Deaconb0e89592011-07-26 22:10:28 +0100654/*
655 * PMU platform driver and devicetree bindings.
656 */
657static struct of_device_id armpmu_of_device_ids[] = {
658 {.compatible = "arm,cortex-a9-pmu"},
659 {.compatible = "arm,cortex-a8-pmu"},
660 {.compatible = "arm,arm1136-pmu"},
661 {.compatible = "arm,arm1176-pmu"},
662 {},
663};
664
665static struct platform_device_id armpmu_plat_device_ids[] = {
666 {.name = "arm-pmu"},
667 {},
668};
669
670static int __devinit armpmu_device_probe(struct platform_device *pdev)
671{
672 pmu_device = pdev;
673 return 0;
674}
675
676static struct platform_driver armpmu_driver = {
677 .driver = {
678 .name = "arm-pmu",
679 .of_match_table = armpmu_of_device_ids,
680 },
681 .probe = armpmu_device_probe,
682 .id_table = armpmu_plat_device_ids,
683};
684
685static int __init register_pmu_driver(void)
686{
687 return platform_driver_register(&armpmu_driver);
688}
689device_initcall(register_pmu_driver);
690
691/*
692 * CPU PMU identification and registration.
693 */
Jamie Iles1b8873a2010-02-02 20:25:44 +0100694static int __init
695init_hw_perf_events(void)
696{
697 unsigned long cpuid = read_cpuid_id();
698 unsigned long implementor = (cpuid & 0xFF000000) >> 24;
699 unsigned long part_number = (cpuid & 0xFFF0);
700
Will Deacon49e6a322010-04-30 11:33:33 +0100701 /* ARM Ltd CPUs. */
Jamie Iles1b8873a2010-02-02 20:25:44 +0100702 if (0x41 == implementor) {
703 switch (part_number) {
704 case 0xB360: /* ARM1136 */
705 case 0xB560: /* ARM1156 */
706 case 0xB760: /* ARM1176 */
Will Deacon3cb314b2010-11-13 17:37:46 +0000707 armpmu = armv6pmu_init();
Jamie Iles1b8873a2010-02-02 20:25:44 +0100708 break;
709 case 0xB020: /* ARM11mpcore */
Will Deacon3cb314b2010-11-13 17:37:46 +0000710 armpmu = armv6mpcore_pmu_init();
Jamie Iles1b8873a2010-02-02 20:25:44 +0100711 break;
Jean PIHET796d1292010-01-26 18:51:05 +0100712 case 0xC080: /* Cortex-A8 */
Will Deacon3cb314b2010-11-13 17:37:46 +0000713 armpmu = armv7_a8_pmu_init();
Jean PIHET796d1292010-01-26 18:51:05 +0100714 break;
715 case 0xC090: /* Cortex-A9 */
Will Deacon3cb314b2010-11-13 17:37:46 +0000716 armpmu = armv7_a9_pmu_init();
Jean PIHET796d1292010-01-26 18:51:05 +0100717 break;
Will Deacon0c205cb2011-06-03 17:40:15 +0100718 case 0xC050: /* Cortex-A5 */
719 armpmu = armv7_a5_pmu_init();
720 break;
Will Deacon14abd032011-01-19 14:24:38 +0000721 case 0xC0F0: /* Cortex-A15 */
722 armpmu = armv7_a15_pmu_init();
723 break;
Will Deacon49e6a322010-04-30 11:33:33 +0100724 }
725 /* Intel CPUs [xscale]. */
726 } else if (0x69 == implementor) {
727 part_number = (cpuid >> 13) & 0x7;
728 switch (part_number) {
729 case 1:
Will Deacon3cb314b2010-11-13 17:37:46 +0000730 armpmu = xscale1pmu_init();
Will Deacon49e6a322010-04-30 11:33:33 +0100731 break;
732 case 2:
Will Deacon3cb314b2010-11-13 17:37:46 +0000733 armpmu = xscale2pmu_init();
Will Deacon49e6a322010-04-30 11:33:33 +0100734 break;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100735 }
736 }
737
Will Deacon49e6a322010-04-30 11:33:33 +0100738 if (armpmu) {
Jean PIHET796d1292010-01-26 18:51:05 +0100739 pr_info("enabled with %s PMU driver, %d counters available\n",
Will Deacon62994832010-11-13 18:45:27 +0000740 armpmu->name, armpmu->num_events);
Will Deacon49e6a322010-04-30 11:33:33 +0100741 } else {
742 pr_info("no hardware support available\n");
Will Deacon49e6a322010-04-30 11:33:33 +0100743 }
Jamie Iles1b8873a2010-02-02 20:25:44 +0100744
Peter Zijlstra2e80a822010-11-17 23:17:36 +0100745 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200746
Jamie Iles1b8873a2010-02-02 20:25:44 +0100747 return 0;
748}
Peter Zijlstra004417a2010-11-25 18:38:29 +0100749early_initcall(init_hw_perf_events);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100750
751/*
752 * Callchain handling code.
753 */
Jamie Iles1b8873a2010-02-02 20:25:44 +0100754
755/*
756 * The registers we're interested in are at the end of the variable
757 * length saved register structure. The fp points at the end of this
758 * structure so the address of this struct is:
759 * (struct frame_tail *)(xxx->fp)-1
760 *
761 * This code has been adapted from the ARM OProfile support.
762 */
763struct frame_tail {
Will Deacon4d6b7a72010-11-30 18:15:53 +0100764 struct frame_tail __user *fp;
765 unsigned long sp;
766 unsigned long lr;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100767} __attribute__((packed));
768
769/*
770 * Get the return address for a single stackframe and return a pointer to the
771 * next frame tail.
772 */
Will Deacon4d6b7a72010-11-30 18:15:53 +0100773static struct frame_tail __user *
774user_backtrace(struct frame_tail __user *tail,
Jamie Iles1b8873a2010-02-02 20:25:44 +0100775 struct perf_callchain_entry *entry)
776{
777 struct frame_tail buftail;
778
779 /* Also check accessibility of one struct frame_tail beyond */
780 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
781 return NULL;
782 if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
783 return NULL;
784
Frederic Weisbecker70791ce2010-06-29 19:34:05 +0200785 perf_callchain_store(entry, buftail.lr);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100786
787 /*
788 * Frame pointers should strictly progress back up the stack
789 * (towards higher addresses).
790 */
Rabin Vincentcb061992011-02-09 11:35:12 +0100791 if (tail + 1 >= buftail.fp)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100792 return NULL;
793
794 return buftail.fp - 1;
795}
796
Frederic Weisbecker56962b42010-06-30 23:03:51 +0200797void
798perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100799{
Will Deacon4d6b7a72010-11-30 18:15:53 +0100800 struct frame_tail __user *tail;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100801
Jamie Iles1b8873a2010-02-02 20:25:44 +0100802
Will Deacon4d6b7a72010-11-30 18:15:53 +0100803 tail = (struct frame_tail __user *)regs->ARM_fp - 1;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100804
Sonny Rao860ad782011-04-18 22:12:59 +0100805 while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
806 tail && !((unsigned long)tail & 0x3))
Jamie Iles1b8873a2010-02-02 20:25:44 +0100807 tail = user_backtrace(tail, entry);
808}
809
810/*
811 * Gets called by walk_stackframe() for every stackframe. This will be called
812 * whist unwinding the stackframe and is like a subroutine return so we use
813 * the PC.
814 */
815static int
816callchain_trace(struct stackframe *fr,
817 void *data)
818{
819 struct perf_callchain_entry *entry = data;
Frederic Weisbecker70791ce2010-06-29 19:34:05 +0200820 perf_callchain_store(entry, fr->pc);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100821 return 0;
822}
823
Frederic Weisbecker56962b42010-06-30 23:03:51 +0200824void
825perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100826{
827 struct stackframe fr;
828
Jamie Iles1b8873a2010-02-02 20:25:44 +0100829 fr.fp = regs->ARM_fp;
830 fr.sp = regs->ARM_sp;
831 fr.lr = regs->ARM_lr;
832 fr.pc = regs->ARM_pc;
833 walk_stackframe(&fr, callchain_trace, entry);
834}