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review.evervolv.com / android_kernel_oneplus_msm8996 / 05e57eec23eadf6641911ff07560f9ec7c6457c1 / . / arch / powerpc / boot / dts / p4080ds.dts
blob: efa00911f12be6b45bf61123311513db397b4845 [file] [log] [blame]
Kumar Galaab2f4892009-10-22 16:35:07 -0500[diff] [blame]1/*
2 * P4080DS Device Tree Source
3 *
4 * Copyright 2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "fsl,P4080DS";
16 compatible = "fsl,P4080DS";
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 ccsr = &soc;
22
23 serial0 = &serial0;
24 serial1 = &serial1;
25 serial2 = &serial2;
26 serial3 = &serial3;
27 pci0 = &pci0;
28 pci1 = &pci1;
29 pci2 = &pci2;
30 usb0 = &usb0;
31 usb1 = &usb1;
32 dma0 = &dma0;
33 dma1 = &dma1;
34 sdhc = &sdhc;
35
36 rio0 = &rapidio0;
37 };
38
39 cpus {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 cpu0: PowerPC,4080@0 {
44 device_type = "cpu";
45 reg = <0>;
46 next-level-cache = <&L2_0>;
47 L2_0: l2-cache {
48 };
49 };
50 cpu1: PowerPC,4080@1 {
51 device_type = "cpu";
52 reg = <1>;
53 next-level-cache = <&L2_1>;
54 L2_1: l2-cache {
55 };
56 };
57 cpu2: PowerPC,4080@2 {
58 device_type = "cpu";
59 reg = <2>;
60 next-level-cache = <&L2_2>;
61 L2_2: l2-cache {
62 };
63 };
64 cpu3: PowerPC,4080@3 {
65 device_type = "cpu";
66 reg = <3>;
67 next-level-cache = <&L2_3>;
68 L2_3: l2-cache {
69 };
70 };
71 cpu4: PowerPC,4080@4 {
72 device_type = "cpu";
73 reg = <4>;
74 next-level-cache = <&L2_4>;
75 L2_4: l2-cache {
76 };
77 };
78 cpu5: PowerPC,4080@5 {
79 device_type = "cpu";
80 reg = <5>;
81 next-level-cache = <&L2_5>;
82 L2_5: l2-cache {
83 };
84 };
85 cpu6: PowerPC,4080@6 {
86 device_type = "cpu";
87 reg = <6>;
88 next-level-cache = <&L2_6>;
89 L2_6: l2-cache {
90 };
91 };
92 cpu7: PowerPC,4080@7 {
93 device_type = "cpu";
94 reg = <7>;
95 next-level-cache = <&L2_7>;
96 L2_7: l2-cache {
97 };
98 };
99 };
100
101 memory {
102 device_type = "memory";
103 };
104
105 soc: soc@ffe000000 {
106 #address-cells = <1>;
107 #size-cells = <1>;
108 device_type = "soc";
109 compatible = "simple-bus";
110 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
111 reg = <0xf 0xfe000000 0 0x00001000>;
112
113 corenet-law@0 {
114 compatible = "fsl,corenet-law";
115 reg = <0x0 0x1000>;
116 fsl,num-laws = <32>;
117 };
118
119 memory-controller@8000 {
120 compatible = "fsl,p4080-memory-controller";
121 reg = <0x8000 0x1000>;
122 interrupt-parent = <&mpic>;
123 interrupts = <0x12 2>;
124 };
125
126 memory-controller@9000 {
127 compatible = "fsl,p4080-memory-controller";
128 reg = <0x9000 0x1000>;
129 interrupt-parent = <&mpic>;
130 interrupts = <0x12 2>;
131 };
132
133 corenet-cf@18000 {
134 compatible = "fsl,corenet-cf";
135 reg = <0x18000 0x1000>;
136 fsl,ccf-num-csdids = <32>;
137 fsl,ccf-num-snoopids = <32>;
138 };
139
140 iommu@20000 {
141 compatible = "fsl,p4080-pamu";
142 reg = <0x20000 0x10000>;
143 interrupts = <24 2>;
144 interrupt-parent = <&mpic>;
145 };
146
147 mpic: pic@40000 {
148 interrupt-controller;
149 #address-cells = <0>;
150 #interrupt-cells = <2>;
151 reg = <0x40000 0x40000>;
152 compatible = "chrp,open-pic";
153 device_type = "open-pic";
154 };
155
156 dma0: dma@100300 {
157 #address-cells = <1>;
158 #size-cells = <1>;
159 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
160 reg = <0x100300 0x4>;
161 ranges = <0x0 0x100100 0x200>;
162 cell-index = <0>;
163 dma-channel@0 {
164 compatible = "fsl,p4080-dma-channel",
165 "fsl,eloplus-dma-channel";
166 reg = <0x0 0x80>;
167 cell-index = <0>;
168 interrupt-parent = <&mpic>;
169 interrupts = <28 2>;
170 };
171 dma-channel@80 {
172 compatible = "fsl,p4080-dma-channel",
173 "fsl,eloplus-dma-channel";
174 reg = <0x80 0x80>;
175 cell-index = <1>;
176 interrupt-parent = <&mpic>;
177 interrupts = <29 2>;
178 };
179 dma-channel@100 {
180 compatible = "fsl,p4080-dma-channel",
181 "fsl,eloplus-dma-channel";
182 reg = <0x100 0x80>;
183 cell-index = <2>;
184 interrupt-parent = <&mpic>;
185 interrupts = <30 2>;
186 };
187 dma-channel@180 {
188 compatible = "fsl,p4080-dma-channel",
189 "fsl,eloplus-dma-channel";
190 reg = <0x180 0x80>;
191 cell-index = <3>;
192 interrupt-parent = <&mpic>;
193 interrupts = <31 2>;
194 };
195 };
196
197 dma1: dma@101300 {
198 #address-cells = <1>;
199 #size-cells = <1>;
200 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
201 reg = <0x101300 0x4>;
202 ranges = <0x0 0x101100 0x200>;
203 cell-index = <1>;
204 dma-channel@0 {
205 compatible = "fsl,p4080-dma-channel",
206 "fsl,eloplus-dma-channel";
207 reg = <0x0 0x80>;
208 cell-index = <0>;
209 interrupt-parent = <&mpic>;
210 interrupts = <32 2>;
211 };
212 dma-channel@80 {
213 compatible = "fsl,p4080-dma-channel",
214 "fsl,eloplus-dma-channel";
215 reg = <0x80 0x80>;
216 cell-index = <1>;
217 interrupt-parent = <&mpic>;
218 interrupts = <33 2>;
219 };
220 dma-channel@100 {
221 compatible = "fsl,p4080-dma-channel",
222 "fsl,eloplus-dma-channel";
223 reg = <0x100 0x80>;
224 cell-index = <2>;
225 interrupt-parent = <&mpic>;
226 interrupts = <34 2>;
227 };
228 dma-channel@180 {
229 compatible = "fsl,p4080-dma-channel",
230 "fsl,eloplus-dma-channel";
231 reg = <0x180 0x80>;
232 cell-index = <3>;
233 interrupt-parent = <&mpic>;
234 interrupts = <35 2>;
235 };
236 };
237
238 spi@110000 {
239 cell-index = <0>;
240 #address-cells = <1>;
241 #size-cells = <0>;
242 compatible = "fsl,espi";
243 reg = <0x110000 0x1000>;
244 interrupts = <53 0x2>;
245 interrupt-parent = <&mpic>;
246 espi,num-ss-bits = <4>;
247 mode = "cpu";
248
249 fsl_m25p80@0 {
250 #address-cells = <1>;
251 #size-cells = <1>;
252 compatible = "fsl,espi-flash";
253 reg = <0>;
254 linux,modalias = "fsl_m25p80";
255 spi-max-frequency = <40000000>; /* input clock */
256 partition@u-boot {
257 label = "u-boot";
258 reg = <0x00000000 0x00100000>;
259 read-only;
260 };
261 partition@kernel {
262 label = "kernel";
263 reg = <0x00100000 0x00500000>;
264 read-only;
265 };
266 partition@dtb {
267 label = "dtb";
268 reg = <0x00600000 0x00100000>;
269 read-only;
270 };
271 partition@fs {
272 label = "file system";
273 reg = <0x00700000 0x00900000>;
274 };
275 };
276 };
277
278 sdhc: sdhc@114000 {
279 compatible = "fsl,p4080-esdhc", "fsl,esdhc";
280 reg = <0x114000 0x1000>;
281 interrupts = <48 2>;
282 interrupt-parent = <&mpic>;
Roy Zang05e57ee2010-08-10 18:02:00 -0700[diff] [blame^]283 sdhci,auto-cmd12;
Kumar Galaab2f4892009-10-22 16:35:07 -0500[diff] [blame]284 };
285
286 i2c@118000 {
287 #address-cells = <1>;
288 #size-cells = <0>;
289 cell-index = <0>;
290 compatible = "fsl-i2c";
291 reg = <0x118000 0x100>;
292 interrupts = <38 2>;
293 interrupt-parent = <&mpic>;
294 dfsrr;
295 };
296
297 i2c@118100 {
298 #address-cells = <1>;
299 #size-cells = <0>;
300 cell-index = <1>;
301 compatible = "fsl-i2c";
302 reg = <0x118100 0x100>;
303 interrupts = <38 2>;
304 interrupt-parent = <&mpic>;
305 dfsrr;
306 eeprom@51 {
307 compatible = "at24,24c256";
308 reg = <0x51>;
309 };
310 eeprom@52 {
311 compatible = "at24,24c256";
312 reg = <0x52>;
313 };
314 rtc@68 {
315 compatible = "dallas,ds3232";
316 reg = <0x68>;
317 interrupts = <0 0x1>;
318 interrupt-parent = <&mpic>;
319 };
320 };
321
322 i2c@119000 {
323 #address-cells = <1>;
324 #size-cells = <0>;
325 cell-index = <2>;
326 compatible = "fsl-i2c";
327 reg = <0x119000 0x100>;
328 interrupts = <39 2>;
329 interrupt-parent = <&mpic>;
330 dfsrr;
331 };
332
333 i2c@119100 {
334 #address-cells = <1>;
335 #size-cells = <0>;
336 cell-index = <3>;
337 compatible = "fsl-i2c";
338 reg = <0x119100 0x100>;
339 interrupts = <39 2>;
340 interrupt-parent = <&mpic>;
341 dfsrr;
342 };
343
344 serial0: serial@11c500 {
345 cell-index = <0>;
346 device_type = "serial";
347 compatible = "ns16550";
348 reg = <0x11c500 0x100>;
349 clock-frequency = <0>;
350 interrupts = <36 2>;
351 interrupt-parent = <&mpic>;
352 };
353
354 serial1: serial@11c600 {
355 cell-index = <1>;
356 device_type = "serial";
357 compatible = "ns16550";
358 reg = <0x11c600 0x100>;
359 clock-frequency = <0>;
360 interrupts = <36 2>;
361 interrupt-parent = <&mpic>;
362 };
363
364 serial2: serial@11d500 {
365 cell-index = <2>;
366 device_type = "serial";
367 compatible = "ns16550";
368 reg = <0x11d500 0x100>;
369 clock-frequency = <0>;
370 interrupts = <37 2>;
371 interrupt-parent = <&mpic>;
372 };
373
374 serial3: serial@11d600 {
375 cell-index = <3>;
376 device_type = "serial";
377 compatible = "ns16550";
378 reg = <0x11d600 0x100>;
379 clock-frequency = <0>;
380 interrupts = <37 2>;
381 interrupt-parent = <&mpic>;
382 };
383
384 gpio0: gpio@130000 {
385 compatible = "fsl,p4080-gpio";
386 reg = <0x130000 0x1000>;
387 interrupts = <55 2>;
388 interrupt-parent = <&mpic>;
389 #gpio-cells = <2>;
390 gpio-controller;
391 };
392
393 usb0: usb@210000 {
394 compatible = "fsl,p4080-usb2-mph",
395 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
396 reg = <0x210000 0x1000>;
397 #address-cells = <1>;
398 #size-cells = <0>;
399 interrupt-parent = <&mpic>;
400 interrupts = <44 0x2>;
401 phy_type = "ulpi";
402 };
403
404 usb1: usb@211000 {
405 compatible = "fsl,p4080-usb2-dr",
406 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
407 reg = <0x211000 0x1000>;
408 #address-cells = <1>;
409 #size-cells = <0>;
410 interrupt-parent = <&mpic>;
411 interrupts = <45 0x2>;
412 dr_mode = "host";
413 phy_type = "ulpi";
414 };
415 };
416
417 rapidio0: rapidio@ffe0c0000 {
418 #address-cells = <2>;
419 #size-cells = <2>;
420 compatible = "fsl,rapidio-delta";
421 reg = <0xf 0xfe0c0000 0 0x20000>;
422 ranges = <0 0 0xf 0xf5000000 0 0x01000000>;
423 interrupt-parent = <&mpic>;
424 /* err_irq bell_outb_irq bell_inb_irq
425 msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
426 interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>;
427 };
428
429 localbus@ffe124000 {
430 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
431 reg = <0xf 0xfe124000 0 0x1000>;
432 interrupts = <25 2>;
433 #address-cells = <2>;
434 #size-cells = <1>;
435
436 ranges = <0 0 0xf 0xe8000000 0x08000000>;
437
438 flash@0,0 {
439 compatible = "cfi-flash";
440 reg = <0 0 0x08000000>;
441 bank-width = <2>;
442 device-width = <2>;
443 };
444 };
445
446 pci0: pcie@ffe200000 {
447 compatible = "fsl,p4080-pcie";
448 device_type = "pci";
449 #interrupt-cells = <1>;
450 #size-cells = <2>;
451 #address-cells = <3>;
452 reg = <0xf 0xfe200000 0 0x1000>;
453 bus-range = <0x0 0xff>;
454 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
455 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
456 clock-frequency = <0x1fca055>;
457 interrupt-parent = <&mpic>;
458 interrupts = <16 2>;
459
460 interrupt-map-mask = <0xf800 0 0 7>;
461 interrupt-map = <
462 /* IDSEL 0x0 */
463 0000 0 0 1 &mpic 40 1
464 0000 0 0 2 &mpic 1 1
465 0000 0 0 3 &mpic 2 1
466 0000 0 0 4 &mpic 3 1
467 >;
468 pcie@0 {
469 reg = <0 0 0 0 0>;
470 #size-cells = <2>;
471 #address-cells = <3>;
472 device_type = "pci";
473 ranges = <0x02000000 0 0xe0000000
474 0x02000000 0 0xe0000000
475 0 0x20000000
476
477 0x01000000 0 0x00000000
478 0x01000000 0 0x00000000
479 0 0x00010000>;
480 };
481 };
482
483 pci1: pcie@ffe201000 {
484 compatible = "fsl,p4080-pcie";
485 device_type = "pci";
486 #interrupt-cells = <1>;
487 #size-cells = <2>;
488 #address-cells = <3>;
489 reg = <0xf 0xfe201000 0 0x1000>;
490 bus-range = <0 0xff>;
491 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
492 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
493 clock-frequency = <0x1fca055>;
494 interrupt-parent = <&mpic>;
495 interrupts = <16 2>;
496 interrupt-map-mask = <0xf800 0 0 7>;
497 interrupt-map = <
498 /* IDSEL 0x0 */
499 0000 0 0 1 &mpic 41 1
500 0000 0 0 2 &mpic 5 1
501 0000 0 0 3 &mpic 6 1
502 0000 0 0 4 &mpic 7 1
503 >;
504 pcie@0 {
505 reg = <0 0 0 0 0>;
506 #size-cells = <2>;
507 #address-cells = <3>;
508 device_type = "pci";
509 ranges = <0x02000000 0 0xe0000000
510 0x02000000 0 0xe0000000
511 0 0x20000000
512
513 0x01000000 0 0x00000000
514 0x01000000 0 0x00000000
515 0 0x00010000>;
516 };
517 };
518
519 pci2: pcie@ffe202000 {
520 compatible = "fsl,p4080-pcie";
521 device_type = "pci";
522 #interrupt-cells = <1>;
523 #size-cells = <2>;
524 #address-cells = <3>;
525 reg = <0xf 0xfe202000 0 0x1000>;
526 bus-range = <0x0 0xff>;
527 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
528 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
529 clock-frequency = <0x1fca055>;
530 interrupt-parent = <&mpic>;
531 interrupts = <16 2>;
532 interrupt-map-mask = <0xf800 0 0 7>;
533 interrupt-map = <
534 /* IDSEL 0x0 */
535 0000 0 0 1 &mpic 42 1
536 0000 0 0 2 &mpic 9 1
537 0000 0 0 3 &mpic 10 1
538 0000 0 0 4 &mpic 11 1
539 >;
540 pcie@0 {
541 reg = <0 0 0 0 0>;
542 #size-cells = <2>;
543 #address-cells = <3>;
544 device_type = "pci";
545 ranges = <0x02000000 0 0xe0000000
546 0x02000000 0 0xe0000000
547 0 0x20000000
548
549 0x01000000 0 0x00000000
550 0x01000000 0 0x00000000
551 0 0x00010000>;
552 };
553 };
554
555};