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Hans Verkuil1c1e45d2008-04-28 20:24:33 -03001/*
2 * cx18 mailbox functions
3 *
4 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
Andy Walls6afdeaf2010-05-23 18:53:35 -03005 * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net>
Hans Verkuil1c1e45d2008-04-28 20:24:33 -03006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20 * 02111-1307 USA
21 */
22
23#include <stdarg.h>
24
25#include "cx18-driver.h"
Andy Wallsb1526422008-08-30 16:03:44 -030026#include "cx18-io.h"
Hans Verkuil1c1e45d2008-04-28 20:24:33 -030027#include "cx18-scb.h"
28#include "cx18-irq.h"
29#include "cx18-mailbox.h"
Andy Wallsee2d64f2008-11-16 01:38:19 -030030#include "cx18-queue.h"
31#include "cx18-streams.h"
Devin Heitmueller9972de92010-01-18 21:29:51 -030032#include "cx18-alsa-pcm.h" /* FIXME make configurable */
Andy Wallsee2d64f2008-11-16 01:38:19 -030033
34static const char *rpu_str[] = { "APU", "CPU", "EPU", "HPU" };
Hans Verkuil1c1e45d2008-04-28 20:24:33 -030035
36#define API_FAST (1 << 2) /* Short timeout */
37#define API_SLOW (1 << 3) /* Additional 300ms timeout */
38
Hans Verkuil1c1e45d2008-04-28 20:24:33 -030039struct cx18_api_info {
40 u32 cmd;
41 u8 flags; /* Flags, see above */
42 u8 rpu; /* Processing unit */
43 const char *name; /* The name of the command */
44};
45
46#define API_ENTRY(rpu, x, f) { (x), (f), (rpu), #x }
47
48static const struct cx18_api_info api_info[] = {
49 /* MPEG encoder API */
50 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
51 API_ENTRY(CPU, CX18_EPU_DEBUG, 0),
52 API_ENTRY(CPU, CX18_CREATE_TASK, 0),
53 API_ENTRY(CPU, CX18_DESTROY_TASK, 0),
54 API_ENTRY(CPU, CX18_CPU_CAPTURE_START, API_SLOW),
55 API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP, API_SLOW),
56 API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE, 0),
57 API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME, 0),
58 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
59 API_ENTRY(CPU, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 0),
60 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_IN, 0),
61 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RATE, 0),
62 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_RESOLUTION, 0),
63 API_ENTRY(CPU, CX18_CPU_SET_FILTER_PARAM, 0),
64 API_ENTRY(CPU, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 0),
65 API_ENTRY(CPU, CX18_CPU_SET_MEDIAN_CORING, 0),
66 API_ENTRY(CPU, CX18_CPU_SET_INDEXTABLE, 0),
67 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PARAMETERS, 0),
68 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_MUTE, 0),
69 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_MUTE, 0),
70 API_ENTRY(CPU, CX18_CPU_SET_MISC_PARAMETERS, 0),
71 API_ENTRY(CPU, CX18_CPU_SET_RAW_VBI_PARAM, API_SLOW),
72 API_ENTRY(CPU, CX18_CPU_SET_CAPTURE_LINE_NO, 0),
73 API_ENTRY(CPU, CX18_CPU_SET_COPYRIGHT, 0),
74 API_ENTRY(CPU, CX18_CPU_SET_AUDIO_PID, 0),
75 API_ENTRY(CPU, CX18_CPU_SET_VIDEO_PID, 0),
76 API_ENTRY(CPU, CX18_CPU_SET_VER_CROP_LINE, 0),
77 API_ENTRY(CPU, CX18_CPU_SET_GOP_STRUCTURE, 0),
78 API_ENTRY(CPU, CX18_CPU_SET_SCENE_CHANGE_DETECTION, 0),
79 API_ENTRY(CPU, CX18_CPU_SET_ASPECT_RATIO, 0),
80 API_ENTRY(CPU, CX18_CPU_SET_SKIP_INPUT_FRAME, 0),
81 API_ENTRY(CPU, CX18_CPU_SET_SLICED_VBI_PARAM, 0),
82 API_ENTRY(CPU, CX18_CPU_SET_USERDATA_PLACE_HOLDER, 0),
83 API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS, 0),
Steven Tothb7101de2011-04-06 08:32:56 -030084 API_ENTRY(CPU, CX18_CPU_SET_VFC_PARAM, 0),
Hans Verkuil1c1e45d2008-04-28 20:24:33 -030085 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0),
86 API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST),
Andy Walls4e6b6102008-11-01 01:07:36 -030087 API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, API_SLOW),
Andy Walls350145a2009-01-04 21:51:17 -030088 API_ENTRY(APU, CX18_APU_START, 0),
89 API_ENTRY(APU, CX18_APU_STOP, 0),
Andy Wallsfd6b9c92008-12-14 21:26:25 -030090 API_ENTRY(APU, CX18_APU_RESETAI, 0),
91 API_ENTRY(CPU, CX18_CPU_DEBUG_PEEK32, 0),
Hans Verkuil1c1e45d2008-04-28 20:24:33 -030092 API_ENTRY(0, 0, 0),
93};
94
95static const struct cx18_api_info *find_api_info(u32 cmd)
96{
97 int i;
98
99 for (i = 0; api_info[i].cmd; i++)
100 if (api_info[i].cmd == cmd)
101 return &api_info[i];
102 return NULL;
103}
104
Andy Walls50299992009-01-01 12:35:06 -0300105/* Call with buf of n*11+1 bytes */
106static char *u32arr2hex(u32 data[], int n, char *buf)
107{
108 char *p;
109 int i;
110
111 for (i = 0, p = buf; i < n; i++, p += 11) {
112 /* kernel snprintf() appends '\0' always */
113 snprintf(p, 12, " %#010x", data[i]);
114 }
115 *p = '\0';
116 return buf;
117}
118
Andy Wallsee2d64f2008-11-16 01:38:19 -0300119static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name)
120{
121 char argstr[MAX_MB_ARGUMENTS*11+1];
Andy Wallsee2d64f2008-11-16 01:38:19 -0300122
123 if (!(cx18_debug & CX18_DBGFLG_API))
124 return;
125
Andy Wallsee2d64f2008-11-16 01:38:19 -0300126 CX18_DEBUG_API("%s: req %#010x ack %#010x cmd %#010x err %#010x args%s"
Andy Walls50299992009-01-01 12:35:06 -0300127 "\n", name, mb->request, mb->ack, mb->cmd, mb->error,
128 u32arr2hex(mb->args, MAX_MB_ARGUMENTS, argstr));
Andy Wallsee2d64f2008-11-16 01:38:19 -0300129}
130
131
132/*
133 * Functions that run in a work_queue work handling context
134 */
135
Andy Walls52fcb3e2009-11-08 23:45:24 -0300136static void cx18_mdl_send_to_dvb(struct cx18_stream *s, struct cx18_mdl *mdl)
137{
138 struct cx18_buffer *buf;
139
Andy Walls754f9962010-12-11 20:38:20 -0300140 if (s->dvb == NULL || !s->dvb->enabled || mdl->bytesused == 0)
Andy Walls52fcb3e2009-11-08 23:45:24 -0300141 return;
142
143 /* We ignore mdl and buf readpos accounting here - it doesn't matter */
144
145 /* The likely case */
146 if (list_is_singular(&mdl->buf_list)) {
147 buf = list_first_entry(&mdl->buf_list, struct cx18_buffer,
148 list);
149 if (buf->bytesused)
Andy Walls754f9962010-12-11 20:38:20 -0300150 dvb_dmx_swfilter(&s->dvb->demux,
Andy Walls52fcb3e2009-11-08 23:45:24 -0300151 buf->buf, buf->bytesused);
152 return;
153 }
154
155 list_for_each_entry(buf, &mdl->buf_list, list) {
156 if (buf->bytesused == 0)
157 break;
Andy Walls754f9962010-12-11 20:38:20 -0300158 dvb_dmx_swfilter(&s->dvb->demux, buf->buf, buf->bytesused);
Andy Walls52fcb3e2009-11-08 23:45:24 -0300159 }
160}
161
Steven Tothb7101de2011-04-06 08:32:56 -0300162static void cx18_mdl_send_to_videobuf(struct cx18_stream *s,
163 struct cx18_mdl *mdl)
164{
165 struct cx18_videobuf_buffer *vb_buf;
166 struct cx18_buffer *buf;
Simon Farnsworthbea3c542011-05-05 09:42:36 -0300167 u8 *p;
Steven Tothb7101de2011-04-06 08:32:56 -0300168 u32 offset = 0;
169 int dispatch = 0;
Steven Tothb7101de2011-04-06 08:32:56 -0300170
171 if (mdl->bytesused == 0)
172 return;
173
174 /* Acquire a videobuf buffer, clone to and and release it */
175 spin_lock(&s->vb_lock);
176 if (list_empty(&s->vb_capture))
177 goto out;
178
Simon Farnsworth1bf58422011-05-03 08:57:40 -0300179 vb_buf = list_first_entry(&s->vb_capture, struct cx18_videobuf_buffer,
Steven Tothb7101de2011-04-06 08:32:56 -0300180 vb.queue);
181
182 p = videobuf_to_vmalloc(&vb_buf->vb);
183 if (!p)
184 goto out;
185
186 offset = vb_buf->bytes_used;
187 list_for_each_entry(buf, &mdl->buf_list, list) {
188 if (buf->bytesused == 0)
189 break;
190
191 if ((offset + buf->bytesused) <= vb_buf->vb.bsize) {
192 memcpy(p + offset, buf->buf, buf->bytesused);
193 offset += buf->bytesused;
194 vb_buf->bytes_used += buf->bytesused;
195 }
196 }
197
198 /* If we've filled the buffer as per the callers res then dispatch it */
Simon Farnsworth09fc9802011-09-05 12:23:12 -0300199 if (vb_buf->bytes_used >= s->vb_bytes_per_frame) {
Steven Tothb7101de2011-04-06 08:32:56 -0300200 dispatch = 1;
201 vb_buf->bytes_used = 0;
202 }
203
Steven Tothb7101de2011-04-06 08:32:56 -0300204 if (dispatch) {
Simon Farnsworthbea3c542011-05-05 09:42:36 -0300205 vb_buf->vb.ts = ktime_to_timeval(ktime_get());
Steven Tothb7101de2011-04-06 08:32:56 -0300206 list_del(&vb_buf->vb.queue);
207 vb_buf->vb.state = VIDEOBUF_DONE;
208 wake_up(&vb_buf->vb.done);
209 }
210
Simon Farnsworth1bf58422011-05-03 08:57:40 -0300211 mod_timer(&s->vb_timeout, msecs_to_jiffies(2000) + jiffies);
Steven Tothb7101de2011-04-06 08:32:56 -0300212
213out:
214 spin_unlock(&s->vb_lock);
215}
Devin Heitmueller9972de92010-01-18 21:29:51 -0300216
217static void cx18_mdl_send_to_alsa(struct cx18 *cx, struct cx18_stream *s,
218 struct cx18_mdl *mdl)
219{
220 struct cx18_buffer *buf;
221
222 if (mdl->bytesused == 0)
223 return;
224
225 /* We ignore mdl and buf readpos accounting here - it doesn't matter */
226
227 /* The likely case */
228 if (list_is_singular(&mdl->buf_list)) {
229 buf = list_first_entry(&mdl->buf_list, struct cx18_buffer,
230 list);
231 if (buf->bytesused)
232 cx->pcm_announce_callback(cx->alsa, buf->buf,
233 buf->bytesused);
234 return;
235 }
236
237 list_for_each_entry(buf, &mdl->buf_list, list) {
238 if (buf->bytesused == 0)
239 break;
240 cx->pcm_announce_callback(cx->alsa, buf->buf, buf->bytesused);
241 }
242}
243
Andy Wallsdeed75e2009-04-13 22:22:40 -0300244static void epu_dma_done(struct cx18 *cx, struct cx18_in_work_order *order)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300245{
Andy Wallsbca11a52008-11-19 01:24:33 -0300246 u32 handle, mdl_ack_count, id;
Andy Wallsee2d64f2008-11-16 01:38:19 -0300247 struct cx18_mailbox *mb;
248 struct cx18_mdl_ack *mdl_ack;
249 struct cx18_stream *s;
Andy Walls52fcb3e2009-11-08 23:45:24 -0300250 struct cx18_mdl *mdl;
Andy Wallsee2d64f2008-11-16 01:38:19 -0300251 int i;
252
253 mb = &order->mb;
254 handle = mb->args[0];
255 s = cx18_handle_to_stream(cx, handle);
256
257 if (s == NULL) {
258 CX18_WARN("Got DMA done notification for unknown/inactive"
Andy Wallsbca11a52008-11-19 01:24:33 -0300259 " handle %d, %s mailbox seq no %d\n", handle,
260 (order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) ?
261 "stale" : "good", mb->request);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300262 return;
263 }
264
265 mdl_ack_count = mb->args[2];
266 mdl_ack = order->mdl_ack;
267 for (i = 0; i < mdl_ack_count; i++, mdl_ack++) {
Andy Wallsbca11a52008-11-19 01:24:33 -0300268 id = mdl_ack->id;
269 /*
270 * Simple integrity check for processing a stale (and possibly
Andy Walls52fcb3e2009-11-08 23:45:24 -0300271 * inconsistent mailbox): make sure the MDL id is in the
Andy Wallsbca11a52008-11-19 01:24:33 -0300272 * valid range for the stream.
273 *
274 * We go through the trouble of dealing with stale mailboxes
275 * because most of the time, the mailbox data is still valid and
276 * unchanged (and in practice the firmware ping-pongs the
277 * two mdl_ack buffers so mdl_acks are not stale).
278 *
279 * There are occasions when we get a half changed mailbox,
280 * which this check catches for a handle & id mismatch. If the
281 * handle and id do correspond, the worst case is that we
Andy Walls52fcb3e2009-11-08 23:45:24 -0300282 * completely lost the old MDL, but pick up the new MDL
Andy Wallsbca11a52008-11-19 01:24:33 -0300283 * early (but the new mdl_ack is guaranteed to be good in this
284 * case as the firmware wouldn't point us to a new mdl_ack until
285 * it's filled in).
286 *
Andy Walls52fcb3e2009-11-08 23:45:24 -0300287 * cx18_queue_get_mdl() will detect the lost MDLs
Andy Wallsabb096d2008-12-12 15:50:27 -0300288 * and send them back to q_free for fw rotation eventually.
Andy Wallsbca11a52008-11-19 01:24:33 -0300289 */
290 if ((order->flags & CX18_F_EWO_MB_STALE_UPON_RECEIPT) &&
Andy Wallsfa655dd2009-11-05 21:51:24 -0300291 !(id >= s->mdl_base_idx &&
292 id < (s->mdl_base_idx + s->buffers))) {
Andy Wallsbca11a52008-11-19 01:24:33 -0300293 CX18_WARN("Fell behind! Ignoring stale mailbox with "
Andy Walls52fcb3e2009-11-08 23:45:24 -0300294 " inconsistent data. Lost MDL for mailbox "
Andy Wallsbca11a52008-11-19 01:24:33 -0300295 "seq no %d\n", mb->request);
296 break;
297 }
Andy Walls52fcb3e2009-11-08 23:45:24 -0300298 mdl = cx18_queue_get_mdl(s, id, mdl_ack->data_used);
Andy Wallsabb096d2008-12-12 15:50:27 -0300299
Andy Walls52fcb3e2009-11-08 23:45:24 -0300300 CX18_DEBUG_HI_DMA("DMA DONE for %s (MDL %d)\n", s->name, id);
301 if (mdl == NULL) {
302 CX18_WARN("Could not find MDL %d for stream %s\n",
Andy Wallsbca11a52008-11-19 01:24:33 -0300303 id, s->name);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300304 continue;
305 }
306
Andy Walls40c55202009-04-13 23:08:00 -0300307 CX18_DEBUG_HI_DMA("%s recv bytesused = %d\n",
Andy Walls52fcb3e2009-11-08 23:45:24 -0300308 s->name, mdl->bytesused);
Andy Walls40c55202009-04-13 23:08:00 -0300309
Devin Heitmueller9972de92010-01-18 21:29:51 -0300310 if (s->type == CX18_ENC_STREAM_TYPE_TS) {
311 cx18_mdl_send_to_dvb(s, mdl);
312 cx18_enqueue(s, mdl, &s->q_free);
313 } else if (s->type == CX18_ENC_STREAM_TYPE_PCM) {
314 /* Pass the data to cx18-alsa */
315 if (cx->pcm_announce_callback != NULL) {
316 cx18_mdl_send_to_alsa(cx, s, mdl);
317 cx18_enqueue(s, mdl, &s->q_free);
318 } else {
319 cx18_enqueue(s, mdl, &s->q_full);
320 }
Steven Tothb7101de2011-04-06 08:32:56 -0300321 } else if (s->type == CX18_ENC_STREAM_TYPE_YUV) {
322 cx18_mdl_send_to_videobuf(s, mdl);
323 cx18_enqueue(s, mdl, &s->q_free);
Devin Heitmueller9972de92010-01-18 21:29:51 -0300324 } else {
Andy Walls52fcb3e2009-11-08 23:45:24 -0300325 cx18_enqueue(s, mdl, &s->q_full);
Andy Wallsef991792009-12-31 18:27:13 -0300326 if (s->type == CX18_ENC_STREAM_TYPE_IDX)
327 cx18_stream_rotate_idx_mdls(cx);
328 }
Andy Wallsee2d64f2008-11-16 01:38:19 -0300329 }
Andy Walls52fcb3e2009-11-08 23:45:24 -0300330 /* Put as many MDLs as possible back into fw use */
Andy Walls40c55202009-04-13 23:08:00 -0300331 cx18_stream_load_fw_queue(s);
332
Andy Wallsee2d64f2008-11-16 01:38:19 -0300333 wake_up(&cx->dma_waitq);
334 if (s->id != -1)
335 wake_up(&s->waitq);
336}
337
Andy Wallsdeed75e2009-04-13 22:22:40 -0300338static void epu_debug(struct cx18 *cx, struct cx18_in_work_order *order)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300339{
340 char *p;
341 char *str = order->str;
342
343 CX18_DEBUG_INFO("%x %s\n", order->mb.args[0], str);
344 p = strchr(str, '.');
345 if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str)
346 CX18_INFO("FW version: %s\n", p - 1);
347}
348
Andy Wallsdeed75e2009-04-13 22:22:40 -0300349static void epu_cmd(struct cx18 *cx, struct cx18_in_work_order *order)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300350{
351 switch (order->rpu) {
352 case CPU:
353 {
354 switch (order->mb.cmd) {
355 case CX18_EPU_DMA_DONE:
356 epu_dma_done(cx, order);
357 break;
358 case CX18_EPU_DEBUG:
359 epu_debug(cx, order);
360 break;
361 default:
362 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
363 order->mb.cmd);
364 break;
365 }
366 break;
367 }
368 case APU:
369 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
370 order->mb.cmd);
371 break;
372 default:
373 break;
374 }
375}
376
377static
Andy Wallsdeed75e2009-04-13 22:22:40 -0300378void free_in_work_order(struct cx18 *cx, struct cx18_in_work_order *order)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300379{
380 atomic_set(&order->pending, 0);
381}
382
Andy Wallsdeed75e2009-04-13 22:22:40 -0300383void cx18_in_work_handler(struct work_struct *work)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300384{
Andy Wallsdeed75e2009-04-13 22:22:40 -0300385 struct cx18_in_work_order *order =
386 container_of(work, struct cx18_in_work_order, work);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300387 struct cx18 *cx = order->cx;
388 epu_cmd(cx, order);
Andy Wallsdeed75e2009-04-13 22:22:40 -0300389 free_in_work_order(cx, order);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300390}
391
392
393/*
394 * Functions that run in an interrupt handling context
395 */
396
Andy Wallsdeed75e2009-04-13 22:22:40 -0300397static void mb_ack_irq(struct cx18 *cx, struct cx18_in_work_order *order)
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300398{
Al Viro990c81c2008-05-21 00:32:01 -0300399 struct cx18_mailbox __iomem *ack_mb;
Andy Wallsee2d64f2008-11-16 01:38:19 -0300400 u32 ack_irq, req;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300401
Andy Wallsee2d64f2008-11-16 01:38:19 -0300402 switch (order->rpu) {
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300403 case APU:
404 ack_irq = IRQ_EPU_TO_APU_ACK;
405 ack_mb = &cx->scb->apu2epu_mb;
406 break;
407 case CPU:
408 ack_irq = IRQ_EPU_TO_CPU_ACK;
409 ack_mb = &cx->scb->cpu2epu_mb;
410 break;
411 default:
Andy Walls72c2d6d2008-11-06 01:15:41 -0300412 CX18_WARN("Unhandled RPU (%d) for command %x ack\n",
Andy Wallsee2d64f2008-11-16 01:38:19 -0300413 order->rpu, order->mb.cmd);
414 return;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300415 }
416
Andy Wallsee2d64f2008-11-16 01:38:19 -0300417 req = order->mb.request;
418 /* Don't ack if the RPU has gotten impatient and timed us out */
419 if (req != cx18_readl(cx, &ack_mb->request) ||
Andy Walls72a4f802008-11-16 21:18:00 -0300420 req == cx18_readl(cx, &ack_mb->ack)) {
Andy Wallsbca11a52008-11-19 01:24:33 -0300421 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
422 "incoming %s to EPU mailbox (sequence no. %u) "
423 "while processing\n",
424 rpu_str[order->rpu], rpu_str[order->rpu], req);
Andy Walls72a4f802008-11-16 21:18:00 -0300425 order->flags |= CX18_F_EWO_MB_STALE_WHILE_PROC;
Andy Wallsee2d64f2008-11-16 01:38:19 -0300426 return;
Andy Walls72a4f802008-11-16 21:18:00 -0300427 }
Andy Wallsee2d64f2008-11-16 01:38:19 -0300428 cx18_writel(cx, req, &ack_mb->ack);
Andy Wallsf056d292008-10-31 20:49:12 -0300429 cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300430 return;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300431}
432
Andy Wallsdeed75e2009-04-13 22:22:40 -0300433static int epu_dma_done_irq(struct cx18 *cx, struct cx18_in_work_order *order)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300434{
435 u32 handle, mdl_ack_offset, mdl_ack_count;
436 struct cx18_mailbox *mb;
437
438 mb = &order->mb;
439 handle = mb->args[0];
440 mdl_ack_offset = mb->args[1];
441 mdl_ack_count = mb->args[2];
442
443 if (handle == CX18_INVALID_TASK_HANDLE ||
444 mdl_ack_count == 0 || mdl_ack_count > CX18_MAX_MDL_ACKS) {
Andy Walls72a4f802008-11-16 21:18:00 -0300445 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300446 mb_ack_irq(cx, order);
447 return -1;
448 }
449
450 cx18_memcpy_fromio(cx, order->mdl_ack, cx->enc_mem + mdl_ack_offset,
451 sizeof(struct cx18_mdl_ack) * mdl_ack_count);
Andy Walls72a4f802008-11-16 21:18:00 -0300452
453 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300454 mb_ack_irq(cx, order);
455 return 1;
456}
457
458static
Andy Wallsdeed75e2009-04-13 22:22:40 -0300459int epu_debug_irq(struct cx18 *cx, struct cx18_in_work_order *order)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300460{
461 u32 str_offset;
462 char *str = order->str;
463
464 str[0] = '\0';
465 str_offset = order->mb.args[1];
466 if (str_offset) {
467 cx18_setup_page(cx, str_offset);
468 cx18_memcpy_fromio(cx, str, cx->enc_mem + str_offset, 252);
469 str[252] = '\0';
470 cx18_setup_page(cx, SCB_OFFSET);
471 }
472
Andy Walls72a4f802008-11-16 21:18:00 -0300473 if ((order->flags & CX18_F_EWO_MB_STALE) == 0)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300474 mb_ack_irq(cx, order);
475
476 return str_offset ? 1 : 0;
477}
478
479static inline
Andy Wallsdeed75e2009-04-13 22:22:40 -0300480int epu_cmd_irq(struct cx18 *cx, struct cx18_in_work_order *order)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300481{
482 int ret = -1;
483
484 switch (order->rpu) {
485 case CPU:
486 {
487 switch (order->mb.cmd) {
488 case CX18_EPU_DMA_DONE:
Andy Walls72a4f802008-11-16 21:18:00 -0300489 ret = epu_dma_done_irq(cx, order);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300490 break;
491 case CX18_EPU_DEBUG:
Andy Walls72a4f802008-11-16 21:18:00 -0300492 ret = epu_debug_irq(cx, order);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300493 break;
494 default:
495 CX18_WARN("Unknown CPU to EPU mailbox command %#0x\n",
496 order->mb.cmd);
497 break;
498 }
499 break;
500 }
501 case APU:
502 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n",
503 order->mb.cmd);
504 break;
505 default:
506 break;
507 }
508 return ret;
509}
510
511static inline
Andy Wallsdeed75e2009-04-13 22:22:40 -0300512struct cx18_in_work_order *alloc_in_work_order_irq(struct cx18 *cx)
Andy Wallsee2d64f2008-11-16 01:38:19 -0300513{
514 int i;
Andy Wallsdeed75e2009-04-13 22:22:40 -0300515 struct cx18_in_work_order *order = NULL;
Andy Wallsee2d64f2008-11-16 01:38:19 -0300516
Andy Wallsdeed75e2009-04-13 22:22:40 -0300517 for (i = 0; i < CX18_MAX_IN_WORK_ORDERS; i++) {
Andy Wallsee2d64f2008-11-16 01:38:19 -0300518 /*
519 * We only need "pending" atomic to inspect its contents,
520 * and need not do a check and set because:
521 * 1. Any work handler thread only clears "pending" and only
522 * on one, particular work order at a time, per handler thread.
523 * 2. "pending" is only set here, and we're serialized because
524 * we're called in an IRQ handler context.
525 */
Andy Wallsdeed75e2009-04-13 22:22:40 -0300526 if (atomic_read(&cx->in_work_order[i].pending) == 0) {
527 order = &cx->in_work_order[i];
Andy Wallsee2d64f2008-11-16 01:38:19 -0300528 atomic_set(&order->pending, 1);
529 break;
530 }
531 }
532 return order;
533}
534
535void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
536{
537 struct cx18_mailbox __iomem *mb;
538 struct cx18_mailbox *order_mb;
Andy Wallsdeed75e2009-04-13 22:22:40 -0300539 struct cx18_in_work_order *order;
Andy Wallsee2d64f2008-11-16 01:38:19 -0300540 int submit;
541
542 switch (rpu) {
543 case CPU:
544 mb = &cx->scb->cpu2epu_mb;
545 break;
546 case APU:
547 mb = &cx->scb->apu2epu_mb;
548 break;
549 default:
550 return;
551 }
552
Andy Wallsdeed75e2009-04-13 22:22:40 -0300553 order = alloc_in_work_order_irq(cx);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300554 if (order == NULL) {
555 CX18_WARN("Unable to find blank work order form to schedule "
556 "incoming mailbox command processing\n");
557 return;
558 }
559
Andy Walls72a4f802008-11-16 21:18:00 -0300560 order->flags = 0;
Andy Wallsee2d64f2008-11-16 01:38:19 -0300561 order->rpu = rpu;
562 order_mb = &order->mb;
Andy Wallsd6c7e5f2008-11-17 22:48:46 -0300563
564 /* mb->cmd and mb->args[0] through mb->args[2] */
565 cx18_memcpy_fromio(cx, &order_mb->cmd, &mb->cmd, 4 * sizeof(u32));
566 /* mb->request and mb->ack. N.B. we want to read mb->ack last */
567 cx18_memcpy_fromio(cx, &order_mb->request, &mb->request,
568 2 * sizeof(u32));
Andy Wallsee2d64f2008-11-16 01:38:19 -0300569
570 if (order_mb->request == order_mb->ack) {
Andy Wallsbca11a52008-11-19 01:24:33 -0300571 CX18_DEBUG_WARN("Possibly falling behind: %s self-ack'ed our "
572 "incoming %s to EPU mailbox (sequence no. %u)"
573 "\n",
574 rpu_str[rpu], rpu_str[rpu], order_mb->request);
Andy Walls50299992009-01-01 12:35:06 -0300575 if (cx18_debug & CX18_DBGFLG_WARN)
576 dump_mb(cx, order_mb, "incoming");
Andy Walls72a4f802008-11-16 21:18:00 -0300577 order->flags = CX18_F_EWO_MB_STALE_UPON_RECEIPT;
Andy Wallsee2d64f2008-11-16 01:38:19 -0300578 }
579
580 /*
581 * Individual EPU command processing is responsible for ack-ing
582 * a non-stale mailbox as soon as possible
583 */
Andy Walls72a4f802008-11-16 21:18:00 -0300584 submit = epu_cmd_irq(cx, order);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300585 if (submit > 0) {
Andy Wallsdeed75e2009-04-13 22:22:40 -0300586 queue_work(cx->in_work_queue, &order->work);
Andy Wallsee2d64f2008-11-16 01:38:19 -0300587 }
588}
589
590
591/*
592 * Functions called from a non-interrupt, non work_queue context
593 */
594
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300595static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
596{
597 const struct cx18_api_info *info = find_api_info(cmd);
Andy Wallsac504412008-11-07 23:57:46 -0300598 u32 state, irq, req, ack, err;
Al Viro990c81c2008-05-21 00:32:01 -0300599 struct cx18_mailbox __iomem *mb;
Andy Wallsac504412008-11-07 23:57:46 -0300600 u32 __iomem *xpu_state;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300601 wait_queue_head_t *waitq;
Andy Walls72c2d6d2008-11-06 01:15:41 -0300602 struct mutex *mb_lock;
Andy Walls5f0a3cf2009-04-13 22:53:09 -0300603 unsigned long int t0, timeout, ret;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300604 int i;
Andy Walls50299992009-01-01 12:35:06 -0300605 char argstr[MAX_MB_ARGUMENTS*11+1];
Andy Walls5f0a3cf2009-04-13 22:53:09 -0300606 DEFINE_WAIT(w);
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300607
608 if (info == NULL) {
609 CX18_WARN("unknown cmd %x\n", cmd);
610 return -EINVAL;
611 }
612
Andy Walls50299992009-01-01 12:35:06 -0300613 if (cx18_debug & CX18_DBGFLG_API) { /* only call u32arr2hex if needed */
614 if (cmd == CX18_CPU_DE_SET_MDL) {
615 if (cx18_debug & CX18_DBGFLG_HIGHVOL)
616 CX18_DEBUG_HI_API("%s\tcmd %#010x args%s\n",
617 info->name, cmd,
618 u32arr2hex(data, args, argstr));
619 } else
620 CX18_DEBUG_API("%s\tcmd %#010x args%s\n",
621 info->name, cmd,
622 u32arr2hex(data, args, argstr));
623 }
Andy Walls72c2d6d2008-11-06 01:15:41 -0300624
625 switch (info->rpu) {
626 case APU:
627 waitq = &cx->mb_apu_waitq;
628 mb_lock = &cx->epu2apu_mb_lock;
Andy Wallsac504412008-11-07 23:57:46 -0300629 irq = IRQ_EPU_TO_APU;
630 mb = &cx->scb->epu2apu_mb;
631 xpu_state = &cx->scb->apu_state;
Andy Walls72c2d6d2008-11-06 01:15:41 -0300632 break;
633 case CPU:
634 waitq = &cx->mb_cpu_waitq;
635 mb_lock = &cx->epu2cpu_mb_lock;
Andy Wallsac504412008-11-07 23:57:46 -0300636 irq = IRQ_EPU_TO_CPU;
637 mb = &cx->scb->epu2cpu_mb;
638 xpu_state = &cx->scb->cpu_state;
Andy Walls72c2d6d2008-11-06 01:15:41 -0300639 break;
640 default:
641 CX18_WARN("Unknown RPU (%d) for API call\n", info->rpu);
642 return -EINVAL;
643 }
644
645 mutex_lock(mb_lock);
Andy Wallsac504412008-11-07 23:57:46 -0300646 /*
647 * Wait for an in-use mailbox to complete
648 *
649 * If the XPU is responding with Ack's, the mailbox shouldn't be in
650 * a busy state, since we serialize access to it on our end.
651 *
652 * If the wait for ack after sending a previous command was interrupted
653 * by a signal, we may get here and find a busy mailbox. After waiting,
654 * mark it "not busy" from our end, if the XPU hasn't ack'ed it still.
655 */
656 state = cx18_readl(cx, xpu_state);
657 req = cx18_readl(cx, &mb->request);
Andy Walls2bb49f12008-11-22 01:23:22 -0300658 timeout = msecs_to_jiffies(10);
Andy Wallsac504412008-11-07 23:57:46 -0300659 ret = wait_event_timeout(*waitq,
660 (ack = cx18_readl(cx, &mb->ack)) == req,
Andy Walls330c6ec2008-11-08 14:19:37 -0300661 timeout);
Andy Wallsac504412008-11-07 23:57:46 -0300662 if (req != ack) {
663 /* waited long enough, make the mbox "not busy" from our end */
664 cx18_writel(cx, req, &mb->ack);
665 CX18_ERR("mbox was found stuck busy when setting up for %s; "
666 "clearing busy and trying to proceed\n", info->name);
Andy Walls330c6ec2008-11-08 14:19:37 -0300667 } else if (ret != timeout)
Andy Walls2bb49f12008-11-22 01:23:22 -0300668 CX18_DEBUG_API("waited %u msecs for busy mbox to be acked\n",
669 jiffies_to_msecs(timeout-ret));
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300670
Andy Wallsac504412008-11-07 23:57:46 -0300671 /* Build the outgoing mailbox */
672 req = ((req & 0xfffffffe) == 0xfffffffe) ? 1 : req + 1;
673
Andy Wallsb1526422008-08-30 16:03:44 -0300674 cx18_writel(cx, cmd, &mb->cmd);
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300675 for (i = 0; i < args; i++)
Andy Wallsb1526422008-08-30 16:03:44 -0300676 cx18_writel(cx, data[i], &mb->args[i]);
677 cx18_writel(cx, 0, &mb->error);
678 cx18_writel(cx, req, &mb->request);
Andy Wallsac504412008-11-07 23:57:46 -0300679 cx18_writel(cx, req - 1, &mb->ack); /* ensure ack & req are distinct */
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300680
Andy Walls330c6ec2008-11-08 14:19:37 -0300681 /*
682 * Notify the XPU and wait for it to send an Ack back
Andy Walls330c6ec2008-11-08 14:19:37 -0300683 */
Andy Walls2bb49f12008-11-22 01:23:22 -0300684 timeout = msecs_to_jiffies((info->flags & API_FAST) ? 10 : 20);
Andy Wallsac504412008-11-07 23:57:46 -0300685
686 CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n",
687 irq, info->name);
Andy Walls5f0a3cf2009-04-13 22:53:09 -0300688
689 /* So we don't miss the wakeup, prepare to wait before notifying fw */
690 prepare_to_wait(waitq, &w, TASK_UNINTERRUPTIBLE);
Andy Wallsf056d292008-10-31 20:49:12 -0300691 cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq);
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300692
Andy Walls5f0a3cf2009-04-13 22:53:09 -0300693 t0 = jiffies;
694 ack = cx18_readl(cx, &mb->ack);
695 if (ack != req) {
696 schedule_timeout(timeout);
697 ret = jiffies - t0;
698 ack = cx18_readl(cx, &mb->ack);
699 } else {
700 ret = jiffies - t0;
701 }
Andy Walls2bb49f12008-11-22 01:23:22 -0300702
Andy Walls5f0a3cf2009-04-13 22:53:09 -0300703 finish_wait(waitq, &w);
704
705 if (req != ack) {
Andy Walls72c2d6d2008-11-06 01:15:41 -0300706 mutex_unlock(mb_lock);
Andy Walls5f0a3cf2009-04-13 22:53:09 -0300707 if (ret >= timeout) {
708 /* Timed out */
709 CX18_DEBUG_WARN("sending %s timed out waiting %d msecs "
710 "for RPU acknowledgement\n",
711 info->name, jiffies_to_msecs(ret));
712 } else {
713 CX18_DEBUG_WARN("woken up before mailbox ack was ready "
714 "after submitting %s to RPU. only "
715 "waited %d msecs on req %u but awakened"
716 " with unmatched ack %u\n",
717 info->name,
718 jiffies_to_msecs(ret),
719 req, ack);
720 }
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300721 return -EINVAL;
Andy Walls330c6ec2008-11-08 14:19:37 -0300722 }
723
Andy Walls5f0a3cf2009-04-13 22:53:09 -0300724 if (ret >= timeout)
725 CX18_DEBUG_WARN("failed to be awakened upon RPU acknowledgment "
726 "sending %s; timed out waiting %d msecs\n",
727 info->name, jiffies_to_msecs(ret));
728 else
Andy Walls330c6ec2008-11-08 14:19:37 -0300729 CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n",
Andy Walls5f0a3cf2009-04-13 22:53:09 -0300730 jiffies_to_msecs(ret), info->name);
Andy Walls72c2d6d2008-11-06 01:15:41 -0300731
Andy Wallsac504412008-11-07 23:57:46 -0300732 /* Collect data returned by the XPU */
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300733 for (i = 0; i < MAX_MB_ARGUMENTS; i++)
Andy Wallsb1526422008-08-30 16:03:44 -0300734 data[i] = cx18_readl(cx, &mb->args[i]);
735 err = cx18_readl(cx, &mb->error);
Andy Walls72c2d6d2008-11-06 01:15:41 -0300736 mutex_unlock(mb_lock);
Andy Wallsac504412008-11-07 23:57:46 -0300737
738 /*
739 * Wait for XPU to perform extra actions for the caller in some cases.
Andy Walls52fcb3e2009-11-08 23:45:24 -0300740 * e.g. CX18_CPU_DE_RELEASE_MDL will cause the CPU to send all MDLs
Andy Wallsac504412008-11-07 23:57:46 -0300741 * back in a burst shortly thereafter
742 */
Andy Walls72c2d6d2008-11-06 01:15:41 -0300743 if (info->flags & API_SLOW)
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300744 cx18_msleep_timeout(300, 0);
Andy Wallsac504412008-11-07 23:57:46 -0300745
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300746 if (err)
747 CX18_DEBUG_API("mailbox error %08x for command %s\n", err,
748 info->name);
749 return err ? -EIO : 0;
750}
751
752int cx18_api(struct cx18 *cx, u32 cmd, int args, u32 data[])
753{
Andy Wallsac504412008-11-07 23:57:46 -0300754 return cx18_api_call(cx, cmd, args, data);
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300755}
756
757static int cx18_set_filter_param(struct cx18_stream *s)
758{
759 struct cx18 *cx = s->cx;
760 u32 mode;
761 int ret;
762
763 mode = (cx->filter_mode & 1) ? 2 : (cx->spatial_strength ? 1 : 0);
764 ret = cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
765 s->handle, 1, mode, cx->spatial_strength);
766 mode = (cx->filter_mode & 2) ? 2 : (cx->temporal_strength ? 1 : 0);
767 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
768 s->handle, 0, mode, cx->temporal_strength);
769 ret = ret ? ret : cx18_vapi(cx, CX18_CPU_SET_FILTER_PARAM, 4,
770 s->handle, 2, cx->filter_mode >> 2, 0);
771 return ret;
772}
773
774int cx18_api_func(void *priv, u32 cmd, int in, int out,
775 u32 data[CX2341X_MBOX_MAX_DATA])
776{
Hans Verkuila75b9be2010-12-31 10:22:52 -0300777 struct cx18_stream *s = priv;
778 struct cx18 *cx = s->cx;
Hans Verkuil1c1e45d2008-04-28 20:24:33 -0300779
780 switch (cmd) {
781 case CX2341X_ENC_SET_OUTPUT_PORT:
782 return 0;
783 case CX2341X_ENC_SET_FRAME_RATE:
784 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_IN, 6,
785 s->handle, 0, 0, 0, 0, data[0]);
786 case CX2341X_ENC_SET_FRAME_SIZE:
787 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RESOLUTION, 3,
788 s->handle, data[1], data[0]);
789 case CX2341X_ENC_SET_STREAM_TYPE:
790 return cx18_vapi(cx, CX18_CPU_SET_STREAM_OUTPUT_TYPE, 2,
791 s->handle, data[0]);
792 case CX2341X_ENC_SET_ASPECT_RATIO:
793 return cx18_vapi(cx, CX18_CPU_SET_ASPECT_RATIO, 2,
794 s->handle, data[0]);
795
796 case CX2341X_ENC_SET_GOP_PROPERTIES:
797 return cx18_vapi(cx, CX18_CPU_SET_GOP_STRUCTURE, 3,
798 s->handle, data[0], data[1]);
799 case CX2341X_ENC_SET_GOP_CLOSURE:
800 return 0;
801 case CX2341X_ENC_SET_AUDIO_PROPERTIES:
802 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_PARAMETERS, 2,
803 s->handle, data[0]);
804 case CX2341X_ENC_MUTE_AUDIO:
805 return cx18_vapi(cx, CX18_CPU_SET_AUDIO_MUTE, 2,
806 s->handle, data[0]);
807 case CX2341X_ENC_SET_BIT_RATE:
808 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_RATE, 5,
809 s->handle, data[0], data[1], data[2], data[3]);
810 case CX2341X_ENC_MUTE_VIDEO:
811 return cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2,
812 s->handle, data[0]);
813 case CX2341X_ENC_SET_FRAME_DROP_RATE:
814 return cx18_vapi(cx, CX18_CPU_SET_SKIP_INPUT_FRAME, 2,
815 s->handle, data[0]);
816 case CX2341X_ENC_MISC:
817 return cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 4,
818 s->handle, data[0], data[1], data[2]);
819 case CX2341X_ENC_SET_DNR_FILTER_MODE:
820 cx->filter_mode = (data[0] & 3) | (data[1] << 2);
821 return cx18_set_filter_param(s);
822 case CX2341X_ENC_SET_DNR_FILTER_PROPS:
823 cx->spatial_strength = data[0];
824 cx->temporal_strength = data[1];
825 return cx18_set_filter_param(s);
826 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
827 return cx18_vapi(cx, CX18_CPU_SET_SPATIAL_FILTER_TYPE, 3,
828 s->handle, data[0], data[1]);
829 case CX2341X_ENC_SET_CORING_LEVELS:
830 return cx18_vapi(cx, CX18_CPU_SET_MEDIAN_CORING, 5,
831 s->handle, data[0], data[1], data[2], data[3]);
832 }
833 CX18_WARN("Unknown cmd %x\n", cmd);
834 return 0;
835}
836
837int cx18_vapi_result(struct cx18 *cx, u32 data[MAX_MB_ARGUMENTS],
838 u32 cmd, int args, ...)
839{
840 va_list ap;
841 int i;
842
843 va_start(ap, args);
844 for (i = 0; i < args; i++)
845 data[i] = va_arg(ap, u32);
846 va_end(ap);
847 return cx18_api(cx, cmd, args, data);
848}
849
850int cx18_vapi(struct cx18 *cx, u32 cmd, int args, ...)
851{
852 u32 data[MAX_MB_ARGUMENTS];
853 va_list ap;
854 int i;
855
856 if (cx == NULL) {
857 CX18_ERR("cx == NULL (cmd=%x)\n", cmd);
858 return 0;
859 }
860 if (args > MAX_MB_ARGUMENTS) {
861 CX18_ERR("args too big (cmd=%x)\n", cmd);
862 args = MAX_MB_ARGUMENTS;
863 }
864 va_start(ap, args);
865 for (i = 0; i < args; i++)
866 data[i] = va_arg(ap, u32);
867 va_end(ap);
868 return cx18_api(cx, cmd, args, data);
869}