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Ben Dooks431107e2010-01-26 10:11:04 +09001/* linux/arch/arm/mach-s3c64xx/mach-smdk6410.c
Ben Dooks5718df92008-10-21 14:07:09 +01002 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/timer.h>
19#include <linux/init.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
Ben Dooks096941e2008-10-31 16:14:59 +000023#include <linux/i2c.h>
Mark Browna7a81d02010-02-17 18:19:31 +000024#include <linux/leds.h>
Ben Dooks438a5d42008-11-19 15:41:34 +000025#include <linux/fb.h>
26#include <linux/gpio.h>
27#include <linux/delay.h>
Mark Brown3056ea02009-01-27 16:18:01 +000028#include <linux/smsc911x.h>
Mark Brown42015c12009-11-03 14:42:06 +000029#include <linux/regulator/fixed.h>
Ben Dooks438a5d42008-11-19 15:41:34 +000030
Mark Brownecc558a2009-02-17 15:59:38 +000031#ifdef CONFIG_SMDK6410_WM1190_EV1
32#include <linux/mfd/wm8350/core.h>
33#include <linux/mfd/wm8350/pmic.h>
34#endif
Ben Dooks438a5d42008-11-19 15:41:34 +000035
Mark Brown60f91012010-02-17 18:19:29 +000036#ifdef CONFIG_SMDK6410_WM1192_EV1
Mark Browna7a81d02010-02-17 18:19:31 +000037#include <linux/mfd/wm831x/core.h>
Mark Brown60f91012010-02-17 18:19:29 +000038#include <linux/mfd/wm831x/pdata.h>
39#endif
40
Ben Dooks438a5d42008-11-19 15:41:34 +000041#include <video/platform_lcd.h>
Ben Dooks5718df92008-10-21 14:07:09 +010042
43#include <asm/mach/arch.h>
44#include <asm/mach/map.h>
45#include <asm/mach/irq.h>
46
47#include <mach/hardware.h>
Ben Dooks438a5d42008-11-19 15:41:34 +000048#include <mach/regs-fb.h>
Ben Dooks5718df92008-10-21 14:07:09 +010049#include <mach/map.h>
50
51#include <asm/irq.h>
52#include <asm/mach-types.h>
53
54#include <plat/regs-serial.h>
Ben Dooks3501c9a2010-01-26 10:45:40 +090055#include <mach/regs-modem.h>
56#include <mach/regs-gpio.h>
57#include <mach/regs-sys.h>
58#include <mach/regs-srom.h>
Abhilash Kesavan0ab0b6d2010-06-08 16:55:45 +090059#include <plat/ata.h>
Ben Dooksd85fa242008-10-31 16:14:52 +000060#include <plat/iic.h>
Ben Dooks438a5d42008-11-19 15:41:34 +000061#include <plat/fb.h>
Mark Brown3056ea02009-01-27 16:18:01 +000062#include <plat/gpio-cfg.h>
Ben Dooks5718df92008-10-21 14:07:09 +010063
Ben Dooksf7be9ab2010-01-26 13:41:30 +090064#include <mach/s3c6410.h>
Ben Dooks5718df92008-10-21 14:07:09 +010065#include <plat/clock.h>
66#include <plat/devs.h>
67#include <plat/cpu.h>
Naveen Krishna Ch85b14a32010-05-20 11:39:52 +090068#include <plat/adc.h>
69#include <plat/ts.h>
Ben Dooks5718df92008-10-21 14:07:09 +010070
71#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
72#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
73#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
74
75static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
76 [0] = {
77 .hwport = 0,
78 .flags = 0,
Matt Hsubd258e52009-06-29 19:03:41 +080079 .ucon = UCON,
80 .ulcon = ULCON,
81 .ufcon = UFCON,
Ben Dooks5718df92008-10-21 14:07:09 +010082 },
83 [1] = {
84 .hwport = 1,
85 .flags = 0,
Matt Hsubd258e52009-06-29 19:03:41 +080086 .ucon = UCON,
87 .ulcon = ULCON,
88 .ufcon = UFCON,
89 },
90 [2] = {
91 .hwport = 2,
92 .flags = 0,
93 .ucon = UCON,
94 .ulcon = ULCON,
95 .ufcon = UFCON,
96 },
97 [3] = {
98 .hwport = 3,
99 .flags = 0,
100 .ucon = UCON,
101 .ulcon = ULCON,
102 .ufcon = UFCON,
Ben Dooks5718df92008-10-21 14:07:09 +0100103 },
104};
105
Ben Dooks438a5d42008-11-19 15:41:34 +0000106/* framebuffer and LCD setup. */
107
108/* GPF15 = LCD backlight control
109 * GPF13 => Panel power
110 * GPN5 = LCD nRESET signal
111 * PWM_TOUT1 => backlight brightness
112 */
113
114static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
115 unsigned int power)
116{
117 if (power) {
118 gpio_direction_output(S3C64XX_GPF(13), 1);
119 gpio_direction_output(S3C64XX_GPF(15), 1);
120
121 /* fire nRESET on power up */
122 gpio_direction_output(S3C64XX_GPN(5), 0);
123 msleep(10);
124 gpio_direction_output(S3C64XX_GPN(5), 1);
125 msleep(1);
126 } else {
127 gpio_direction_output(S3C64XX_GPF(15), 0);
128 gpio_direction_output(S3C64XX_GPF(13), 0);
129 }
130}
131
132static struct plat_lcd_data smdk6410_lcd_power_data = {
133 .set_power = smdk6410_lcd_power_set,
134};
135
136static struct platform_device smdk6410_lcd_powerdev = {
137 .name = "platform-lcd",
138 .dev.parent = &s3c_device_fb.dev,
139 .dev.platform_data = &smdk6410_lcd_power_data,
140};
141
142static struct s3c_fb_pd_win smdk6410_fb_win0 = {
143 /* this is to ensure we use win0 */
144 .win_mode = {
145 .pixclock = 41094,
146 .left_margin = 8,
147 .right_margin = 13,
148 .upper_margin = 7,
149 .lower_margin = 5,
150 .hsync_len = 3,
151 .vsync_len = 1,
152 .xres = 800,
153 .yres = 480,
154 },
155 .max_bpp = 32,
156 .default_bpp = 16,
157};
158
159/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
160static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
161 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
162 .win[0] = &smdk6410_fb_win0,
163 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
164 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
165};
166
Andy Greena4e94692009-12-29 14:40:43 +0000167/*
168 * Configuring Ethernet on SMDK6410
169 *
170 * Both CS8900A and LAN9115 chips share one chip select mediated by CFG6.
171 * The constant address below corresponds to nCS1
172 *
173 * 1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet"
174 * 2) CFG6 needs to be switched to "LAN9115" side
175 */
176
Mark Brown3056ea02009-01-27 16:18:01 +0000177static struct resource smdk6410_smsc911x_resources[] = {
178 [0] = {
Andy Greenf01fdac2009-12-29 14:40:36 +0000179 .start = S3C64XX_PA_XM0CSN1,
180 .end = S3C64XX_PA_XM0CSN1 + SZ_64K - 1,
Mark Brown3056ea02009-01-27 16:18:01 +0000181 .flags = IORESOURCE_MEM,
182 },
183 [1] = {
184 .start = S3C_EINT(10),
185 .end = S3C_EINT(10),
186 .flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
187 },
188};
189
190static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
191 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
192 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
193 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
194 .phy_interface = PHY_INTERFACE_MODE_MII,
195};
196
197
198static struct platform_device smdk6410_smsc911x = {
199 .name = "smsc911x",
200 .id = -1,
201 .num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
202 .resource = &smdk6410_smsc911x_resources[0],
203 .dev = {
204 .platform_data = &smdk6410_smsc911x_pdata,
205 },
206};
207
Mark Brown42015c12009-11-03 14:42:06 +0000208#ifdef CONFIG_REGULATOR
209static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
210 {
211 /* WM8580 */
212 .supply = "PVDD",
213 .dev_name = "0-001b",
214 },
215 {
216 /* WM8580 */
217 .supply = "AVDD",
218 .dev_name = "0-001b",
219 },
220};
221
222static struct regulator_init_data smdk6410_b_pwr_5v_data = {
223 .constraints = {
224 .always_on = 1,
225 },
226 .num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
227 .consumer_supplies = smdk6410_b_pwr_5v_consumers,
228};
229
230static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
231 .supply_name = "B_PWR_5V",
232 .microvolts = 5000000,
233 .init_data = &smdk6410_b_pwr_5v_data,
Mark Brownd3cf4482010-01-13 13:57:04 +0000234 .gpio = -EINVAL,
Mark Brown42015c12009-11-03 14:42:06 +0000235};
236
237static struct platform_device smdk6410_b_pwr_5v = {
238 .name = "reg-fixed-voltage",
239 .id = -1,
240 .dev = {
241 .platform_data = &smdk6410_b_pwr_5v_pdata,
242 },
243};
244#endif
245
Abhilash Kesavan0ab0b6d2010-06-08 16:55:45 +0900246static struct s3c_ide_platdata smdk6410_ide_pdata __initdata = {
247 .setup_gpio = s3c64xx_ide_setup_gpio,
248};
249
Mark Brown027191a2009-01-23 16:29:43 +0000250static struct map_desc smdk6410_iodesc[] = {};
Ben Dooks5718df92008-10-21 14:07:09 +0100251
252static struct platform_device *smdk6410_devices[] __initdata = {
Ben Dooksb24636c2008-11-03 20:14:53 +0000253#ifdef CONFIG_SMDK6410_SD_CH0
Ben Dooks39057f22008-10-31 16:14:29 +0000254 &s3c_device_hsmmc0,
Ben Dooksb24636c2008-11-03 20:14:53 +0000255#endif
256#ifdef CONFIG_SMDK6410_SD_CH1
257 &s3c_device_hsmmc1,
258#endif
Ben Dooksd85fa242008-10-31 16:14:52 +0000259 &s3c_device_i2c0,
Ben Dooksd7ea3742008-10-31 16:14:57 +0000260 &s3c_device_i2c1,
Ben Dooks438a5d42008-11-19 15:41:34 +0000261 &s3c_device_fb,
Ben Dooksb8132482009-11-23 00:13:39 +0000262 &s3c_device_ohci,
Ben Dooks06fa1d32009-05-16 22:11:20 +0100263 &s3c_device_usb_hsotg,
Mark Brown1f100862010-02-17 19:03:20 +0000264 &s3c64xx_device_iisv4,
Mark Brown42015c12009-11-03 14:42:06 +0000265
266#ifdef CONFIG_REGULATOR
267 &smdk6410_b_pwr_5v,
268#endif
Ben Dooks438a5d42008-11-19 15:41:34 +0000269 &smdk6410_lcd_powerdev,
Mark Brown3056ea02009-01-27 16:18:01 +0000270
271 &smdk6410_smsc911x,
Naveen Krishna Ch85b14a32010-05-20 11:39:52 +0900272 &s3c_device_adc,
Abhilash Kesavan0ab0b6d2010-06-08 16:55:45 +0900273 &s3c_device_cfcon,
Naveen Krishna Ch85b14a32010-05-20 11:39:52 +0900274 &s3c_device_ts,
Banajit Goswamib351c4a2010-05-20 16:21:30 +0900275 &s3c_device_wdt,
Ben Dooks5718df92008-10-21 14:07:09 +0100276};
277
Mark Brown60f91012010-02-17 18:19:29 +0000278#ifdef CONFIG_REGULATOR
279/* ARM core */
280static struct regulator_consumer_supply smdk6410_vddarm_consumers[] = {
281 {
282 .supply = "vddarm",
283 }
284};
285
286/* VDDARM, BUCK1 on J5 */
287static struct regulator_init_data smdk6410_vddarm = {
288 .constraints = {
289 .name = "PVDD_ARM",
290 .min_uV = 1000000,
291 .max_uV = 1300000,
292 .always_on = 1,
293 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
294 },
295 .num_consumer_supplies = ARRAY_SIZE(smdk6410_vddarm_consumers),
296 .consumer_supplies = smdk6410_vddarm_consumers,
297};
298
299/* VDD_INT, BUCK2 on J5 */
300static struct regulator_init_data smdk6410_vddint = {
301 .constraints = {
302 .name = "PVDD_INT",
303 .min_uV = 1000000,
304 .max_uV = 1200000,
305 .always_on = 1,
306 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
307 },
308};
309
310/* VDD_HI, LDO3 on J5 */
311static struct regulator_init_data smdk6410_vddhi = {
312 .constraints = {
313 .name = "PVDD_HI",
314 .always_on = 1,
315 },
316};
317
318/* VDD_PLL, LDO2 on J5 */
319static struct regulator_init_data smdk6410_vddpll = {
320 .constraints = {
321 .name = "PVDD_PLL",
322 .always_on = 1,
323 },
324};
325
326/* VDD_UH_MMC, LDO5 on J5 */
327static struct regulator_init_data smdk6410_vdduh_mmc = {
328 .constraints = {
329 .name = "PVDD_UH/PVDD_MMC",
330 .always_on = 1,
331 },
332};
333
334/* VCCM3BT, LDO8 on J5 */
335static struct regulator_init_data smdk6410_vccmc3bt = {
336 .constraints = {
337 .name = "PVCCM3BT",
338 .always_on = 1,
339 },
340};
341
342/* VCCM2MTV, LDO11 on J5 */
343static struct regulator_init_data smdk6410_vccm2mtv = {
344 .constraints = {
345 .name = "PVCCM2MTV",
346 .always_on = 1,
347 },
348};
349
350/* VDD_LCD, LDO12 on J5 */
351static struct regulator_init_data smdk6410_vddlcd = {
352 .constraints = {
353 .name = "PVDD_LCD",
354 .always_on = 1,
355 },
356};
357
358/* VDD_OTGI, LDO9 on J5 */
359static struct regulator_init_data smdk6410_vddotgi = {
360 .constraints = {
361 .name = "PVDD_OTGI",
362 .always_on = 1,
363 },
364};
365
366/* VDD_OTG, LDO14 on J5 */
367static struct regulator_init_data smdk6410_vddotg = {
368 .constraints = {
369 .name = "PVDD_OTG",
370 .always_on = 1,
371 },
372};
373
374/* VDD_ALIVE, LDO15 on J5 */
375static struct regulator_init_data smdk6410_vddalive = {
376 .constraints = {
377 .name = "PVDD_ALIVE",
378 .always_on = 1,
379 },
380};
381
382/* VDD_AUDIO, VLDO_AUDIO on J5 */
383static struct regulator_init_data smdk6410_vddaudio = {
384 .constraints = {
385 .name = "PVDD_AUDIO",
386 .always_on = 1,
387 },
388};
389#endif
390
Mark Brownecc558a2009-02-17 15:59:38 +0000391#ifdef CONFIG_SMDK6410_WM1190_EV1
392/* S3C64xx internal logic & PLL */
393static struct regulator_init_data wm8350_dcdc1_data = {
394 .constraints = {
395 .name = "PVDD_INT/PVDD_PLL",
396 .min_uV = 1200000,
397 .max_uV = 1200000,
398 .always_on = 1,
399 .apply_uV = 1,
400 },
401};
402
403/* Memory */
404static struct regulator_init_data wm8350_dcdc3_data = {
405 .constraints = {
406 .name = "PVDD_MEM",
407 .min_uV = 1800000,
408 .max_uV = 1800000,
409 .always_on = 1,
410 .state_mem = {
411 .uV = 1800000,
412 .mode = REGULATOR_MODE_NORMAL,
413 .enabled = 1,
Mark Brown60f91012010-02-17 18:19:29 +0000414 },
Mark Brownecc558a2009-02-17 15:59:38 +0000415 .initial_state = PM_SUSPEND_MEM,
416 },
417};
418
419/* USB, EXT, PCM, ADC/DAC, USB, MMC */
Mark Brown42015c12009-11-03 14:42:06 +0000420static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
421 {
422 /* WM8580 */
423 .supply = "DVDD",
424 .dev_name = "0-001b",
425 },
426};
427
Mark Brownecc558a2009-02-17 15:59:38 +0000428static struct regulator_init_data wm8350_dcdc4_data = {
429 .constraints = {
430 .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
431 .min_uV = 3000000,
432 .max_uV = 3000000,
433 .always_on = 1,
434 },
Mark Brown42015c12009-11-03 14:42:06 +0000435 .num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
436 .consumer_supplies = wm8350_dcdc4_consumers,
Mark Brownecc558a2009-02-17 15:59:38 +0000437};
438
Mark Brownecc558a2009-02-17 15:59:38 +0000439/* OTGi/1190-EV1 HPVDD & AVDD */
440static struct regulator_init_data wm8350_ldo4_data = {
441 .constraints = {
442 .name = "PVDD_OTGI/HPVDD/AVDD",
443 .min_uV = 1200000,
444 .max_uV = 1200000,
445 .apply_uV = 1,
Mark Brownf53aee22009-04-09 16:30:40 +0100446 .always_on = 1,
Mark Brownecc558a2009-02-17 15:59:38 +0000447 },
448};
449
450static struct {
451 int regulator;
452 struct regulator_init_data *initdata;
453} wm1190_regulators[] = {
454 { WM8350_DCDC_1, &wm8350_dcdc1_data },
455 { WM8350_DCDC_3, &wm8350_dcdc3_data },
456 { WM8350_DCDC_4, &wm8350_dcdc4_data },
Mark Brown60f91012010-02-17 18:19:29 +0000457 { WM8350_DCDC_6, &smdk6410_vddarm },
458 { WM8350_LDO_1, &smdk6410_vddalive },
459 { WM8350_LDO_2, &smdk6410_vddotg },
460 { WM8350_LDO_3, &smdk6410_vddlcd },
Mark Brownecc558a2009-02-17 15:59:38 +0000461 { WM8350_LDO_4, &wm8350_ldo4_data },
462};
463
464static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
465{
466 int i;
467
Mark Browna3323b72009-11-03 14:42:04 +0000468 /* Configure the IRQ line */
469 s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
470
Mark Brownecc558a2009-02-17 15:59:38 +0000471 /* Instantiate the regulators */
472 for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
473 wm8350_register_regulator(wm8350,
474 wm1190_regulators[i].regulator,
475 wm1190_regulators[i].initdata);
476
477 return 0;
478}
479
480static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
481 .init = smdk6410_wm8350_init,
Mark Browndb9256f2009-04-09 19:00:19 +0100482 .irq_high = 1,
Mark Brown9fca8782010-01-19 15:26:56 +0000483 .irq_base = IRQ_BOARD_START,
Mark Brownecc558a2009-02-17 15:59:38 +0000484};
485#endif
486
Mark Brown60f91012010-02-17 18:19:29 +0000487#ifdef CONFIG_SMDK6410_WM1192_EV1
Mark Browna7a81d02010-02-17 18:19:31 +0000488static struct gpio_led wm1192_pmic_leds[] = {
489 {
490 .name = "PMIC:red:power",
491 .gpio = GPIO_BOARD_START + 3,
492 .default_state = LEDS_GPIO_DEFSTATE_ON,
493 },
494};
495
496static struct gpio_led_platform_data wm1192_pmic_led = {
497 .num_leds = ARRAY_SIZE(wm1192_pmic_leds),
498 .leds = wm1192_pmic_leds,
499};
500
501static struct platform_device wm1192_pmic_led_dev = {
502 .name = "leds-gpio",
503 .id = -1,
504 .dev = {
505 .platform_data = &wm1192_pmic_led,
506 },
507};
508
Mark Brown60f91012010-02-17 18:19:29 +0000509static int wm1192_pre_init(struct wm831x *wm831x)
510{
Mark Browna7a81d02010-02-17 18:19:31 +0000511 int ret;
512
Mark Brown60f91012010-02-17 18:19:29 +0000513 /* Configure the IRQ line */
514 s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
515
Mark Browna7a81d02010-02-17 18:19:31 +0000516 ret = platform_device_register(&wm1192_pmic_led_dev);
517 if (ret != 0)
518 dev_err(wm831x->dev, "Failed to add PMIC LED: %d\n", ret);
519
Mark Brown60f91012010-02-17 18:19:29 +0000520 return 0;
521}
522
523static struct wm831x_backlight_pdata wm1192_backlight_pdata = {
524 .isink = 1,
525 .max_uA = 27554,
526};
527
528static struct regulator_init_data wm1192_dcdc3 = {
529 .constraints = {
530 .name = "PVDD_MEM/PVDD_GPS",
531 .always_on = 1,
532 },
533};
534
535static struct regulator_consumer_supply wm1192_ldo1_consumers[] = {
536 { .supply = "DVDD", .dev_name = "0-001b", }, /* WM8580 */
537};
538
539static struct regulator_init_data wm1192_ldo1 = {
540 .constraints = {
541 .name = "PVDD_LCD/PVDD_EXT",
542 .always_on = 1,
543 },
544 .consumer_supplies = wm1192_ldo1_consumers,
545 .num_consumer_supplies = ARRAY_SIZE(wm1192_ldo1_consumers),
546};
547
548static struct wm831x_status_pdata wm1192_led7_pdata = {
549 .name = "LED7:green:",
550};
551
552static struct wm831x_status_pdata wm1192_led8_pdata = {
553 .name = "LED8:green:",
554};
555
556static struct wm831x_pdata smdk6410_wm1192_pdata = {
557 .pre_init = wm1192_pre_init,
558 .irq_base = IRQ_BOARD_START,
559
560 .backlight = &wm1192_backlight_pdata,
561 .dcdc = {
562 &smdk6410_vddarm, /* DCDC1 */
563 &smdk6410_vddint, /* DCDC2 */
564 &wm1192_dcdc3,
565 },
Mark Browna7a81d02010-02-17 18:19:31 +0000566 .gpio_base = GPIO_BOARD_START,
Mark Brown60f91012010-02-17 18:19:29 +0000567 .ldo = {
568 &wm1192_ldo1, /* LDO1 */
569 &smdk6410_vdduh_mmc, /* LDO2 */
570 NULL, /* LDO3 NC */
571 &smdk6410_vddotgi, /* LDO4 */
572 &smdk6410_vddotg, /* LDO5 */
573 &smdk6410_vddhi, /* LDO6 */
574 &smdk6410_vddaudio, /* LDO7 */
575 &smdk6410_vccm2mtv, /* LDO8 */
576 &smdk6410_vddpll, /* LDO9 */
577 &smdk6410_vccmc3bt, /* LDO10 */
578 &smdk6410_vddalive, /* LDO11 */
579 },
580 .status = {
581 &wm1192_led7_pdata,
582 &wm1192_led8_pdata,
583 },
584};
585#endif
586
Ben Dooks096941e2008-10-31 16:14:59 +0000587static struct i2c_board_info i2c_devs0[] __initdata = {
588 { I2C_BOARD_INFO("24c08", 0x50), },
Mark Brown77897472009-01-23 16:29:41 +0000589 { I2C_BOARD_INFO("wm8580", 0x1b), },
Mark Brownecc558a2009-02-17 15:59:38 +0000590
Mark Brown60f91012010-02-17 18:19:29 +0000591#ifdef CONFIG_SMDK6410_WM1192_EV1
592 { I2C_BOARD_INFO("wm8312", 0x34),
593 .platform_data = &smdk6410_wm1192_pdata,
594 .irq = S3C_EINT(12),
595 },
596#endif
597
Mark Brownecc558a2009-02-17 15:59:38 +0000598#ifdef CONFIG_SMDK6410_WM1190_EV1
599 { I2C_BOARD_INFO("wm8350", 0x1a),
600 .platform_data = &smdk6410_wm8350_pdata,
601 .irq = S3C_EINT(12),
602 },
603#endif
Ben Dooks096941e2008-10-31 16:14:59 +0000604};
605
606static struct i2c_board_info i2c_devs1[] __initdata = {
607 { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
Ben Dooks5718df92008-10-21 14:07:09 +0100608};
609
Naveen Krishna Ch85b14a32010-05-20 11:39:52 +0900610static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
611 .delay = 10000,
612 .presc = 49,
613 .oversampling_shift = 2,
614};
615
Ben Dooks5718df92008-10-21 14:07:09 +0100616static void __init smdk6410_map_io(void)
617{
Ben Dooksd6662c32008-12-12 00:24:40 +0000618 u32 tmp;
619
Ben Dooks5718df92008-10-21 14:07:09 +0100620 s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
621 s3c24xx_init_clocks(12000000);
622 s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
Ben Dooksd6662c32008-12-12 00:24:40 +0000623
624 /* set the LCD type */
625
626 tmp = __raw_readl(S3C64XX_SPCON);
627 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
628 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
629 __raw_writel(tmp, S3C64XX_SPCON);
630
631 /* remove the lcd bypass */
632 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
633 tmp &= ~MIFPCON_LCD_BYPASS;
634 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
Ben Dooks5718df92008-10-21 14:07:09 +0100635}
636
637static void __init smdk6410_machine_init(void)
638{
Andy Greenf01fdac2009-12-29 14:40:36 +0000639 u32 cs1;
640
Ben Dooksd85fa242008-10-31 16:14:52 +0000641 s3c_i2c0_set_platdata(NULL);
Ben Dooksd7ea3742008-10-31 16:14:57 +0000642 s3c_i2c1_set_platdata(NULL);
Ben Dooks438a5d42008-11-19 15:41:34 +0000643 s3c_fb_set_platdata(&smdk6410_lcd_pdata);
Ben Dooks096941e2008-10-31 16:14:59 +0000644
Naveen Krishna Ch85b14a32010-05-20 11:39:52 +0900645 s3c24xx_ts_set_platdata(&s3c_ts_platform);
646
Andy Greenf01fdac2009-12-29 14:40:36 +0000647 /* configure nCS1 width to 16 bits */
648
649 cs1 = __raw_readl(S3C64XX_SROM_BW) &
650 ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
651 cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
652 (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
653 (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
654 S3C64XX_SROM_BW__NCS1__SHIFT;
655 __raw_writel(cs1, S3C64XX_SROM_BW);
656
657 /* set timing for nCS1 suitable for ethernet chip */
658
659 __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
660 (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
661 (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
662 (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
663 (0xe << S3C64XX_SROM_BCX__TACC__SHIFT) |
664 (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
665 (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
666
Mark Brownb7f9a942009-04-08 16:12:35 +0100667 gpio_request(S3C64XX_GPN(5), "LCD power");
668 gpio_request(S3C64XX_GPF(13), "LCD power");
669 gpio_request(S3C64XX_GPF(15), "LCD power");
670
Ben Dooks096941e2008-10-31 16:14:59 +0000671 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
672 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
673
Abhilash Kesavan0ab0b6d2010-06-08 16:55:45 +0900674 s3c_ide_set_platdata(&smdk6410_ide_pdata);
675
Ben Dooks5718df92008-10-21 14:07:09 +0100676 platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
677}
678
679MACHINE_START(SMDK6410, "SMDK6410")
Ben Dooksafdd2252010-05-07 09:24:05 +0900680 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
Ben Dooks5718df92008-10-21 14:07:09 +0100681 .phys_io = S3C_PA_UART & 0xfff00000,
682 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
683 .boot_params = S3C64XX_PA_SDRAM + 0x100,
684
685 .init_irq = s3c6410_init_irq,
686 .map_io = smdk6410_map_io,
687 .init_machine = smdk6410_machine_init,
688 .timer = &s3c24xx_timer,
689MACHINE_END