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Kuninori Morimoto6c01ba42011-11-10 18:45:52 -08001/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
Kuninori Morimoto215d6cc2011-11-10 18:46:35 -080021#include <linux/init.h>
Kuninori Morimoto6c01ba42011-11-10 18:45:52 -080022#include <linux/io.h>
Bastian Hecht0b7d7822013-03-27 14:54:04 +010023#include <linux/irqchip/arm-gic.h>
Kuninori Morimoto6c01ba42011-11-10 18:45:52 -080024
25void __init r8a7740_init_irq(void)
26{
Bastian Hecht0b7d7822013-03-27 14:54:04 +010027 void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
28 void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
29 void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
30 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
31 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
Kuninori Morimoto6c01ba42011-11-10 18:45:52 -080032
Bastian Hecht0b7d7822013-03-27 14:54:04 +010033 /* initialize the Generic Interrupt Controller PL390 r0p0 */
34 gic_init(0, 29, gic_dist_base, gic_cpu_base);
Kuninori Morimoto6c01ba42011-11-10 18:45:52 -080035
Bastian Hecht0b7d7822013-03-27 14:54:04 +010036 /* route signals to GIC */
37 iowrite32(0x0, pfc_inta_ctrl);
38
39 /*
40 * To mask the shared interrupt to SPI 149 we must ensure to set
41 * PRIO *and* MASK. Else we run into IRQ floods when registering
42 * the intc_irqpin devices
43 */
44 iowrite32(0x0, intc_prio_base + 0x0);
45 iowrite32(0x0, intc_prio_base + 0x4);
46 iowrite32(0x0, intc_prio_base + 0x8);
47 iowrite32(0x0, intc_prio_base + 0xc);
48 iowrite8(0xff, intc_msk_base + 0x0);
49 iowrite8(0xff, intc_msk_base + 0x4);
50 iowrite8(0xff, intc_msk_base + 0x8);
51 iowrite8(0xff, intc_msk_base + 0xc);
52
53 iounmap(intc_prio_base);
54 iounmap(intc_msk_base);
55 iounmap(pfc_inta_ctrl);
Kuninori Morimoto6c01ba42011-11-10 18:45:52 -080056}