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review.evervolv.com / android_kernel_oneplus_msm8996 / 109269e87895caaa927bc313bc2a2cad8a114b08 / . / arch / arm / boot / dts / tegra20.dtsi
blob: cdb8da0b69833f6f3084b5c7a48f7db7a5b80311 [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>;
6
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]7 aliases {
8 serial0 = &uarta;
9 serial1 = &uartb;
10 serial2 = &uartc;
11 serial3 = &uartd;
12 serial4 = &uarte;
13 };
14
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]15 host1x {
16 compatible = "nvidia,tegra20-host1x", "simple-bus";
17 reg = <0x50000000 0x00024000>;
18 interrupts = <0 65 0x04 /* mpcore syncpt */
19 0 67 0x04>; /* mpcore general */
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]20 clocks = <&tegra_car 28>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]21
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 ranges = <0x54000000 0x54000000 0x04000000>;
26
27 mpe {
28 compatible = "nvidia,tegra20-mpe";
29 reg = <0x54040000 0x00040000>;
30 interrupts = <0 68 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]31 clocks = <&tegra_car 60>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]32 };
33
34 vi {
35 compatible = "nvidia,tegra20-vi";
36 reg = <0x54080000 0x00040000>;
37 interrupts = <0 69 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]38 clocks = <&tegra_car 100>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]39 };
40
41 epp {
42 compatible = "nvidia,tegra20-epp";
43 reg = <0x540c0000 0x00040000>;
44 interrupts = <0 70 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]45 clocks = <&tegra_car 19>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]46 };
47
48 isp {
49 compatible = "nvidia,tegra20-isp";
50 reg = <0x54100000 0x00040000>;
51 interrupts = <0 71 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]52 clocks = <&tegra_car 23>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]53 };
54
55 gr2d {
56 compatible = "nvidia,tegra20-gr2d";
57 reg = <0x54140000 0x00040000>;
58 interrupts = <0 72 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]59 clocks = <&tegra_car 21>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]60 };
61
62 gr3d {
63 compatible = "nvidia,tegra20-gr3d";
64 reg = <0x54180000 0x00040000>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]65 clocks = <&tegra_car 24>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]66 };
67
68 dc@54200000 {
69 compatible = "nvidia,tegra20-dc";
70 reg = <0x54200000 0x00040000>;
71 interrupts = <0 73 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]72 clocks = <&tegra_car 27>, <&tegra_car 121>;
73 clock-names = "disp1", "parent";
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]74
75 rgb {
76 status = "disabled";
77 };
78 };
79
80 dc@54240000 {
81 compatible = "nvidia,tegra20-dc";
82 reg = <0x54240000 0x00040000>;
83 interrupts = <0 74 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]84 clocks = <&tegra_car 26>, <&tegra_car 121>;
85 clock-names = "disp2", "parent";
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]86
87 rgb {
88 status = "disabled";
89 };
90 };
91
92 hdmi {
93 compatible = "nvidia,tegra20-hdmi";
94 reg = <0x54280000 0x00040000>;
95 interrupts = <0 75 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]96 clocks = <&tegra_car 51>, <&tegra_car 117>;
97 clock-names = "hdmi", "parent";
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]98 status = "disabled";
99 };
100
101 tvo {
102 compatible = "nvidia,tegra20-tvo";
103 reg = <0x542c0000 0x00040000>;
104 interrupts = <0 76 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]105 clocks = <&tegra_car 102>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]106 status = "disabled";
107 };
108
109 dsi {
110 compatible = "nvidia,tegra20-dsi";
111 reg = <0x54300000 0x00040000>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]112 clocks = <&tegra_car 48>;
Thierry Redinged821f02012-11-15 22:07:54 +0100[diff] [blame]113 status = "disabled";
114 };
115 };
116
Stephen Warren73368ba2012-09-19 14:17:24 -0600[diff] [blame]117 timer@50004600 {
118 compatible = "arm,cortex-a9-twd-timer";
119 reg = <0x50040600 0x20>;
120 interrupts = <1 13 0x304>;
121 };
122
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]123 intc: interrupt-controller {
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]124 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]125 reg = <0x50041000 0x1000
126 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]127 interrupt-controller;
128 #interrupt-cells = <3>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]129 };
130
Stephen Warrenbb2c1de2013-01-14 10:09:16 -0700[diff] [blame]131 cache-controller {
132 compatible = "arm,pl310-cache";
133 reg = <0x50043000 0x1000>;
134 arm,data-latency = <5 5 2>;
135 arm,tag-latency = <4 4 2>;
136 cache-unified;
137 cache-level = <2>;
138 };
139
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]140 timer@60005000 {
141 compatible = "nvidia,tegra20-timer";
142 reg = <0x60005000 0x60>;
143 interrupts = <0 0 0x04
144 0 1 0x04
145 0 41 0x04
146 0 42 0x04>;
147 };
148
Stephen Warren270f8ce2013-01-11 13:16:22 +0530[diff] [blame]149 tegra_car: clock {
150 compatible = "nvidia,tegra20-car";
151 reg = <0x60006000 0x1000>;
152 #clock-cells = <1>;
153 };
154
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]155 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]156 compatible = "nvidia,tegra20-apbdma";
157 reg = <0x6000a000 0x1200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]158 interrupts = <0 104 0x04
159 0 105 0x04
160 0 106 0x04
161 0 107 0x04
162 0 108 0x04
163 0 109 0x04
164 0 110 0x04
165 0 111 0x04
166 0 112 0x04
167 0 113 0x04
168 0 114 0x04
169 0 115 0x04
170 0 116 0x04
171 0 117 0x04
172 0 118 0x04
173 0 119 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]174 clocks = <&tegra_car 34>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]175 };
176
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]177 ahb {
178 compatible = "nvidia,tegra20-ahb";
179 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]180 };
181
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]182 gpio: gpio {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]183 compatible = "nvidia,tegra20-gpio";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]184 reg = <0x6000d000 0x1000>;
185 interrupts = <0 32 0x04
186 0 33 0x04
187 0 34 0x04
188 0 35 0x04
189 0 55 0x04
190 0 87 0x04
191 0 89 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]192 #gpio-cells = <2>;
193 gpio-controller;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000[diff] [blame]194 #interrupt-cells = <2>;
195 interrupt-controller;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]196 };
197
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]198 pinmux: pinmux {
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]199 compatible = "nvidia,tegra20-pinmux";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]200 reg = <0x70000014 0x10 /* Tri-state registers */
201 0x70000080 0x20 /* Mux registers */
202 0x700000a0 0x14 /* Pull-up/down registers */
203 0x70000868 0xa8>; /* Pad control registers */
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]204 };
205
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]206 das {
207 compatible = "nvidia,tegra20-das";
208 reg = <0x70000c00 0x80>;
209 };
Lucas Stach0698ed12013-01-05 02:18:44 +0100[diff] [blame]210
211 tegra_ac97: ac97 {
212 compatible = "nvidia,tegra20-ac97";
213 reg = <0x70002000 0x200>;
214 interrupts = <0 81 0x04>;
215 nvidia,dma-request-selector = <&apbdma 12>;
216 clocks = <&tegra_car 3>;
217 status = "disabled";
218 };
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]219
220 tegra_i2s1: i2s@70002800 {
221 compatible = "nvidia,tegra20-i2s";
222 reg = <0x70002800 0x200>;
223 interrupts = <0 13 0x04>;
224 nvidia,dma-request-selector = <&apbdma 2>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]225 clocks = <&tegra_car 11>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]226 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]227 };
228
229 tegra_i2s2: i2s@70002a00 {
230 compatible = "nvidia,tegra20-i2s";
231 reg = <0x70002a00 0x200>;
232 interrupts = <0 3 0x04>;
233 nvidia,dma-request-selector = <&apbdma 1>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]234 clocks = <&tegra_car 18>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]235 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]236 };
237
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]238 /*
239 * There are two serial driver i.e. 8250 based simple serial
240 * driver and APB DMA based serial driver for higher baudrate
241 * and performace. To enable the 8250 based driver, the compatible
242 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
243 * driver, the comptible is "nvidia,tegra20-hsuart".
244 */
245 uarta: serial@70006000 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]246 compatible = "nvidia,tegra20-uart";
247 reg = <0x70006000 0x40>;
248 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]249 interrupts = <0 36 0x04>;
Lucas Stachab343e92013-01-22 22:46:07 +0100[diff] [blame]250 clock-frequency = <216000000>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]251 nvidia,dma-request-selector = <&apbdma 8>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]252 clocks = <&tegra_car 6>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]253 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]254 };
255
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]256 uartb: serial@70006040 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]257 compatible = "nvidia,tegra20-uart";
258 reg = <0x70006040 0x40>;
259 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]260 interrupts = <0 37 0x04>;
Lucas Stachab343e92013-01-22 22:46:07 +0100[diff] [blame]261 clock-frequency = <216000000>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]262 nvidia,dma-request-selector = <&apbdma 9>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]263 clocks = <&tegra_car 96>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]264 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]265 };
266
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]267 uartc: serial@70006200 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]268 compatible = "nvidia,tegra20-uart";
269 reg = <0x70006200 0x100>;
270 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]271 interrupts = <0 46 0x04>;
Lucas Stachab343e92013-01-22 22:46:07 +0100[diff] [blame]272 clock-frequency = <216000000>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]273 nvidia,dma-request-selector = <&apbdma 10>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]274 clocks = <&tegra_car 55>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]275 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]276 };
277
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]278 uartd: serial@70006300 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]279 compatible = "nvidia,tegra20-uart";
280 reg = <0x70006300 0x100>;
281 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]282 interrupts = <0 90 0x04>;
Lucas Stachab343e92013-01-22 22:46:07 +0100[diff] [blame]283 clock-frequency = <216000000>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]284 nvidia,dma-request-selector = <&apbdma 19>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]285 clocks = <&tegra_car 65>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]286 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]287 };
288
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]289 uarte: serial@70006400 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]290 compatible = "nvidia,tegra20-uart";
291 reg = <0x70006400 0x100>;
292 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]293 interrupts = <0 91 0x04>;
Lucas Stachab343e92013-01-22 22:46:07 +0100[diff] [blame]294 clock-frequency = <216000000>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]295 nvidia,dma-request-selector = <&apbdma 20>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]296 clocks = <&tegra_car 66>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]297 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]298 };
299
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]300 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]301 compatible = "nvidia,tegra20-pwm";
302 reg = <0x7000a000 0x100>;
303 #pwm-cells = <2>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]304 clocks = <&tegra_car 17>;
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]305 };
306
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame]307 rtc {
308 compatible = "nvidia,tegra20-rtc";
309 reg = <0x7000e000 0x100>;
310 interrupts = <0 2 0x04>;
311 };
312
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]313 i2c@7000c000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]314 compatible = "nvidia,tegra20-i2c";
315 reg = <0x7000c000 0x100>;
316 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]317 #address-cells = <1>;
318 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]319 clocks = <&tegra_car 12>, <&tegra_car 124>;
320 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]321 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]322 };
323
Laxman Dewanganfa98a112012-11-13 10:33:39 +0530[diff] [blame]324 spi@7000c380 {
325 compatible = "nvidia,tegra20-sflash";
326 reg = <0x7000c380 0x80>;
327 interrupts = <0 39 0x04>;
328 nvidia,dma-request-selector = <&apbdma 11>;
329 #address-cells = <1>;
330 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]331 clocks = <&tegra_car 43>;
Laxman Dewanganfa98a112012-11-13 10:33:39 +0530[diff] [blame]332 status = "disabled";
333 };
334
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]335 i2c@7000c400 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]336 compatible = "nvidia,tegra20-i2c";
337 reg = <0x7000c400 0x100>;
338 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]339 #address-cells = <1>;
340 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]341 clocks = <&tegra_car 54>, <&tegra_car 124>;
342 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]343 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]344 };
345
346 i2c@7000c500 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]347 compatible = "nvidia,tegra20-i2c";
348 reg = <0x7000c500 0x100>;
349 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]350 #address-cells = <1>;
351 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]352 clocks = <&tegra_car 67>, <&tegra_car 124>;
353 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]354 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]355 };
356
357 i2c@7000d000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]358 compatible = "nvidia,tegra20-i2c-dvc";
359 reg = <0x7000d000 0x200>;
360 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]361 #address-cells = <1>;
362 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]363 clocks = <&tegra_car 47>, <&tegra_car 124>;
364 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]365 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]366 };
367
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]368 spi@7000d400 {
369 compatible = "nvidia,tegra20-slink";
370 reg = <0x7000d400 0x200>;
371 interrupts = <0 59 0x04>;
372 nvidia,dma-request-selector = <&apbdma 15>;
373 #address-cells = <1>;
374 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]375 clocks = <&tegra_car 41>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]376 status = "disabled";
377 };
378
379 spi@7000d600 {
380 compatible = "nvidia,tegra20-slink";
381 reg = <0x7000d600 0x200>;
382 interrupts = <0 82 0x04>;
383 nvidia,dma-request-selector = <&apbdma 16>;
384 #address-cells = <1>;
385 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]386 clocks = <&tegra_car 44>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]387 status = "disabled";
388 };
389
390 spi@7000d800 {
391 compatible = "nvidia,tegra20-slink";
392 reg = <0x7000d480 0x200>;
393 interrupts = <0 83 0x04>;
394 nvidia,dma-request-selector = <&apbdma 17>;
395 #address-cells = <1>;
396 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]397 clocks = <&tegra_car 46>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]398 status = "disabled";
399 };
400
401 spi@7000da00 {
402 compatible = "nvidia,tegra20-slink";
403 reg = <0x7000da00 0x200>;
404 interrupts = <0 93 0x04>;
405 nvidia,dma-request-selector = <&apbdma 18>;
406 #address-cells = <1>;
407 #size-cells = <0>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]408 clocks = <&tegra_car 68>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]409 status = "disabled";
410 };
411
Laxman Dewangan699ed4b2013-01-11 19:03:03 +0530[diff] [blame]412 kbc {
413 compatible = "nvidia,tegra20-kbc";
414 reg = <0x7000e200 0x100>;
415 interrupts = <0 85 0x04>;
416 clocks = <&tegra_car 36>;
417 status = "disabled";
418 };
419
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]420 pmc {
421 compatible = "nvidia,tegra20-pmc";
422 reg = <0x7000e400 0x400>;
423 };
424
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]425 memory-controller@7000f000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]426 compatible = "nvidia,tegra20-mc";
427 reg = <0x7000f000 0x024
428 0x7000f03c 0x3c4>;
429 interrupts = <0 77 0x04>;
430 };
431
Hiroshi Doyu109269e2013-01-29 10:30:30 +0200[diff] [blame^]432 iommu {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]433 compatible = "nvidia,tegra20-gart";
434 reg = <0x7000f024 0x00000018 /* controller registers */
435 0x58000000 0x02000000>; /* GART aperture */
436 };
437
Stephen Warrenbbfc33b2012-10-02 13:10:47 -0600[diff] [blame]438 memory-controller@7000f400 {
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]439 compatible = "nvidia,tegra20-emc";
440 reg = <0x7000f400 0x200>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]441 #address-cells = <1>;
442 #size-cells = <0>;
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]443 };
444
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]445 phy1: usb-phy@c5000400 {
446 compatible = "nvidia,tegra20-usb-phy";
447 reg = <0xc5000400 0x3c00>;
448 phy_type = "utmi";
449 nvidia,has-legacy-mode;
Stephen Warren540fc9d2013-01-22 17:12:25 -0700[diff] [blame]450 clocks = <&tegra_car 22>, <&tegra_car 127>;
451 clock-names = "phy", "pll_u";
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]452 };
453
454 phy2: usb-phy@c5004400 {
455 compatible = "nvidia,tegra20-usb-phy";
456 reg = <0xc5004400 0x3c00>;
457 phy_type = "ulpi";
Stephen Warren540fc9d2013-01-22 17:12:25 -0700[diff] [blame]458 clocks = <&tegra_car 94>, <&tegra_car 127>;
459 clock-names = "phy", "pll_u";
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]460 };
461
462 phy3: usb-phy@c5008400 {
463 compatible = "nvidia,tegra20-usb-phy";
464 reg = <0xc5008400 0x3C00>;
465 phy_type = "utmi";
Stephen Warren540fc9d2013-01-22 17:12:25 -0700[diff] [blame]466 clocks = <&tegra_car 22>, <&tegra_car 127>;
467 clock-names = "phy", "pll_u";
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]468 };
469
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]470 usb@c5000000 {
471 compatible = "nvidia,tegra20-ehci", "usb-ehci";
472 reg = <0xc5000000 0x4000>;
473 interrupts = <0 20 0x04>;
474 phy_type = "utmi";
475 nvidia,has-legacy-mode;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]476 clocks = <&tegra_car 22>;
Venu Byravarasub4e07472012-12-13 20:59:07 +0000[diff] [blame]477 nvidia,needs-double-reset;
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]478 nvidia,phy = <&phy1>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]479 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]480 };
481
482 usb@c5004000 {
483 compatible = "nvidia,tegra20-ehci", "usb-ehci";
484 reg = <0xc5004000 0x4000>;
485 interrupts = <0 21 0x04>;
486 phy_type = "ulpi";
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]487 clocks = <&tegra_car 58>;
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]488 nvidia,phy = <&phy2>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]489 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]490 };
491
492 usb@c5008000 {
493 compatible = "nvidia,tegra20-ehci", "usb-ehci";
494 reg = <0xc5008000 0x4000>;
495 interrupts = <0 97 0x04>;
496 phy_type = "utmi";
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]497 clocks = <&tegra_car 59>;
Venu Byravarasue374b652013-01-16 03:30:19 +0000[diff] [blame]498 nvidia,phy = <&phy3>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]499 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]500 };
501
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]502 sdhci@c8000000 {
503 compatible = "nvidia,tegra20-sdhci";
504 reg = <0xc8000000 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]505 interrupts = <0 14 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]506 clocks = <&tegra_car 14>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]507 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]508 };
509
510 sdhci@c8000200 {
511 compatible = "nvidia,tegra20-sdhci";
512 reg = <0xc8000200 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]513 interrupts = <0 15 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]514 clocks = <&tegra_car 9>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]515 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]516 };
517
518 sdhci@c8000400 {
519 compatible = "nvidia,tegra20-sdhci";
520 reg = <0xc8000400 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]521 interrupts = <0 19 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]522 clocks = <&tegra_car 69>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]523 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]524 };
525
526 sdhci@c8000600 {
527 compatible = "nvidia,tegra20-sdhci";
528 reg = <0xc8000600 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]529 interrupts = <0 31 0x04>;
Prashant Gaikwad8d8b43d2013-01-11 13:31:21 +0530[diff] [blame]530 clocks = <&tegra_car 15>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]531 status = "disabled";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]532 };
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]533
Hiroshi Doyu4dd2bd32013-01-11 15:26:55 +0200[diff] [blame]534 cpus {
535 #address-cells = <1>;
536 #size-cells = <0>;
537
538 cpu@0 {
539 device_type = "cpu";
540 compatible = "arm,cortex-a9";
541 reg = <0>;
542 };
543
544 cpu@1 {
545 device_type = "cpu";
546 compatible = "arm,cortex-a9";
547 reg = <1>;
548 };
549 };
550
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]551 pmu {
552 compatible = "arm,cortex-a9-pmu";
553 interrupts = <0 56 0x04
554 0 57 0x04>;
hdoyu@nvidia.com6a943e02012-05-09 21:45:33 +0000[diff] [blame]555 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]556};