| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* arch/arm/mach-lh7a40x/irq-lh7a400.c | 
|  | 2 | * | 
|  | 3 | *  Copyright (C) 2004 Coastal Environmental Systems | 
|  | 4 | * | 
|  | 5 | *  This program is free software; you can redistribute it and/or | 
|  | 6 | *  modify it under the terms of the GNU General Public License | 
|  | 7 | *  version 2 as published by the Free Software Foundation. | 
|  | 8 | * | 
|  | 9 | */ | 
|  | 10 |  | 
|  | 11 | #include <linux/init.h> | 
|  | 12 | #include <linux/module.h> | 
|  | 13 | #include <linux/interrupt.h> | 
|  | 14 | #include <linux/ptrace.h> | 
|  | 15 |  | 
|  | 16 | #include <asm/hardware.h> | 
|  | 17 | #include <asm/irq.h> | 
|  | 18 | #include <asm/mach/irq.h> | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | #include <asm/arch/irqs.h> | 
|  | 20 |  | 
| Russell King | 411ef7f | 2006-03-04 10:37:07 +0000 | [diff] [blame] | 21 | #include "common.h" | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 |  | 
|  | 23 | /* CPU IRQ handling */ | 
|  | 24 |  | 
|  | 25 | static void lh7a400_mask_irq (u32 irq) | 
|  | 26 | { | 
|  | 27 | INTC_INTENC = (1 << irq); | 
|  | 28 | } | 
|  | 29 |  | 
|  | 30 | static void lh7a400_unmask_irq (u32 irq) | 
|  | 31 | { | 
|  | 32 | INTC_INTENS = (1 << irq); | 
|  | 33 | } | 
|  | 34 |  | 
|  | 35 | static void lh7a400_ack_gpio_irq (u32 irq) | 
|  | 36 | { | 
|  | 37 | GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq)); | 
|  | 38 | INTC_INTENC = (1 << irq); | 
|  | 39 | } | 
|  | 40 |  | 
| David Brownell | 38c677c | 2006-08-01 22:26:25 +0100 | [diff] [blame] | 41 | static struct irq_chip lh7a400_internal_chip = { | 
|  | 42 | .name	= "MPU", | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | .ack	= lh7a400_mask_irq, /* Level triggering -> mask is ack */ | 
|  | 44 | .mask	= lh7a400_mask_irq, | 
|  | 45 | .unmask	= lh7a400_unmask_irq, | 
|  | 46 | }; | 
|  | 47 |  | 
| David Brownell | 38c677c | 2006-08-01 22:26:25 +0100 | [diff] [blame] | 48 | static struct irq_chip lh7a400_gpio_chip = { | 
|  | 49 | .name	= "GPIO", | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | .ack	= lh7a400_ack_gpio_irq, | 
|  | 51 | .mask	= lh7a400_mask_irq, | 
|  | 52 | .unmask	= lh7a400_unmask_irq, | 
|  | 53 | }; | 
|  | 54 |  | 
|  | 55 |  | 
|  | 56 | /* IRQ initialization */ | 
|  | 57 |  | 
|  | 58 | void __init lh7a400_init_irq (void) | 
|  | 59 | { | 
|  | 60 | int irq; | 
|  | 61 |  | 
|  | 62 | INTC_INTENC = 0xffffffff;	/* Disable all interrupts */ | 
|  | 63 | GPIO_GPIOFINTEN = 0x00;		/* Disable all GPIOF interrupts */ | 
|  | 64 | barrier (); | 
|  | 65 |  | 
|  | 66 | for (irq = 0; irq < NR_IRQS; ++irq) { | 
|  | 67 | switch (irq) { | 
|  | 68 | case IRQ_GPIO0INTR: | 
|  | 69 | case IRQ_GPIO1INTR: | 
|  | 70 | case IRQ_GPIO2INTR: | 
|  | 71 | case IRQ_GPIO3INTR: | 
|  | 72 | case IRQ_GPIO4INTR: | 
|  | 73 | case IRQ_GPIO5INTR: | 
|  | 74 | case IRQ_GPIO6INTR: | 
|  | 75 | case IRQ_GPIO7INTR: | 
|  | 76 | set_irq_chip (irq, &lh7a400_gpio_chip); | 
| Russell King | 10dd5ce | 2006-11-23 11:41:32 +0000 | [diff] [blame^] | 77 | set_irq_handler (irq, handle_level_irq); /* OK default */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 78 | break; | 
|  | 79 | default: | 
|  | 80 | set_irq_chip (irq, &lh7a400_internal_chip); | 
| Russell King | 10dd5ce | 2006-11-23 11:41:32 +0000 | [diff] [blame^] | 81 | set_irq_handler (irq, handle_level_irq); | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 82 | } | 
|  | 83 | set_irq_flags (irq, IRQF_VALID); | 
|  | 84 | } | 
|  | 85 |  | 
|  | 86 | lh7a40x_init_board_irq (); | 
|  | 87 |  | 
|  | 88 | /* *** FIXME: the LH7a400 does use FIQ interrupts in some cases.  For | 
|  | 89 | the time being, these are not initialized. */ | 
|  | 90 |  | 
|  | 91 | /*	init_FIQ(); */ | 
|  | 92 | } |