Gitiles
Code Review Sign In
review.evervolv.com / android_kernel_oneplus_msm8996 / 112b51cfa21714d001e5b3e3f7c1f13146906a5d / . / arch / mips / ath79 / common.c
blob: 5a4adfc9d79dc3b3fe891456530ff88e20c5ff90 [file] [log] [blame]
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100[diff] [blame]1/*
2 * Atheros AR71XX/AR724X/AR913X common routines
3 *
Gabor Juhos42184762012-03-14 10:45:26 +0100[diff] [blame]4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100[diff] [blame]6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
Gabor Juhos42184762012-03-14 10:45:26 +0100[diff] [blame]8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
9 *
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100[diff] [blame]10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/types.h>
18#include <linux/spinlock.h>
19
20#include <asm/mach-ath79/ath79.h>
21#include <asm/mach-ath79/ar71xx_regs.h>
22#include "common.h"
23
24static DEFINE_SPINLOCK(ath79_device_reset_lock);
25
26u32 ath79_cpu_freq;
27EXPORT_SYMBOL_GPL(ath79_cpu_freq);
28
29u32 ath79_ahb_freq;
30EXPORT_SYMBOL_GPL(ath79_ahb_freq);
31
32u32 ath79_ddr_freq;
33EXPORT_SYMBOL_GPL(ath79_ddr_freq);
34
35enum ath79_soc_type ath79_soc;
Gabor Juhosbe5f3622011-11-18 00:17:46 +0000[diff] [blame]36unsigned int ath79_soc_rev;
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100[diff] [blame]37
38void __iomem *ath79_pll_base;
39void __iomem *ath79_reset_base;
40EXPORT_SYMBOL_GPL(ath79_reset_base);
41void __iomem *ath79_ddr_base;
42
43void ath79_ddr_wb_flush(u32 reg)
44{
45 void __iomem *flush_reg = ath79_ddr_base + reg;
46
47 /* Flush the DDR write buffer. */
48 __raw_writel(0x1, flush_reg);
49 while (__raw_readl(flush_reg) & 0x1)
50 ;
51
52 /* It must be run twice. */
53 __raw_writel(0x1, flush_reg);
54 while (__raw_readl(flush_reg) & 0x1)
55 ;
56}
57EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush);
58
59void ath79_device_reset_set(u32 mask)
60{
61 unsigned long flags;
62 u32 reg;
63 u32 t;
64
65 if (soc_is_ar71xx())
66 reg = AR71XX_RESET_REG_RESET_MODULE;
67 else if (soc_is_ar724x())
68 reg = AR724X_RESET_REG_RESET_MODULE;
69 else if (soc_is_ar913x())
70 reg = AR913X_RESET_REG_RESET_MODULE;
Gabor Juhos7ee15d82011-06-20 21:26:05 +0200[diff] [blame]71 else if (soc_is_ar933x())
72 reg = AR933X_RESET_REG_RESET_MODULE;
Gabor Juhos42184762012-03-14 10:45:26 +0100[diff] [blame]73 else if (soc_is_ar934x())
74 reg = AR934X_RESET_REG_RESET_MODULE;
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100[diff] [blame]75 else
76 BUG();
77
78 spin_lock_irqsave(&ath79_device_reset_lock, flags);
79 t = ath79_reset_rr(reg);
80 ath79_reset_wr(reg, t | mask);
81 spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
82}
83EXPORT_SYMBOL_GPL(ath79_device_reset_set);
84
85void ath79_device_reset_clear(u32 mask)
86{
87 unsigned long flags;
88 u32 reg;
89 u32 t;
90
91 if (soc_is_ar71xx())
92 reg = AR71XX_RESET_REG_RESET_MODULE;
93 else if (soc_is_ar724x())
94 reg = AR724X_RESET_REG_RESET_MODULE;
95 else if (soc_is_ar913x())
96 reg = AR913X_RESET_REG_RESET_MODULE;
Gabor Juhos7ee15d82011-06-20 21:26:05 +0200[diff] [blame]97 else if (soc_is_ar933x())
98 reg = AR933X_RESET_REG_RESET_MODULE;
Gabor Juhos42184762012-03-14 10:45:26 +0100[diff] [blame]99 else if (soc_is_ar934x())
100 reg = AR934X_RESET_REG_RESET_MODULE;
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100[diff] [blame]101 else
102 BUG();
103
104 spin_lock_irqsave(&ath79_device_reset_lock, flags);
105 t = ath79_reset_rr(reg);
106 ath79_reset_wr(reg, t & ~mask);
107 spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
108}
109EXPORT_SYMBOL_GPL(ath79_device_reset_clear);