| Mark Brown | 73b34ea | 2010-03-15 17:46:02 +0000 | [diff] [blame] | 1 | /* |
| 2 | * linux/sound/wm8903.h -- Platform data for WM8903 |
| 3 | * |
| 4 | * Copyright 2010 Wolfson Microelectronics. PLC. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #ifndef __LINUX_SND_WM8903_H |
| 12 | #define __LINUX_SND_WM8903_H |
| 13 | |
| 14 | /* Used to enable configuration of a GPIO to all zeros */ |
| 15 | #define WM8903_GPIO_NO_CONFIG 0x8000 |
| 16 | |
| 17 | /* |
| Mark Brown | 37f88e8 | 2010-03-15 18:14:34 +0000 | [diff] [blame] | 18 | * R6 (0x06) - Mic Bias Control 0 |
| 19 | */ |
| 20 | #define WM8903_MICDET_HYST_ENA 0x0080 /* MICDET_HYST_ENA */ |
| 21 | #define WM8903_MICDET_HYST_ENA_MASK 0x0080 /* MICDET_HYST_ENA */ |
| 22 | #define WM8903_MICDET_HYST_ENA_SHIFT 7 /* MICDET_HYST_ENA */ |
| 23 | #define WM8903_MICDET_HYST_ENA_WIDTH 1 /* MICDET_HYST_ENA */ |
| 24 | #define WM8903_MICDET_THR_MASK 0x0070 /* MICDET_THR - [6:4] */ |
| 25 | #define WM8903_MICDET_THR_SHIFT 4 /* MICDET_THR - [6:4] */ |
| 26 | #define WM8903_MICDET_THR_WIDTH 3 /* MICDET_THR - [6:4] */ |
| 27 | #define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */ |
| 28 | #define WM8903_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */ |
| 29 | #define WM8903_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */ |
| 30 | #define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */ |
| 31 | #define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */ |
| 32 | #define WM8903_MICDET_ENA_SHIFT 1 /* MICDET_ENA */ |
| 33 | #define WM8903_MICDET_ENA_WIDTH 1 /* MICDET_ENA */ |
| 34 | #define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */ |
| 35 | #define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */ |
| 36 | #define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */ |
| 37 | #define WM8903_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */ |
| 38 | |
| 39 | /* |
| Mark Brown | 73b34ea | 2010-03-15 17:46:02 +0000 | [diff] [blame] | 40 | * R116 (0x74) - GPIO Control 1 |
| 41 | */ |
| 42 | #define WM8903_GP1_FN_MASK 0x1F00 /* GP1_FN - [12:8] */ |
| 43 | #define WM8903_GP1_FN_SHIFT 8 /* GP1_FN - [12:8] */ |
| 44 | #define WM8903_GP1_FN_WIDTH 5 /* GP1_FN - [12:8] */ |
| 45 | #define WM8903_GP1_DIR 0x0080 /* GP1_DIR */ |
| 46 | #define WM8903_GP1_DIR_MASK 0x0080 /* GP1_DIR */ |
| 47 | #define WM8903_GP1_DIR_SHIFT 7 /* GP1_DIR */ |
| 48 | #define WM8903_GP1_DIR_WIDTH 1 /* GP1_DIR */ |
| 49 | #define WM8903_GP1_OP_CFG 0x0040 /* GP1_OP_CFG */ |
| 50 | #define WM8903_GP1_OP_CFG_MASK 0x0040 /* GP1_OP_CFG */ |
| 51 | #define WM8903_GP1_OP_CFG_SHIFT 6 /* GP1_OP_CFG */ |
| 52 | #define WM8903_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ |
| 53 | #define WM8903_GP1_IP_CFG 0x0020 /* GP1_IP_CFG */ |
| 54 | #define WM8903_GP1_IP_CFG_MASK 0x0020 /* GP1_IP_CFG */ |
| 55 | #define WM8903_GP1_IP_CFG_SHIFT 5 /* GP1_IP_CFG */ |
| 56 | #define WM8903_GP1_IP_CFG_WIDTH 1 /* GP1_IP_CFG */ |
| 57 | #define WM8903_GP1_LVL 0x0010 /* GP1_LVL */ |
| 58 | #define WM8903_GP1_LVL_MASK 0x0010 /* GP1_LVL */ |
| 59 | #define WM8903_GP1_LVL_SHIFT 4 /* GP1_LVL */ |
| 60 | #define WM8903_GP1_LVL_WIDTH 1 /* GP1_LVL */ |
| 61 | #define WM8903_GP1_PD 0x0008 /* GP1_PD */ |
| 62 | #define WM8903_GP1_PD_MASK 0x0008 /* GP1_PD */ |
| 63 | #define WM8903_GP1_PD_SHIFT 3 /* GP1_PD */ |
| 64 | #define WM8903_GP1_PD_WIDTH 1 /* GP1_PD */ |
| 65 | #define WM8903_GP1_PU 0x0004 /* GP1_PU */ |
| 66 | #define WM8903_GP1_PU_MASK 0x0004 /* GP1_PU */ |
| 67 | #define WM8903_GP1_PU_SHIFT 2 /* GP1_PU */ |
| 68 | #define WM8903_GP1_PU_WIDTH 1 /* GP1_PU */ |
| 69 | #define WM8903_GP1_INTMODE 0x0002 /* GP1_INTMODE */ |
| 70 | #define WM8903_GP1_INTMODE_MASK 0x0002 /* GP1_INTMODE */ |
| 71 | #define WM8903_GP1_INTMODE_SHIFT 1 /* GP1_INTMODE */ |
| 72 | #define WM8903_GP1_INTMODE_WIDTH 1 /* GP1_INTMODE */ |
| 73 | #define WM8903_GP1_DB 0x0001 /* GP1_DB */ |
| 74 | #define WM8903_GP1_DB_MASK 0x0001 /* GP1_DB */ |
| 75 | #define WM8903_GP1_DB_SHIFT 0 /* GP1_DB */ |
| 76 | #define WM8903_GP1_DB_WIDTH 1 /* GP1_DB */ |
| 77 | |
| 78 | /* |
| 79 | * R117 (0x75) - GPIO Control 2 |
| 80 | */ |
| 81 | #define WM8903_GP2_FN_MASK 0x1F00 /* GP2_FN - [12:8] */ |
| 82 | #define WM8903_GP2_FN_SHIFT 8 /* GP2_FN - [12:8] */ |
| 83 | #define WM8903_GP2_FN_WIDTH 5 /* GP2_FN - [12:8] */ |
| 84 | #define WM8903_GP2_DIR 0x0080 /* GP2_DIR */ |
| 85 | #define WM8903_GP2_DIR_MASK 0x0080 /* GP2_DIR */ |
| 86 | #define WM8903_GP2_DIR_SHIFT 7 /* GP2_DIR */ |
| 87 | #define WM8903_GP2_DIR_WIDTH 1 /* GP2_DIR */ |
| 88 | #define WM8903_GP2_OP_CFG 0x0040 /* GP2_OP_CFG */ |
| 89 | #define WM8903_GP2_OP_CFG_MASK 0x0040 /* GP2_OP_CFG */ |
| 90 | #define WM8903_GP2_OP_CFG_SHIFT 6 /* GP2_OP_CFG */ |
| 91 | #define WM8903_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ |
| 92 | #define WM8903_GP2_IP_CFG 0x0020 /* GP2_IP_CFG */ |
| 93 | #define WM8903_GP2_IP_CFG_MASK 0x0020 /* GP2_IP_CFG */ |
| 94 | #define WM8903_GP2_IP_CFG_SHIFT 5 /* GP2_IP_CFG */ |
| 95 | #define WM8903_GP2_IP_CFG_WIDTH 1 /* GP2_IP_CFG */ |
| 96 | #define WM8903_GP2_LVL 0x0010 /* GP2_LVL */ |
| 97 | #define WM8903_GP2_LVL_MASK 0x0010 /* GP2_LVL */ |
| 98 | #define WM8903_GP2_LVL_SHIFT 4 /* GP2_LVL */ |
| 99 | #define WM8903_GP2_LVL_WIDTH 1 /* GP2_LVL */ |
| 100 | #define WM8903_GP2_PD 0x0008 /* GP2_PD */ |
| 101 | #define WM8903_GP2_PD_MASK 0x0008 /* GP2_PD */ |
| 102 | #define WM8903_GP2_PD_SHIFT 3 /* GP2_PD */ |
| 103 | #define WM8903_GP2_PD_WIDTH 1 /* GP2_PD */ |
| 104 | #define WM8903_GP2_PU 0x0004 /* GP2_PU */ |
| 105 | #define WM8903_GP2_PU_MASK 0x0004 /* GP2_PU */ |
| 106 | #define WM8903_GP2_PU_SHIFT 2 /* GP2_PU */ |
| 107 | #define WM8903_GP2_PU_WIDTH 1 /* GP2_PU */ |
| 108 | #define WM8903_GP2_INTMODE 0x0002 /* GP2_INTMODE */ |
| 109 | #define WM8903_GP2_INTMODE_MASK 0x0002 /* GP2_INTMODE */ |
| 110 | #define WM8903_GP2_INTMODE_SHIFT 1 /* GP2_INTMODE */ |
| 111 | #define WM8903_GP2_INTMODE_WIDTH 1 /* GP2_INTMODE */ |
| 112 | #define WM8903_GP2_DB 0x0001 /* GP2_DB */ |
| 113 | #define WM8903_GP2_DB_MASK 0x0001 /* GP2_DB */ |
| 114 | #define WM8903_GP2_DB_SHIFT 0 /* GP2_DB */ |
| 115 | #define WM8903_GP2_DB_WIDTH 1 /* GP2_DB */ |
| 116 | |
| 117 | /* |
| 118 | * R118 (0x76) - GPIO Control 3 |
| 119 | */ |
| 120 | #define WM8903_GP3_FN_MASK 0x1F00 /* GP3_FN - [12:8] */ |
| 121 | #define WM8903_GP3_FN_SHIFT 8 /* GP3_FN - [12:8] */ |
| 122 | #define WM8903_GP3_FN_WIDTH 5 /* GP3_FN - [12:8] */ |
| 123 | #define WM8903_GP3_DIR 0x0080 /* GP3_DIR */ |
| 124 | #define WM8903_GP3_DIR_MASK 0x0080 /* GP3_DIR */ |
| 125 | #define WM8903_GP3_DIR_SHIFT 7 /* GP3_DIR */ |
| 126 | #define WM8903_GP3_DIR_WIDTH 1 /* GP3_DIR */ |
| 127 | #define WM8903_GP3_OP_CFG 0x0040 /* GP3_OP_CFG */ |
| 128 | #define WM8903_GP3_OP_CFG_MASK 0x0040 /* GP3_OP_CFG */ |
| 129 | #define WM8903_GP3_OP_CFG_SHIFT 6 /* GP3_OP_CFG */ |
| 130 | #define WM8903_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ |
| 131 | #define WM8903_GP3_IP_CFG 0x0020 /* GP3_IP_CFG */ |
| 132 | #define WM8903_GP3_IP_CFG_MASK 0x0020 /* GP3_IP_CFG */ |
| 133 | #define WM8903_GP3_IP_CFG_SHIFT 5 /* GP3_IP_CFG */ |
| 134 | #define WM8903_GP3_IP_CFG_WIDTH 1 /* GP3_IP_CFG */ |
| 135 | #define WM8903_GP3_LVL 0x0010 /* GP3_LVL */ |
| 136 | #define WM8903_GP3_LVL_MASK 0x0010 /* GP3_LVL */ |
| 137 | #define WM8903_GP3_LVL_SHIFT 4 /* GP3_LVL */ |
| 138 | #define WM8903_GP3_LVL_WIDTH 1 /* GP3_LVL */ |
| 139 | #define WM8903_GP3_PD 0x0008 /* GP3_PD */ |
| 140 | #define WM8903_GP3_PD_MASK 0x0008 /* GP3_PD */ |
| 141 | #define WM8903_GP3_PD_SHIFT 3 /* GP3_PD */ |
| 142 | #define WM8903_GP3_PD_WIDTH 1 /* GP3_PD */ |
| 143 | #define WM8903_GP3_PU 0x0004 /* GP3_PU */ |
| 144 | #define WM8903_GP3_PU_MASK 0x0004 /* GP3_PU */ |
| 145 | #define WM8903_GP3_PU_SHIFT 2 /* GP3_PU */ |
| 146 | #define WM8903_GP3_PU_WIDTH 1 /* GP3_PU */ |
| 147 | #define WM8903_GP3_INTMODE 0x0002 /* GP3_INTMODE */ |
| 148 | #define WM8903_GP3_INTMODE_MASK 0x0002 /* GP3_INTMODE */ |
| 149 | #define WM8903_GP3_INTMODE_SHIFT 1 /* GP3_INTMODE */ |
| 150 | #define WM8903_GP3_INTMODE_WIDTH 1 /* GP3_INTMODE */ |
| 151 | #define WM8903_GP3_DB 0x0001 /* GP3_DB */ |
| 152 | #define WM8903_GP3_DB_MASK 0x0001 /* GP3_DB */ |
| 153 | #define WM8903_GP3_DB_SHIFT 0 /* GP3_DB */ |
| 154 | #define WM8903_GP3_DB_WIDTH 1 /* GP3_DB */ |
| 155 | |
| 156 | /* |
| 157 | * R119 (0x77) - GPIO Control 4 |
| 158 | */ |
| 159 | #define WM8903_GP4_FN_MASK 0x1F00 /* GP4_FN - [12:8] */ |
| 160 | #define WM8903_GP4_FN_SHIFT 8 /* GP4_FN - [12:8] */ |
| 161 | #define WM8903_GP4_FN_WIDTH 5 /* GP4_FN - [12:8] */ |
| 162 | #define WM8903_GP4_DIR 0x0080 /* GP4_DIR */ |
| 163 | #define WM8903_GP4_DIR_MASK 0x0080 /* GP4_DIR */ |
| 164 | #define WM8903_GP4_DIR_SHIFT 7 /* GP4_DIR */ |
| 165 | #define WM8903_GP4_DIR_WIDTH 1 /* GP4_DIR */ |
| 166 | #define WM8903_GP4_OP_CFG 0x0040 /* GP4_OP_CFG */ |
| 167 | #define WM8903_GP4_OP_CFG_MASK 0x0040 /* GP4_OP_CFG */ |
| 168 | #define WM8903_GP4_OP_CFG_SHIFT 6 /* GP4_OP_CFG */ |
| 169 | #define WM8903_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ |
| 170 | #define WM8903_GP4_IP_CFG 0x0020 /* GP4_IP_CFG */ |
| 171 | #define WM8903_GP4_IP_CFG_MASK 0x0020 /* GP4_IP_CFG */ |
| 172 | #define WM8903_GP4_IP_CFG_SHIFT 5 /* GP4_IP_CFG */ |
| 173 | #define WM8903_GP4_IP_CFG_WIDTH 1 /* GP4_IP_CFG */ |
| 174 | #define WM8903_GP4_LVL 0x0010 /* GP4_LVL */ |
| 175 | #define WM8903_GP4_LVL_MASK 0x0010 /* GP4_LVL */ |
| 176 | #define WM8903_GP4_LVL_SHIFT 4 /* GP4_LVL */ |
| 177 | #define WM8903_GP4_LVL_WIDTH 1 /* GP4_LVL */ |
| 178 | #define WM8903_GP4_PD 0x0008 /* GP4_PD */ |
| 179 | #define WM8903_GP4_PD_MASK 0x0008 /* GP4_PD */ |
| 180 | #define WM8903_GP4_PD_SHIFT 3 /* GP4_PD */ |
| 181 | #define WM8903_GP4_PD_WIDTH 1 /* GP4_PD */ |
| 182 | #define WM8903_GP4_PU 0x0004 /* GP4_PU */ |
| 183 | #define WM8903_GP4_PU_MASK 0x0004 /* GP4_PU */ |
| 184 | #define WM8903_GP4_PU_SHIFT 2 /* GP4_PU */ |
| 185 | #define WM8903_GP4_PU_WIDTH 1 /* GP4_PU */ |
| 186 | #define WM8903_GP4_INTMODE 0x0002 /* GP4_INTMODE */ |
| 187 | #define WM8903_GP4_INTMODE_MASK 0x0002 /* GP4_INTMODE */ |
| 188 | #define WM8903_GP4_INTMODE_SHIFT 1 /* GP4_INTMODE */ |
| 189 | #define WM8903_GP4_INTMODE_WIDTH 1 /* GP4_INTMODE */ |
| 190 | #define WM8903_GP4_DB 0x0001 /* GP4_DB */ |
| 191 | #define WM8903_GP4_DB_MASK 0x0001 /* GP4_DB */ |
| 192 | #define WM8903_GP4_DB_SHIFT 0 /* GP4_DB */ |
| 193 | #define WM8903_GP4_DB_WIDTH 1 /* GP4_DB */ |
| 194 | |
| 195 | /* |
| 196 | * R120 (0x78) - GPIO Control 5 |
| 197 | */ |
| 198 | #define WM8903_GP5_FN_MASK 0x1F00 /* GP5_FN - [12:8] */ |
| 199 | #define WM8903_GP5_FN_SHIFT 8 /* GP5_FN - [12:8] */ |
| 200 | #define WM8903_GP5_FN_WIDTH 5 /* GP5_FN - [12:8] */ |
| 201 | #define WM8903_GP5_DIR 0x0080 /* GP5_DIR */ |
| 202 | #define WM8903_GP5_DIR_MASK 0x0080 /* GP5_DIR */ |
| 203 | #define WM8903_GP5_DIR_SHIFT 7 /* GP5_DIR */ |
| 204 | #define WM8903_GP5_DIR_WIDTH 1 /* GP5_DIR */ |
| 205 | #define WM8903_GP5_OP_CFG 0x0040 /* GP5_OP_CFG */ |
| 206 | #define WM8903_GP5_OP_CFG_MASK 0x0040 /* GP5_OP_CFG */ |
| 207 | #define WM8903_GP5_OP_CFG_SHIFT 6 /* GP5_OP_CFG */ |
| 208 | #define WM8903_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ |
| 209 | #define WM8903_GP5_IP_CFG 0x0020 /* GP5_IP_CFG */ |
| 210 | #define WM8903_GP5_IP_CFG_MASK 0x0020 /* GP5_IP_CFG */ |
| 211 | #define WM8903_GP5_IP_CFG_SHIFT 5 /* GP5_IP_CFG */ |
| 212 | #define WM8903_GP5_IP_CFG_WIDTH 1 /* GP5_IP_CFG */ |
| 213 | #define WM8903_GP5_LVL 0x0010 /* GP5_LVL */ |
| 214 | #define WM8903_GP5_LVL_MASK 0x0010 /* GP5_LVL */ |
| 215 | #define WM8903_GP5_LVL_SHIFT 4 /* GP5_LVL */ |
| 216 | #define WM8903_GP5_LVL_WIDTH 1 /* GP5_LVL */ |
| 217 | #define WM8903_GP5_PD 0x0008 /* GP5_PD */ |
| 218 | #define WM8903_GP5_PD_MASK 0x0008 /* GP5_PD */ |
| 219 | #define WM8903_GP5_PD_SHIFT 3 /* GP5_PD */ |
| 220 | #define WM8903_GP5_PD_WIDTH 1 /* GP5_PD */ |
| 221 | #define WM8903_GP5_PU 0x0004 /* GP5_PU */ |
| 222 | #define WM8903_GP5_PU_MASK 0x0004 /* GP5_PU */ |
| 223 | #define WM8903_GP5_PU_SHIFT 2 /* GP5_PU */ |
| 224 | #define WM8903_GP5_PU_WIDTH 1 /* GP5_PU */ |
| 225 | #define WM8903_GP5_INTMODE 0x0002 /* GP5_INTMODE */ |
| 226 | #define WM8903_GP5_INTMODE_MASK 0x0002 /* GP5_INTMODE */ |
| 227 | #define WM8903_GP5_INTMODE_SHIFT 1 /* GP5_INTMODE */ |
| 228 | #define WM8903_GP5_INTMODE_WIDTH 1 /* GP5_INTMODE */ |
| 229 | #define WM8903_GP5_DB 0x0001 /* GP5_DB */ |
| 230 | #define WM8903_GP5_DB_MASK 0x0001 /* GP5_DB */ |
| 231 | #define WM8903_GP5_DB_SHIFT 0 /* GP5_DB */ |
| 232 | #define WM8903_GP5_DB_WIDTH 1 /* GP5_DB */ |
| 233 | |
| 234 | struct wm8903_platform_data { |
| Mark Brown | 8abd16a | 2010-03-15 18:25:26 +0000 | [diff] [blame] | 235 | bool irq_active_low; /* Set if IRQ active low, default high */ |
| 236 | |
| Mark Brown | 37f88e8 | 2010-03-15 18:14:34 +0000 | [diff] [blame] | 237 | /* Default register value for R6 (Mic bias), used to configure |
| 238 | * microphone detection. In conjunction with gpio_cfg this |
| 239 | * can be used to route the microphone status signals out onto |
| 240 | * the GPIOs for use with snd_soc_jack_add_gpios(). |
| 241 | */ |
| 242 | u16 micdet_cfg; |
| 243 | |
| Mark Brown | 7245387 | 2010-03-15 21:22:58 +0000 | [diff] [blame] | 244 | int micdet_delay; /* Delay after microphone detection (ms) */ |
| 245 | |
| Mark Brown | 73b34ea | 2010-03-15 17:46:02 +0000 | [diff] [blame] | 246 | u32 gpio_cfg[5]; /* Default register values for GPIO pin mux */ |
| 247 | }; |
| 248 | |
| 249 | #endif |