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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/kernel/entry-armv.S
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
Hyok S. Choiafeb90c2006-01-13 21:05:25 +00006 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Low-level vector interface routines
13 *
Nicolas Pitre70b6f2b2007-12-04 14:33:33 +010014 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
Linus Torvalds1da177e2005-04-16 15:20:36 -070016 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070017
Nicolas Pitref09b9972005-10-29 21:44:55 +010018#include <asm/memory.h>
Russell King753790e2011-02-06 15:32:24 +000019#include <asm/glue-df.h>
20#include <asm/glue-pf.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <asm/vfpmacros.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010022#include <mach/entry-macro.S>
Russell Kingd6551e82006-06-21 13:31:52 +010023#include <asm/thread_notify.h>
Catalin Marinasc4c57162009-02-16 11:42:09 +010024#include <asm/unwind.h>
Russell Kingcc20d422009-11-09 23:53:29 +000025#include <asm/unistd.h>
Tony Lindgrenf159f4e2010-07-05 14:53:10 +010026#include <asm/tls.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027
28#include "entry-header.S"
Magnus Dammcd544ce2010-12-22 13:20:08 +010029#include <asm/entry-macro-multi.S>
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
31/*
Russell King187a51a2005-05-21 18:14:44 +010032 * Interrupt handling. Preserves r7, r8, r9
33 */
34 .macro irq_handler
eric miao52108642010-12-13 09:42:34 +010035#ifdef CONFIG_MULTI_IRQ_HANDLER
36 ldr r5, =handle_arch_irq
37 mov r0, sp
38 ldr r5, [r5]
39 adr lr, BSYM(9997f)
40 teq r5, #0
41 movne pc, r5
Russell King37ee16a2005-11-08 19:08:05 +000042#endif
Magnus Dammcd544ce2010-12-22 13:20:08 +010043 arch_irq_handler_default
Russell Kingf00ec482010-09-04 10:47:48 +0100449997:
Russell King187a51a2005-05-21 18:14:44 +010045 .endm
46
Russell Kingac8b9c12011-06-26 10:22:08 +010047 .macro pabt_helper
48 mov r0, r2 @ pass address of aborted instruction.
49#ifdef MULTI_PABORT
Russell King0402bec2011-06-25 15:46:08 +010050 ldr ip, .LCprocfns
Russell Kingac8b9c12011-06-26 10:22:08 +010051 mov lr, pc
Russell King0402bec2011-06-25 15:46:08 +010052 ldr pc, [ip, #PROCESSOR_PABT_FUNC]
Russell Kingac8b9c12011-06-26 10:22:08 +010053#else
54 bl CPU_PABORT_HANDLER
55#endif
56 .endm
57
58 .macro dabt_helper
59
60 @
61 @ Call the processor-specific abort handler:
62 @
63 @ r2 - aborted context pc
64 @ r3 - aborted context cpsr
65 @
66 @ The abort handler must return the aborted address in r0, and
67 @ the fault status register in r1. r9 must be preserved.
68 @
69#ifdef MULTI_DABORT
Russell King0402bec2011-06-25 15:46:08 +010070 ldr ip, .LCprocfns
Russell Kingac8b9c12011-06-26 10:22:08 +010071 mov lr, pc
Russell King0402bec2011-06-25 15:46:08 +010072 ldr pc, [ip, #PROCESSOR_DABT_FUNC]
Russell Kingac8b9c12011-06-26 10:22:08 +010073#else
74 bl CPU_DABORT_HANDLER
75#endif
76 .endm
77
Nicolas Pitre785d3cd2007-12-03 15:27:56 -050078#ifdef CONFIG_KPROBES
79 .section .kprobes.text,"ax",%progbits
80#else
81 .text
82#endif
83
Russell King187a51a2005-05-21 18:14:44 +010084/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070085 * Invalid mode handlers
86 */
Russell Kingccea7a12005-05-31 22:22:32 +010087 .macro inv_entry, reason
88 sub sp, sp, #S_FRAME_SIZE
Catalin Marinasb86040a2009-07-24 12:32:54 +010089 ARM( stmib sp, {r1 - lr} )
90 THUMB( stmia sp, {r0 - r12} )
91 THUMB( str sp, [sp, #S_SP] )
92 THUMB( str lr, [sp, #S_LR] )
Linus Torvalds1da177e2005-04-16 15:20:36 -070093 mov r1, #\reason
94 .endm
95
96__pabt_invalid:
Russell Kingccea7a12005-05-31 22:22:32 +010097 inv_entry BAD_PREFETCH
98 b common_invalid
Catalin Marinas93ed3972008-08-28 11:22:32 +010099ENDPROC(__pabt_invalid)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100
101__dabt_invalid:
Russell Kingccea7a12005-05-31 22:22:32 +0100102 inv_entry BAD_DATA
103 b common_invalid
Catalin Marinas93ed3972008-08-28 11:22:32 +0100104ENDPROC(__dabt_invalid)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105
106__irq_invalid:
Russell Kingccea7a12005-05-31 22:22:32 +0100107 inv_entry BAD_IRQ
108 b common_invalid
Catalin Marinas93ed3972008-08-28 11:22:32 +0100109ENDPROC(__irq_invalid)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110
111__und_invalid:
Russell Kingccea7a12005-05-31 22:22:32 +0100112 inv_entry BAD_UNDEFINSTR
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113
Russell Kingccea7a12005-05-31 22:22:32 +0100114 @
115 @ XXX fall through to common_invalid
116 @
117
118@
119@ common_invalid - generic code for failed exception (re-entrant version of handlers)
120@
121common_invalid:
122 zero_fp
123
124 ldmia r0, {r4 - r6}
125 add r0, sp, #S_PC @ here for interlock avoidance
126 mov r7, #-1 @ "" "" "" ""
127 str r4, [sp] @ save preserved r0
128 stmia r0, {r5 - r7} @ lr_<exception>,
129 @ cpsr_<exception>, "old_r0"
130
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131 mov r0, sp
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132 b bad_mode
Catalin Marinas93ed3972008-08-28 11:22:32 +0100133ENDPROC(__und_invalid)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134
135/*
136 * SVC mode handlers
137 */
Nicolas Pitre2dede2d2006-01-14 16:18:08 +0000138
139#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
140#define SPFIX(code...) code
141#else
142#define SPFIX(code...)
143#endif
144
Nicolas Pitred30a0c82007-12-14 15:56:01 -0500145 .macro svc_entry, stack_hole=0
Catalin Marinasc4c57162009-02-16 11:42:09 +0100146 UNWIND(.fnstart )
147 UNWIND(.save {r0 - pc} )
Catalin Marinasb86040a2009-07-24 12:32:54 +0100148 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
149#ifdef CONFIG_THUMB2_KERNEL
150 SPFIX( str r0, [sp] ) @ temporarily saved
151 SPFIX( mov r0, sp )
152 SPFIX( tst r0, #4 ) @ test original stack alignment
153 SPFIX( ldr r0, [sp] ) @ restored
154#else
Nicolas Pitre2dede2d2006-01-14 16:18:08 +0000155 SPFIX( tst sp, #4 )
Catalin Marinasb86040a2009-07-24 12:32:54 +0100156#endif
157 SPFIX( subeq sp, sp, #4 )
158 stmia sp, {r1 - r12}
Russell Kingccea7a12005-05-31 22:22:32 +0100159
160 ldmia r0, {r1 - r3}
Catalin Marinasb86040a2009-07-24 12:32:54 +0100161 add r5, sp, #S_SP - 4 @ here for interlock avoidance
Russell Kingccea7a12005-05-31 22:22:32 +0100162 mov r4, #-1 @ "" "" "" ""
Catalin Marinasb86040a2009-07-24 12:32:54 +0100163 add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
164 SPFIX( addeq r0, r0, #4 )
165 str r1, [sp, #-4]! @ save the "real" r0 copied
Russell Kingccea7a12005-05-31 22:22:32 +0100166 @ from the exception stack
167
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168 mov r1, lr
169
170 @
171 @ We are now ready to fill in the remaining blanks on the stack:
172 @
173 @ r0 - sp_svc
174 @ r1 - lr_svc
175 @ r2 - lr_<exception>, already fixed up for correct return/restart
176 @ r3 - spsr_<exception>
177 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
178 @
179 stmia r5, {r0 - r4}
180 .endm
181
182 .align 5
183__dabt_svc:
Russell Kingccea7a12005-05-31 22:22:32 +0100184 svc_entry
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185
186 @
187 @ get ready to re-enable interrupts if appropriate
188 @
189 mrs r9, cpsr
190 tst r3, #PSR_I_BIT
191 biceq r9, r9, #PSR_I_BIT
192
Russell Kingac8b9c12011-06-26 10:22:08 +0100193 dabt_helper
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194
195 @
196 @ set desired IRQ state, then call main handler
197 @
Will Deacon7e202692010-11-28 14:57:24 +0000198 debug_entry r1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199 msr cpsr_c, r9
200 mov r2, sp
201 bl do_DataAbort
202
203 @
204 @ IRQs off again before pulling preserved data off the stack
205 @
Russell Kingac788842010-07-10 10:10:18 +0100206 disable_irq_notrace
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207
208 @
209 @ restore SPSR and restart the instruction
210 @
Catalin Marinasb86040a2009-07-24 12:32:54 +0100211 ldr r2, [sp, #S_PSR]
212 svc_exit r2 @ return from exception
Catalin Marinasc4c57162009-02-16 11:42:09 +0100213 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100214ENDPROC(__dabt_svc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215
216 .align 5
217__irq_svc:
Russell Kingccea7a12005-05-31 22:22:32 +0100218 svc_entry
219
Russell Kingac788842010-07-10 10:10:18 +0100220#ifdef CONFIG_TRACE_IRQFLAGS
221 bl trace_hardirqs_off
222#endif
Russell King1613cc12011-06-25 10:57:57 +0100223
224 irq_handler
225
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226#ifdef CONFIG_PREEMPT
Russell King706fdd92005-05-21 18:15:45 +0100227 get_thread_info tsk
228 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
Russell King706fdd92005-05-21 18:15:45 +0100229 ldr r0, [tsk, #TI_FLAGS] @ get flags
Russell King28fab1a2008-04-13 17:47:35 +0100230 teq r8, #0 @ if preempt count != 0
231 movne r0, #0 @ force flags to 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232 tst r0, #_TIF_NEED_RESCHED
233 blne svc_preempt
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234#endif
Catalin Marinasb86040a2009-07-24 12:32:54 +0100235 ldr r4, [sp, #S_PSR] @ irqs are already disabled
Russell King7ad1bcb2006-08-27 12:07:02 +0100236#ifdef CONFIG_TRACE_IRQFLAGS
Catalin Marinasb86040a2009-07-24 12:32:54 +0100237 tst r4, #PSR_I_BIT
Russell King7ad1bcb2006-08-27 12:07:02 +0100238 bleq trace_hardirqs_on
239#endif
Catalin Marinasb86040a2009-07-24 12:32:54 +0100240 svc_exit r4 @ return from exception
Catalin Marinasc4c57162009-02-16 11:42:09 +0100241 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100242ENDPROC(__irq_svc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243
244 .ltorg
245
246#ifdef CONFIG_PREEMPT
247svc_preempt:
Russell King28fab1a2008-04-13 17:47:35 +0100248 mov r8, lr
Linus Torvalds1da177e2005-04-16 15:20:36 -07002491: bl preempt_schedule_irq @ irq en/disable is done inside
Russell King706fdd92005-05-21 18:15:45 +0100250 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251 tst r0, #_TIF_NEED_RESCHED
Russell King28fab1a2008-04-13 17:47:35 +0100252 moveq pc, r8 @ go again
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253 b 1b
254#endif
255
256 .align 5
257__und_svc:
Nicolas Pitred30a0c82007-12-14 15:56:01 -0500258#ifdef CONFIG_KPROBES
259 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
260 @ it obviously needs free stack space which then will belong to
261 @ the saved context.
262 svc_entry 64
263#else
Russell Kingccea7a12005-05-31 22:22:32 +0100264 svc_entry
Nicolas Pitred30a0c82007-12-14 15:56:01 -0500265#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700266
267 @
268 @ call emulation code, which returns using r9 if it has emulated
269 @ the instruction, or the more conventional lr if we are to treat
270 @ this as a real undefined instruction
271 @
272 @ r0 - instruction
273 @
Catalin Marinas83e686e2009-09-18 23:27:07 +0100274#ifndef CONFIG_THUMB2_KERNEL
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275 ldr r0, [r2, #-4]
Catalin Marinas83e686e2009-09-18 23:27:07 +0100276#else
277 ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2
278 and r9, r0, #0xf800
279 cmp r9, #0xe800 @ 32-bit instruction if xx >= 0
280 ldrhhs r9, [r2] @ bottom 16 bits
281 orrhs r0, r9, r0, lsl #16
282#endif
Catalin Marinasb86040a2009-07-24 12:32:54 +0100283 adr r9, BSYM(1f)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700284 bl call_fpe
285
286 mov r0, sp @ struct pt_regs *regs
287 bl do_undefinstr
288
289 @
290 @ IRQs off again before pulling preserved data off the stack
291 @
Russell Kingac788842010-07-10 10:10:18 +01002921: disable_irq_notrace
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293
294 @
295 @ restore SPSR and restart the instruction
296 @
Catalin Marinasb86040a2009-07-24 12:32:54 +0100297 ldr r2, [sp, #S_PSR] @ Get SVC cpsr
298 svc_exit r2 @ return from exception
Catalin Marinasc4c57162009-02-16 11:42:09 +0100299 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100300ENDPROC(__und_svc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301
302 .align 5
303__pabt_svc:
Russell Kingccea7a12005-05-31 22:22:32 +0100304 svc_entry
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305
306 @
307 @ re-enable interrupts if appropriate
308 @
309 mrs r9, cpsr
310 tst r3, #PSR_I_BIT
311 biceq r9, r9, #PSR_I_BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312
Russell Kingac8b9c12011-06-26 10:22:08 +0100313 pabt_helper
Will Deacon7e202692010-11-28 14:57:24 +0000314 debug_entry r1
Paul Brook48d79272008-04-18 22:43:07 +0100315 msr cpsr_c, r9 @ Maybe enable interrupts
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100316 mov r2, sp @ regs
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317 bl do_PrefetchAbort @ call abort handler
318
319 @
320 @ IRQs off again before pulling preserved data off the stack
321 @
Russell Kingac788842010-07-10 10:10:18 +0100322 disable_irq_notrace
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323
324 @
325 @ restore SPSR and restart the instruction
326 @
Catalin Marinasb86040a2009-07-24 12:32:54 +0100327 ldr r2, [sp, #S_PSR]
328 svc_exit r2 @ return from exception
Catalin Marinasc4c57162009-02-16 11:42:09 +0100329 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100330ENDPROC(__pabt_svc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331
332 .align 5
Russell King49f680e2005-05-31 18:02:00 +0100333.LCcralign:
334 .word cr_alignment
Paul Brook48d79272008-04-18 22:43:07 +0100335#ifdef MULTI_DABORT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336.LCprocfns:
337 .word processor
338#endif
339.LCfp:
340 .word fp_enter
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341
342/*
343 * User mode handlers
Nicolas Pitre2dede2d2006-01-14 16:18:08 +0000344 *
345 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346 */
Nicolas Pitre2dede2d2006-01-14 16:18:08 +0000347
348#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
349#error "sizeof(struct pt_regs) must be a multiple of 8"
350#endif
351
Russell Kingccea7a12005-05-31 22:22:32 +0100352 .macro usr_entry
Catalin Marinasc4c57162009-02-16 11:42:09 +0100353 UNWIND(.fnstart )
354 UNWIND(.cantunwind ) @ don't unwind the user space
Russell Kingccea7a12005-05-31 22:22:32 +0100355 sub sp, sp, #S_FRAME_SIZE
Catalin Marinasb86040a2009-07-24 12:32:54 +0100356 ARM( stmib sp, {r1 - r12} )
357 THUMB( stmia sp, {r0 - r12} )
Russell Kingccea7a12005-05-31 22:22:32 +0100358
359 ldmia r0, {r1 - r3}
360 add r0, sp, #S_PC @ here for interlock avoidance
361 mov r4, #-1 @ "" "" "" ""
362
363 str r1, [sp] @ save the "real" r0 copied
364 @ from the exception stack
Linus Torvalds1da177e2005-04-16 15:20:36 -0700365
366 @
367 @ We are now ready to fill in the remaining blanks on the stack:
368 @
369 @ r2 - lr_<exception>, already fixed up for correct return/restart
370 @ r3 - spsr_<exception>
371 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
372 @
373 @ Also, separately save sp_usr and lr_usr
374 @
Russell Kingccea7a12005-05-31 22:22:32 +0100375 stmia r0, {r2 - r4}
Catalin Marinasb86040a2009-07-24 12:32:54 +0100376 ARM( stmdb r0, {sp, lr}^ )
377 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378
379 @
380 @ Enable the alignment trap while in kernel mode
381 @
Russell King49f680e2005-05-31 18:02:00 +0100382 alignment_trap r0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383
384 @
385 @ Clear FP to mark the first stack frame
386 @
387 zero_fp
388 .endm
389
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100390 .macro kuser_cmpxchg_check
391#if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
392#ifndef CONFIG_MMU
393#warning "NPTL on non MMU needs fixing"
394#else
395 @ Make sure our user space atomic helper is restarted
396 @ if it was interrupted in a critical region. Here we
397 @ perform a quick test inline since it should be false
398 @ 99.9999% of the time. The rest is done out of line.
399 cmp r2, #TASK_SIZE
400 blhs kuser_cmpxchg_fixup
401#endif
402#endif
403 .endm
404
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405 .align 5
406__dabt_usr:
Russell Kingccea7a12005-05-31 22:22:32 +0100407 usr_entry
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100408 kuser_cmpxchg_check
Russell Kingac8b9c12011-06-26 10:22:08 +0100409 dabt_helper
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410
411 @
412 @ IRQs on, then call the main handler
413 @
Will Deacon7e202692010-11-28 14:57:24 +0000414 debug_entry r1
Russell King1ec42c02005-04-26 15:18:26 +0100415 enable_irq
Linus Torvalds1da177e2005-04-16 15:20:36 -0700416 mov r2, sp
Catalin Marinasb86040a2009-07-24 12:32:54 +0100417 adr lr, BSYM(ret_from_exception)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418 b do_DataAbort
Catalin Marinasc4c57162009-02-16 11:42:09 +0100419 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100420ENDPROC(__dabt_usr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700421
422 .align 5
423__irq_usr:
Russell Kingccea7a12005-05-31 22:22:32 +0100424 usr_entry
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100425 kuser_cmpxchg_check
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426
Ming Lei9fc25522011-06-05 02:24:58 +0100427#ifdef CONFIG_IRQSOFF_TRACER
428 bl trace_hardirqs_off
429#endif
430
Russell King187a51a2005-05-21 18:14:44 +0100431 irq_handler
Russell King1613cc12011-06-25 10:57:57 +0100432 get_thread_info tsk
Linus Torvalds1da177e2005-04-16 15:20:36 -0700433 mov why, #0
Ming Lei9fc25522011-06-05 02:24:58 +0100434 b ret_to_user_from_irq
Catalin Marinasc4c57162009-02-16 11:42:09 +0100435 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100436ENDPROC(__irq_usr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700437
438 .ltorg
439
440 .align 5
441__und_usr:
Russell Kingccea7a12005-05-31 22:22:32 +0100442 usr_entry
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444 @
445 @ fall through to the emulation code, which returns using r9 if
446 @ it has emulated the instruction, or the more conventional lr
447 @ if we are to treat this as a real undefined instruction
448 @
449 @ r0 - instruction
450 @
Catalin Marinasb86040a2009-07-24 12:32:54 +0100451 adr r9, BSYM(ret_from_exception)
452 adr lr, BSYM(__und_usr_unknown)
Paul Brookcb170a42008-04-18 22:43:08 +0100453 tst r3, #PSR_T_BIT @ Thumb mode?
Catalin Marinasb86040a2009-07-24 12:32:54 +0100454 itet eq @ explicit IT needed for the 1f label
Paul Brookcb170a42008-04-18 22:43:08 +0100455 subeq r4, r2, #4 @ ARM instr at LR - 4
456 subne r4, r2, #2 @ Thumb instr at LR - 2
4571: ldreqt r0, [r4]
Catalin Marinas26584852009-05-30 14:00:18 +0100458#ifdef CONFIG_CPU_ENDIAN_BE8
459 reveq r0, r0 @ little endian instruction
460#endif
Paul Brookcb170a42008-04-18 22:43:08 +0100461 beq call_fpe
462 @ Thumb instruction
463#if __LINUX_ARM_ARCH__ >= 7
Catalin Marinasb86040a2009-07-24 12:32:54 +01004642:
465 ARM( ldrht r5, [r4], #2 )
466 THUMB( ldrht r5, [r4] )
467 THUMB( add r4, r4, #2 )
Paul Brookcb170a42008-04-18 22:43:08 +0100468 and r0, r5, #0xf800 @ mask bits 111x x... .... ....
469 cmp r0, #0xe800 @ 32bit instruction if xx != 0
470 blo __und_usr_unknown
4713: ldrht r0, [r4]
472 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
473 orr r0, r0, r5, lsl #16
474#else
475 b __und_usr_unknown
476#endif
Catalin Marinasc4c57162009-02-16 11:42:09 +0100477 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100478ENDPROC(__und_usr)
Paul Brookcb170a42008-04-18 22:43:08 +0100479
Linus Torvalds1da177e2005-04-16 15:20:36 -0700480 @
481 @ fallthrough to call_fpe
482 @
483
484/*
485 * The out of line fixup for the ldrt above.
486 */
Russell King42604152010-04-19 10:15:03 +0100487 .pushsection .fixup, "ax"
Paul Brookcb170a42008-04-18 22:43:08 +01004884: mov pc, r9
Russell King42604152010-04-19 10:15:03 +0100489 .popsection
490 .pushsection __ex_table,"a"
Paul Brookcb170a42008-04-18 22:43:08 +0100491 .long 1b, 4b
492#if __LINUX_ARM_ARCH__ >= 7
493 .long 2b, 4b
494 .long 3b, 4b
495#endif
Russell King42604152010-04-19 10:15:03 +0100496 .popsection
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497
498/*
499 * Check whether the instruction is a co-processor instruction.
500 * If yes, we need to call the relevant co-processor handler.
501 *
502 * Note that we don't do a full check here for the co-processor
503 * instructions; all instructions with bit 27 set are well
504 * defined. The only instructions that should fault are the
505 * co-processor instructions. However, we have to watch out
506 * for the ARM6/ARM7 SWI bug.
507 *
Catalin Marinasb5872db2008-01-10 19:16:17 +0100508 * NEON is a special case that has to be handled here. Not all
509 * NEON instructions are co-processor instructions, so we have
510 * to make a special case of checking for them. Plus, there's
511 * five groups of them, so we have a table of mask/opcode pairs
512 * to check against, and if any match then we branch off into the
513 * NEON handler code.
514 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700515 * Emulators may wish to make use of the following registers:
516 * r0 = instruction opcode.
517 * r2 = PC+4
Russell Kingdb6ccbb2007-01-06 22:53:48 +0000518 * r9 = normal "successful" return address
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519 * r10 = this threads thread_info structure.
Russell Kingdb6ccbb2007-01-06 22:53:48 +0000520 * lr = unrecognised instruction return address
Linus Torvalds1da177e2005-04-16 15:20:36 -0700521 */
Paul Brookcb170a42008-04-18 22:43:08 +0100522 @
523 @ Fall-through from Thumb-2 __und_usr
524 @
525#ifdef CONFIG_NEON
526 adr r6, .LCneon_thumb_opcodes
527 b 2f
528#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700529call_fpe:
Catalin Marinasb5872db2008-01-10 19:16:17 +0100530#ifdef CONFIG_NEON
Paul Brookcb170a42008-04-18 22:43:08 +0100531 adr r6, .LCneon_arm_opcodes
Catalin Marinasb5872db2008-01-10 19:16:17 +01005322:
533 ldr r7, [r6], #4 @ mask value
534 cmp r7, #0 @ end mask?
535 beq 1f
536 and r8, r0, r7
537 ldr r7, [r6], #4 @ opcode bits matching in mask
538 cmp r8, r7 @ NEON instruction?
539 bne 2b
540 get_thread_info r10
541 mov r7, #1
542 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
543 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
544 b do_vfp @ let VFP handler handle this
5451:
546#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
Paul Brookcb170a42008-04-18 22:43:08 +0100548 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700549#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
550 and r8, r0, #0x0f000000 @ mask out op-code bits
551 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
552#endif
553 moveq pc, lr
554 get_thread_info r10 @ get current thread
555 and r8, r0, #0x00000f00 @ mask out CP number
Catalin Marinasb86040a2009-07-24 12:32:54 +0100556 THUMB( lsr r8, r8, #8 )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700557 mov r7, #1
558 add r6, r10, #TI_USED_CP
Catalin Marinasb86040a2009-07-24 12:32:54 +0100559 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
560 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700561#ifdef CONFIG_IWMMXT
562 @ Test if we need to give access to iWMMXt coprocessors
563 ldr r5, [r10, #TI_FLAGS]
564 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
565 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
566 bcs iwmmxt_task_enable
567#endif
Catalin Marinasb86040a2009-07-24 12:32:54 +0100568 ARM( add pc, pc, r8, lsr #6 )
569 THUMB( lsl r8, r8, #2 )
570 THUMB( add pc, r8 )
571 nop
Linus Torvalds1da177e2005-04-16 15:20:36 -0700572
Catalin Marinasa771fe62009-10-12 17:31:20 +0100573 movw_pc lr @ CP#0
Catalin Marinasb86040a2009-07-24 12:32:54 +0100574 W(b) do_fpe @ CP#1 (FPE)
575 W(b) do_fpe @ CP#2 (FPE)
Catalin Marinasa771fe62009-10-12 17:31:20 +0100576 movw_pc lr @ CP#3
Lennert Buytenhekc17fad12006-06-27 23:03:03 +0100577#ifdef CONFIG_CRUNCH
578 b crunch_task_enable @ CP#4 (MaverickCrunch)
579 b crunch_task_enable @ CP#5 (MaverickCrunch)
580 b crunch_task_enable @ CP#6 (MaverickCrunch)
581#else
Catalin Marinasa771fe62009-10-12 17:31:20 +0100582 movw_pc lr @ CP#4
583 movw_pc lr @ CP#5
584 movw_pc lr @ CP#6
Lennert Buytenhekc17fad12006-06-27 23:03:03 +0100585#endif
Catalin Marinasa771fe62009-10-12 17:31:20 +0100586 movw_pc lr @ CP#7
587 movw_pc lr @ CP#8
588 movw_pc lr @ CP#9
Linus Torvalds1da177e2005-04-16 15:20:36 -0700589#ifdef CONFIG_VFP
Catalin Marinasb86040a2009-07-24 12:32:54 +0100590 W(b) do_vfp @ CP#10 (VFP)
591 W(b) do_vfp @ CP#11 (VFP)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700592#else
Catalin Marinasa771fe62009-10-12 17:31:20 +0100593 movw_pc lr @ CP#10 (VFP)
594 movw_pc lr @ CP#11 (VFP)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700595#endif
Catalin Marinasa771fe62009-10-12 17:31:20 +0100596 movw_pc lr @ CP#12
597 movw_pc lr @ CP#13
598 movw_pc lr @ CP#14 (Debug)
599 movw_pc lr @ CP#15 (Control)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700600
Catalin Marinasb5872db2008-01-10 19:16:17 +0100601#ifdef CONFIG_NEON
602 .align 6
603
Paul Brookcb170a42008-04-18 22:43:08 +0100604.LCneon_arm_opcodes:
Catalin Marinasb5872db2008-01-10 19:16:17 +0100605 .word 0xfe000000 @ mask
606 .word 0xf2000000 @ opcode
607
608 .word 0xff100000 @ mask
609 .word 0xf4000000 @ opcode
610
611 .word 0x00000000 @ mask
612 .word 0x00000000 @ opcode
Paul Brookcb170a42008-04-18 22:43:08 +0100613
614.LCneon_thumb_opcodes:
615 .word 0xef000000 @ mask
616 .word 0xef000000 @ opcode
617
618 .word 0xff100000 @ mask
619 .word 0xf9000000 @ opcode
620
621 .word 0x00000000 @ mask
622 .word 0x00000000 @ opcode
Catalin Marinasb5872db2008-01-10 19:16:17 +0100623#endif
624
Linus Torvalds1da177e2005-04-16 15:20:36 -0700625do_fpe:
Russell King5d25ac02006-03-15 12:33:43 +0000626 enable_irq
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627 ldr r4, .LCfp
628 add r10, r10, #TI_FPSTATE @ r10 = workspace
629 ldr pc, [r4] @ Call FP module USR entry point
630
631/*
632 * The FP module is called with these registers set:
633 * r0 = instruction
634 * r2 = PC+4
635 * r9 = normal "successful" return address
636 * r10 = FP workspace
637 * lr = unrecognised FP instruction return address
638 */
639
Santosh Shilimkar124efc22010-04-30 10:45:46 +0100640 .pushsection .data
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641ENTRY(fp_enter)
Russell Kingdb6ccbb2007-01-06 22:53:48 +0000642 .word no_fp
Santosh Shilimkar124efc22010-04-30 10:45:46 +0100643 .popsection
Linus Torvalds1da177e2005-04-16 15:20:36 -0700644
Catalin Marinas83e686e2009-09-18 23:27:07 +0100645ENTRY(no_fp)
646 mov pc, lr
647ENDPROC(no_fp)
Russell Kingdb6ccbb2007-01-06 22:53:48 +0000648
649__und_usr_unknown:
Russell Kingecbab712009-01-27 23:20:00 +0000650 enable_irq
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651 mov r0, sp
Catalin Marinasb86040a2009-07-24 12:32:54 +0100652 adr lr, BSYM(ret_from_exception)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653 b do_undefinstr
Catalin Marinas93ed3972008-08-28 11:22:32 +0100654ENDPROC(__und_usr_unknown)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655
656 .align 5
657__pabt_usr:
Russell Kingccea7a12005-05-31 22:22:32 +0100658 usr_entry
Russell Kingac8b9c12011-06-26 10:22:08 +0100659 pabt_helper
Will Deacon7e202692010-11-28 14:57:24 +0000660 debug_entry r1
Russell King1ec42c02005-04-26 15:18:26 +0100661 enable_irq @ Enable interrupts
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100662 mov r2, sp @ regs
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663 bl do_PrefetchAbort @ call abort handler
Catalin Marinasc4c57162009-02-16 11:42:09 +0100664 UNWIND(.fnend )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665 /* fall through */
666/*
667 * This is the return code to user mode for abort handlers
668 */
669ENTRY(ret_from_exception)
Catalin Marinasc4c57162009-02-16 11:42:09 +0100670 UNWIND(.fnstart )
671 UNWIND(.cantunwind )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700672 get_thread_info tsk
673 mov why, #0
674 b ret_to_user
Catalin Marinasc4c57162009-02-16 11:42:09 +0100675 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100676ENDPROC(__pabt_usr)
677ENDPROC(ret_from_exception)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678
679/*
680 * Register switch for ARMv3 and ARMv4 processors
681 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
682 * previous and next are guaranteed not to be the same.
683 */
684ENTRY(__switch_to)
Catalin Marinasc4c57162009-02-16 11:42:09 +0100685 UNWIND(.fnstart )
686 UNWIND(.cantunwind )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700687 add ip, r1, #TI_CPU_SAVE
688 ldr r3, [r2, #TI_TP_VALUE]
Catalin Marinasb86040a2009-07-24 12:32:54 +0100689 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
690 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
691 THUMB( str sp, [ip], #4 )
692 THUMB( str lr, [ip], #4 )
Catalin Marinas247055a2010-09-13 16:03:21 +0100693#ifdef CONFIG_CPU_USE_DOMAINS
Russell Kingd6551e82006-06-21 13:31:52 +0100694 ldr r6, [r2, #TI_CPU_DOMAIN]
Hyok S. Choiafeb90c2006-01-13 21:05:25 +0000695#endif
Tony Lindgrenf159f4e2010-07-05 14:53:10 +0100696 set_tls r3, r4, r5
Nicolas Pitredf0698b2010-06-07 21:50:33 -0400697#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
698 ldr r7, [r2, #TI_TASK]
699 ldr r8, =__stack_chk_guard
700 ldr r7, [r7, #TSK_STACK_CANARY]
701#endif
Catalin Marinas247055a2010-09-13 16:03:21 +0100702#ifdef CONFIG_CPU_USE_DOMAINS
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
Hyok S. Choiafeb90c2006-01-13 21:05:25 +0000704#endif
Russell Kingd6551e82006-06-21 13:31:52 +0100705 mov r5, r0
706 add r4, r2, #TI_CPU_SAVE
707 ldr r0, =thread_notify_head
708 mov r1, #THREAD_NOTIFY_SWITCH
709 bl atomic_notifier_call_chain
Nicolas Pitredf0698b2010-06-07 21:50:33 -0400710#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
711 str r7, [r8]
712#endif
Catalin Marinasb86040a2009-07-24 12:32:54 +0100713 THUMB( mov ip, r4 )
Russell Kingd6551e82006-06-21 13:31:52 +0100714 mov r0, r5
Catalin Marinasb86040a2009-07-24 12:32:54 +0100715 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
716 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
717 THUMB( ldr sp, [ip], #4 )
718 THUMB( ldr pc, [ip] )
Catalin Marinasc4c57162009-02-16 11:42:09 +0100719 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100720ENDPROC(__switch_to)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700721
722 __INIT
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100723
724/*
725 * User helpers.
726 *
727 * These are segment of kernel provided user code reachable from user space
728 * at a fixed address in kernel memory. This is used to provide user space
729 * with some operations which require kernel help because of unimplemented
730 * native feature and/or instructions in many ARM CPUs. The idea is for
731 * this code to be executed directly in user mode for best efficiency but
732 * which is too intimate with the kernel counter part to be left to user
733 * libraries. In fact this code might even differ from one CPU to another
734 * depending on the available instruction set and restrictions like on
735 * SMP systems. In other words, the kernel reserves the right to change
736 * this code as needed without warning. Only the entry points and their
737 * results are guaranteed to be stable.
738 *
739 * Each segment is 32-byte aligned and will be moved to the top of the high
740 * vector page. New segments (if ever needed) must be added in front of
741 * existing ones. This mechanism should be used only for things that are
742 * really small and justified, and not be abused freely.
743 *
744 * User space is expected to implement those things inline when optimizing
745 * for a processor that has the necessary native support, but only if such
746 * resulting binaries are already to be incompatible with earlier ARM
747 * processors due to the use of unsupported instructions other than what
748 * is provided here. In other words don't make binaries unable to run on
749 * earlier processors just for the sake of not using these kernel helpers
750 * if your compiled code is not going to use the new instructions for other
751 * purpose.
752 */
Catalin Marinasb86040a2009-07-24 12:32:54 +0100753 THUMB( .arm )
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100754
Nicolas Pitreba9b5d72006-08-18 17:20:15 +0100755 .macro usr_ret, reg
756#ifdef CONFIG_ARM_THUMB
757 bx \reg
758#else
759 mov pc, \reg
760#endif
761 .endm
762
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100763 .align 5
764 .globl __kuser_helper_start
765__kuser_helper_start:
766
767/*
768 * Reference prototype:
769 *
Nicolas Pitre7c612bf2005-12-19 22:20:51 +0000770 * void __kernel_memory_barrier(void)
771 *
772 * Input:
773 *
774 * lr = return address
775 *
776 * Output:
777 *
778 * none
779 *
780 * Clobbered:
781 *
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100782 * none
Nicolas Pitre7c612bf2005-12-19 22:20:51 +0000783 *
784 * Definition and user space usage example:
785 *
786 * typedef void (__kernel_dmb_t)(void);
787 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
788 *
789 * Apply any needed memory barrier to preserve consistency with data modified
790 * manually and __kuser_cmpxchg usage.
791 *
792 * This could be used as follows:
793 *
794 * #define __kernel_dmb() \
795 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
Paul Brook6896eec2006-03-28 22:19:29 +0100796 * : : : "r0", "lr","cc" )
Nicolas Pitre7c612bf2005-12-19 22:20:51 +0000797 */
798
799__kuser_memory_barrier: @ 0xffff0fa0
Dave Martined3768a2010-12-01 15:39:23 +0100800 smp_dmb arm
Nicolas Pitreba9b5d72006-08-18 17:20:15 +0100801 usr_ret lr
Nicolas Pitre7c612bf2005-12-19 22:20:51 +0000802
803 .align 5
804
805/*
806 * Reference prototype:
807 *
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100808 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
809 *
810 * Input:
811 *
812 * r0 = oldval
813 * r1 = newval
814 * r2 = ptr
815 * lr = return address
816 *
817 * Output:
818 *
819 * r0 = returned value (zero or non-zero)
820 * C flag = set if r0 == 0, clear if r0 != 0
821 *
822 * Clobbered:
823 *
824 * r3, ip, flags
825 *
826 * Definition and user space usage example:
827 *
828 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
829 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
830 *
831 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
832 * Return zero if *ptr was changed or non-zero if no exchange happened.
833 * The C flag is also set if *ptr was changed to allow for assembly
834 * optimization in the calling code.
835 *
Nicolas Pitre5964eae2006-02-08 21:19:37 +0000836 * Notes:
837 *
838 * - This routine already includes memory barriers as needed.
839 *
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100840 * For example, a user space atomic_add implementation could look like this:
841 *
842 * #define atomic_add(ptr, val) \
843 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
844 * register unsigned int __result asm("r1"); \
845 * asm volatile ( \
846 * "1: @ atomic_add\n\t" \
847 * "ldr r0, [r2]\n\t" \
848 * "mov r3, #0xffff0fff\n\t" \
849 * "add lr, pc, #4\n\t" \
850 * "add r1, r0, %2\n\t" \
851 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
852 * "bcc 1b" \
853 * : "=&r" (__result) \
854 * : "r" (__ptr), "rIL" (val) \
855 * : "r0","r3","ip","lr","cc","memory" ); \
856 * __result; })
857 */
858
859__kuser_cmpxchg: @ 0xffff0fc0
860
Nicolas Pitredcef1f62005-06-08 19:00:47 +0100861#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100862
Nicolas Pitredcef1f62005-06-08 19:00:47 +0100863 /*
864 * Poor you. No fast solution possible...
865 * The kernel itself must perform the operation.
866 * A special ghost syscall is used for that (see traps.c).
867 */
Nicolas Pitre5e097442006-01-18 22:38:49 +0000868 stmfd sp!, {r7, lr}
Dave Martin55afd262010-12-01 18:12:43 +0100869 ldr r7, 1f @ it's 20 bits
Russell Kingcc20d422009-11-09 23:53:29 +0000870 swi __ARM_NR_cmpxchg
Nicolas Pitre5e097442006-01-18 22:38:49 +0000871 ldmfd sp!, {r7, pc}
Russell Kingcc20d422009-11-09 23:53:29 +00008721: .word __ARM_NR_cmpxchg
Nicolas Pitredcef1f62005-06-08 19:00:47 +0100873
874#elif __LINUX_ARM_ARCH__ < 6
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100875
Nicolas Pitre49bca4c2006-02-08 21:19:37 +0000876#ifdef CONFIG_MMU
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100877
878 /*
879 * The only thing that can break atomicity in this cmpxchg
880 * implementation is either an IRQ or a data abort exception
881 * causing another process/thread to be scheduled in the middle
882 * of the critical sequence. To prevent this, code is added to
883 * the IRQ and data abort exception handlers to set the pc back
884 * to the beginning of the critical section if it is found to be
885 * within that critical section (see kuser_cmpxchg_fixup).
886 */
8871: ldr r3, [r2] @ load current val
888 subs r3, r3, r0 @ compare with oldval
8892: streq r1, [r2] @ store newval if eq
890 rsbs r0, r3, #0 @ set return val and C flag
891 usr_ret lr
892
893 .text
894kuser_cmpxchg_fixup:
895 @ Called from kuser_cmpxchg_check macro.
896 @ r2 = address of interrupted insn (must be preserved).
897 @ sp = saved regs. r7 and r8 are clobbered.
898 @ 1b = first critical insn, 2b = last critical insn.
899 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
900 mov r7, #0xffff0fff
901 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
902 subs r8, r2, r7
903 rsbcss r8, r8, #(2b - 1b)
904 strcs r7, [sp, #S_PC]
905 mov pc, lr
906 .previous
907
Nicolas Pitre49bca4c2006-02-08 21:19:37 +0000908#else
909#warning "NPTL on non MMU needs fixing"
910 mov r0, #-1
911 adds r0, r0, #0
Nicolas Pitreba9b5d72006-08-18 17:20:15 +0100912 usr_ret lr
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100913#endif
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100914
915#else
916
Dave Martined3768a2010-12-01 15:39:23 +0100917 smp_dmb arm
Nicolas Pitreb49c0f22007-11-20 17:20:29 +01009181: ldrex r3, [r2]
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100919 subs r3, r3, r0
920 strexeq r3, r1, [r2]
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100921 teqeq r3, #1
922 beq 1b
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100923 rsbs r0, r3, #0
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100924 /* beware -- each __kuser slot must be 8 instructions max */
Russell Kingf00ec482010-09-04 10:47:48 +0100925 ALT_SMP(b __kuser_memory_barrier)
926 ALT_UP(usr_ret lr)
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100927
928#endif
929
930 .align 5
931
932/*
933 * Reference prototype:
934 *
935 * int __kernel_get_tls(void)
936 *
937 * Input:
938 *
939 * lr = return address
940 *
941 * Output:
942 *
943 * r0 = TLS value
944 *
945 * Clobbered:
946 *
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100947 * none
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100948 *
949 * Definition and user space usage example:
950 *
951 * typedef int (__kernel_get_tls_t)(void);
952 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
953 *
954 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
955 *
956 * This could be used as follows:
957 *
958 * #define __kernel_get_tls() \
959 * ({ register unsigned int __val asm("r0"); \
960 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
961 * : "=r" (__val) : : "lr","cc" ); \
962 * __val; })
963 */
964
965__kuser_get_tls: @ 0xffff0fe0
Tony Lindgrenf159f4e2010-07-05 14:53:10 +0100966 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
Nicolas Pitreba9b5d72006-08-18 17:20:15 +0100967 usr_ret lr
Tony Lindgrenf159f4e2010-07-05 14:53:10 +0100968 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
969 .rep 4
970 .word 0 @ 0xffff0ff0 software TLS value, then
971 .endr @ pad up to __kuser_helper_version
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100972
973/*
974 * Reference declaration:
975 *
976 * extern unsigned int __kernel_helper_version;
977 *
978 * Definition and user space usage example:
979 *
980 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
981 *
982 * User space may read this to determine the curent number of helpers
983 * available.
984 */
985
986__kuser_helper_version: @ 0xffff0ffc
987 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
988
989 .globl __kuser_helper_end
990__kuser_helper_end:
991
Catalin Marinasb86040a2009-07-24 12:32:54 +0100992 THUMB( .thumb )
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100993
Linus Torvalds1da177e2005-04-16 15:20:36 -0700994/*
995 * Vector stubs.
996 *
Russell King79335232005-04-26 15:17:42 +0100997 * This code is copied to 0xffff0200 so we can use branches in the
998 * vectors, rather than ldr's. Note that this code must not
999 * exceed 0x300 bytes.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001000 *
1001 * Common stub entry macro:
1002 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
Russell Kingccea7a12005-05-31 22:22:32 +01001003 *
1004 * SP points to a minimal amount of processor-private memory, the address
1005 * of which is copied into r0 for the mode specific abort handler.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001006 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001007 .macro vector_stub, name, mode, correction=0
Linus Torvalds1da177e2005-04-16 15:20:36 -07001008 .align 5
1009
1010vector_\name:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001011 .if \correction
1012 sub lr, lr, #\correction
1013 .endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001014
Russell Kingccea7a12005-05-31 22:22:32 +01001015 @
1016 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1017 @ (parent CPSR)
1018 @
1019 stmia sp, {r0, lr} @ save r0, lr
1020 mrs lr, spsr
1021 str lr, [sp, #8] @ save spsr
1022
1023 @
1024 @ Prepare for SVC32 mode. IRQs remain disabled.
1025 @
1026 mrs r0, cpsr
Catalin Marinasb86040a2009-07-24 12:32:54 +01001027 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
Russell Kingccea7a12005-05-31 22:22:32 +01001028 msr spsr_cxsf, r0
1029
1030 @
1031 @ the branch table must immediately follow this code
1032 @
Russell Kingccea7a12005-05-31 22:22:32 +01001033 and lr, lr, #0x0f
Catalin Marinasb86040a2009-07-24 12:32:54 +01001034 THUMB( adr r0, 1f )
1035 THUMB( ldr lr, [r0, lr, lsl #2] )
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001036 mov r0, sp
Catalin Marinasb86040a2009-07-24 12:32:54 +01001037 ARM( ldr lr, [pc, lr, lsl #2] )
Russell Kingccea7a12005-05-31 22:22:32 +01001038 movs pc, lr @ branch to handler in SVC mode
Catalin Marinas93ed3972008-08-28 11:22:32 +01001039ENDPROC(vector_\name)
Catalin Marinas88987ef2009-07-24 12:32:52 +01001040
1041 .align 2
1042 @ handler addresses follow this label
10431:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001044 .endm
1045
Russell King79335232005-04-26 15:17:42 +01001046 .globl __stubs_start
Linus Torvalds1da177e2005-04-16 15:20:36 -07001047__stubs_start:
1048/*
1049 * Interrupt dispatcher
1050 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001051 vector_stub irq, IRQ_MODE, 4
Linus Torvalds1da177e2005-04-16 15:20:36 -07001052
1053 .long __irq_usr @ 0 (USR_26 / USR_32)
1054 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1055 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1056 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1057 .long __irq_invalid @ 4
1058 .long __irq_invalid @ 5
1059 .long __irq_invalid @ 6
1060 .long __irq_invalid @ 7
1061 .long __irq_invalid @ 8
1062 .long __irq_invalid @ 9
1063 .long __irq_invalid @ a
1064 .long __irq_invalid @ b
1065 .long __irq_invalid @ c
1066 .long __irq_invalid @ d
1067 .long __irq_invalid @ e
1068 .long __irq_invalid @ f
1069
1070/*
1071 * Data abort dispatcher
1072 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1073 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001074 vector_stub dabt, ABT_MODE, 8
Linus Torvalds1da177e2005-04-16 15:20:36 -07001075
1076 .long __dabt_usr @ 0 (USR_26 / USR_32)
1077 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1078 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1079 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1080 .long __dabt_invalid @ 4
1081 .long __dabt_invalid @ 5
1082 .long __dabt_invalid @ 6
1083 .long __dabt_invalid @ 7
1084 .long __dabt_invalid @ 8
1085 .long __dabt_invalid @ 9
1086 .long __dabt_invalid @ a
1087 .long __dabt_invalid @ b
1088 .long __dabt_invalid @ c
1089 .long __dabt_invalid @ d
1090 .long __dabt_invalid @ e
1091 .long __dabt_invalid @ f
1092
1093/*
1094 * Prefetch abort dispatcher
1095 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1096 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001097 vector_stub pabt, ABT_MODE, 4
Linus Torvalds1da177e2005-04-16 15:20:36 -07001098
1099 .long __pabt_usr @ 0 (USR_26 / USR_32)
1100 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1101 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1102 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1103 .long __pabt_invalid @ 4
1104 .long __pabt_invalid @ 5
1105 .long __pabt_invalid @ 6
1106 .long __pabt_invalid @ 7
1107 .long __pabt_invalid @ 8
1108 .long __pabt_invalid @ 9
1109 .long __pabt_invalid @ a
1110 .long __pabt_invalid @ b
1111 .long __pabt_invalid @ c
1112 .long __pabt_invalid @ d
1113 .long __pabt_invalid @ e
1114 .long __pabt_invalid @ f
1115
1116/*
1117 * Undef instr entry dispatcher
1118 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1119 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001120 vector_stub und, UND_MODE
Linus Torvalds1da177e2005-04-16 15:20:36 -07001121
1122 .long __und_usr @ 0 (USR_26 / USR_32)
1123 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1124 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1125 .long __und_svc @ 3 (SVC_26 / SVC_32)
1126 .long __und_invalid @ 4
1127 .long __und_invalid @ 5
1128 .long __und_invalid @ 6
1129 .long __und_invalid @ 7
1130 .long __und_invalid @ 8
1131 .long __und_invalid @ 9
1132 .long __und_invalid @ a
1133 .long __und_invalid @ b
1134 .long __und_invalid @ c
1135 .long __und_invalid @ d
1136 .long __und_invalid @ e
1137 .long __und_invalid @ f
1138
1139 .align 5
1140
1141/*=============================================================================
1142 * Undefined FIQs
1143 *-----------------------------------------------------------------------------
1144 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1145 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1146 * Basically to switch modes, we *HAVE* to clobber one register... brain
1147 * damage alert! I don't think that we can execute any code in here in any
1148 * other mode than FIQ... Ok you can switch to another mode, but you can't
1149 * get out of that mode without clobbering one register.
1150 */
1151vector_fiq:
1152 disable_fiq
1153 subs pc, lr, #4
1154
1155/*=============================================================================
1156 * Address exception handler
1157 *-----------------------------------------------------------------------------
1158 * These aren't too critical.
1159 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1160 */
1161
1162vector_addrexcptn:
1163 b vector_addrexcptn
1164
1165/*
1166 * We group all the following data together to optimise
1167 * for CPUs with separate I & D caches.
1168 */
1169 .align 5
1170
1171.LCvswi:
1172 .word vector_swi
1173
Russell King79335232005-04-26 15:17:42 +01001174 .globl __stubs_end
Linus Torvalds1da177e2005-04-16 15:20:36 -07001175__stubs_end:
1176
Russell King79335232005-04-26 15:17:42 +01001177 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
Linus Torvalds1da177e2005-04-16 15:20:36 -07001178
Russell King79335232005-04-26 15:17:42 +01001179 .globl __vectors_start
1180__vectors_start:
Catalin Marinasb86040a2009-07-24 12:32:54 +01001181 ARM( swi SYS_ERROR0 )
1182 THUMB( svc #0 )
1183 THUMB( nop )
1184 W(b) vector_und + stubs_offset
1185 W(ldr) pc, .LCvswi + stubs_offset
1186 W(b) vector_pabt + stubs_offset
1187 W(b) vector_dabt + stubs_offset
1188 W(b) vector_addrexcptn + stubs_offset
1189 W(b) vector_irq + stubs_offset
1190 W(b) vector_fiq + stubs_offset
Linus Torvalds1da177e2005-04-16 15:20:36 -07001191
Russell King79335232005-04-26 15:17:42 +01001192 .globl __vectors_end
1193__vectors_end:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001194
1195 .data
1196
Linus Torvalds1da177e2005-04-16 15:20:36 -07001197 .globl cr_alignment
1198 .globl cr_no_alignment
1199cr_alignment:
1200 .space 4
1201cr_no_alignment:
1202 .space 4
eric miao52108642010-12-13 09:42:34 +01001203
1204#ifdef CONFIG_MULTI_IRQ_HANDLER
1205 .globl handle_arch_irq
1206handle_arch_irq:
1207 .space 4
1208#endif