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review.evervolv.com / android_kernel_oneplus_msm8996 / 172fd616dd46a181be5c9c17bd0a84dd8ae0ce94 / . / drivers / pinctrl / sh-pfc / pfc-r8a73a4.c
blob: cd5c5fd74ba48b6028baa486d5b0234c9079545b [file] [log] [blame]
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]1/*
2 * Copyright (C) 2012-2013 Renesas Solutions Corp.
3 * Copyright (C) 2013 Magnus Damm
4 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of the
9 * License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]20#include <linux/io.h>
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]21#include <linux/kernel.h>
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]22#include <linux/pinctrl/pinconf-generic.h>
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]23#include <mach/irqs.h>
24#include <mach/r8a73a4.h>
25
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]26#include "core.h"
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]27#include "sh_pfc.h"
28
29#define CPU_ALL_PORT(fn, pfx, sfx) \
30 /* Port0 - Port30 */ \
31 PORT_10(fn, pfx, sfx), \
32 PORT_10(fn, pfx##1, sfx), \
33 PORT_10(fn, pfx##2, sfx), \
34 PORT_1(fn, pfx##30, sfx), \
35 /* Port32 - Port40 */ \
36 PORT_1(fn, pfx##32, sfx), PORT_1(fn, pfx##33, sfx), \
37 PORT_1(fn, pfx##34, sfx), PORT_1(fn, pfx##35, sfx), \
38 PORT_1(fn, pfx##36, sfx), PORT_1(fn, pfx##37, sfx), \
39 PORT_1(fn, pfx##38, sfx), PORT_1(fn, pfx##39, sfx), \
40 PORT_1(fn, pfx##40, sfx), \
41 /* Port64 - Port85 */ \
42 PORT_1(fn, pfx##64, sfx), PORT_1(fn, pfx##65, sfx), \
43 PORT_1(fn, pfx##66, sfx), PORT_1(fn, pfx##67, sfx), \
44 PORT_1(fn, pfx##68, sfx), PORT_1(fn, pfx##69, sfx), \
45 PORT_10(fn, pfx##7, sfx), \
46 PORT_1(fn, pfx##80, sfx), PORT_1(fn, pfx##81, sfx), \
47 PORT_1(fn, pfx##82, sfx), PORT_1(fn, pfx##83, sfx), \
48 PORT_1(fn, pfx##84, sfx), PORT_1(fn, pfx##85, sfx), \
49 /* Port96 - Port126 */ \
50 PORT_1(fn, pfx##96, sfx), PORT_1(fn, pfx##97, sfx), \
51 PORT_1(fn, pfx##98, sfx), PORT_1(fn, pfx##99, sfx), \
52 PORT_10(fn, pfx##10, sfx), \
53 PORT_10(fn, pfx##11, sfx), \
54 PORT_1(fn, pfx##120, sfx), PORT_1(fn, pfx##121, sfx), \
55 PORT_1(fn, pfx##122, sfx), PORT_1(fn, pfx##123, sfx), \
56 PORT_1(fn, pfx##124, sfx), PORT_1(fn, pfx##125, sfx), \
57 PORT_1(fn, pfx##126, sfx), \
58 /* Port128 - Port134 */ \
59 PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
60 PORT_1(fn, pfx##130, sfx), PORT_1(fn, pfx##131, sfx), \
61 PORT_1(fn, pfx##132, sfx), PORT_1(fn, pfx##133, sfx), \
62 PORT_1(fn, pfx##134, sfx), \
63 /* Port160 - Port178 */ \
64 PORT_10(fn, pfx##16, sfx), \
65 PORT_1(fn, pfx##170, sfx), PORT_1(fn, pfx##171, sfx), \
66 PORT_1(fn, pfx##172, sfx), PORT_1(fn, pfx##173, sfx), \
67 PORT_1(fn, pfx##174, sfx), PORT_1(fn, pfx##175, sfx), \
68 PORT_1(fn, pfx##176, sfx), PORT_1(fn, pfx##177, sfx), \
69 PORT_1(fn, pfx##178, sfx), \
70 /* Port192 - Port222 */ \
71 PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
72 PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
73 PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
74 PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
75 PORT_10(fn, pfx##20, sfx), \
76 PORT_10(fn, pfx##21, sfx), \
77 PORT_1(fn, pfx##220, sfx), PORT_1(fn, pfx##221, sfx), \
78 PORT_1(fn, pfx##222, sfx), \
79 /* Port224 - Port250 */ \
80 PORT_1(fn, pfx##224, sfx), PORT_1(fn, pfx##225, sfx), \
81 PORT_1(fn, pfx##226, sfx), PORT_1(fn, pfx##227, sfx), \
82 PORT_1(fn, pfx##228, sfx), PORT_1(fn, pfx##229, sfx), \
83 PORT_10(fn, pfx##23, sfx), \
84 PORT_10(fn, pfx##24, sfx), \
85 PORT_1(fn, pfx##250, sfx), \
86 /* Port256 - Port283 */ \
87 PORT_1(fn, pfx##256, sfx), PORT_1(fn, pfx##257, sfx), \
88 PORT_1(fn, pfx##258, sfx), PORT_1(fn, pfx##259, sfx), \
89 PORT_10(fn, pfx##26, sfx), \
90 PORT_10(fn, pfx##27, sfx), \
91 PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
92 PORT_1(fn, pfx##282, sfx), PORT_1(fn, pfx##283, sfx), \
93 /* Port288 - Port308 */ \
94 PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
95 PORT_10(fn, pfx##29, sfx), \
96 PORT_1(fn, pfx##300, sfx), PORT_1(fn, pfx##301, sfx), \
97 PORT_1(fn, pfx##302, sfx), PORT_1(fn, pfx##303, sfx), \
98 PORT_1(fn, pfx##304, sfx), PORT_1(fn, pfx##305, sfx), \
99 PORT_1(fn, pfx##306, sfx), PORT_1(fn, pfx##307, sfx), \
100 PORT_1(fn, pfx##308, sfx), \
101 /* Port320 - Port329 */ \
102 PORT_10(fn, pfx##32, sfx)
103
104
105enum {
106 PINMUX_RESERVED = 0,
107
108 /* PORT0_DATA -> PORT329_DATA */
109 PINMUX_DATA_BEGIN,
110 PORT_ALL(DATA),
111 PINMUX_DATA_END,
112
113 /* PORT0_IN -> PORT329_IN */
114 PINMUX_INPUT_BEGIN,
115 PORT_ALL(IN),
116 PINMUX_INPUT_END,
117
118 /* PORT0_IN_PU -> PORT329_IN_PU */
119 PINMUX_INPUT_PULLUP_BEGIN,
120 PORT_ALL(IN_PU),
121 PINMUX_INPUT_PULLUP_END,
122
123 /* PORT0_IN_PD -> PORT329_IN_PD */
124 PINMUX_INPUT_PULLDOWN_BEGIN,
125 PORT_ALL(IN_PD),
126 PINMUX_INPUT_PULLDOWN_END,
127
128 /* PORT0_OUT -> PORT329_OUT */
129 PINMUX_OUTPUT_BEGIN,
130 PORT_ALL(OUT),
131 PINMUX_OUTPUT_END,
132
133 PINMUX_FUNCTION_BEGIN,
134 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */
135 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */
136 PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */
137 PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */
138 PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */
139 PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */
140 PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */
141 PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */
142 PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */
143 PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */
144
145 MSEL1CR_31_0, MSEL1CR_31_1,
146 MSEL1CR_27_0, MSEL1CR_27_1,
147 MSEL1CR_25_0, MSEL1CR_25_1,
148 MSEL1CR_24_0, MSEL1CR_24_1,
149 MSEL1CR_22_0, MSEL1CR_22_1,
150 MSEL1CR_21_0, MSEL1CR_21_1,
151 MSEL1CR_20_0, MSEL1CR_20_1,
152 MSEL1CR_19_0, MSEL1CR_19_1,
153 MSEL1CR_18_0, MSEL1CR_18_1,
154 MSEL1CR_17_0, MSEL1CR_17_1,
155 MSEL1CR_16_0, MSEL1CR_16_1,
156 MSEL1CR_15_0, MSEL1CR_15_1,
157 MSEL1CR_14_0, MSEL1CR_14_1,
158 MSEL1CR_13_0, MSEL1CR_13_1,
159 MSEL1CR_12_0, MSEL1CR_12_1,
160 MSEL1CR_11_0, MSEL1CR_11_1,
161 MSEL1CR_10_0, MSEL1CR_10_1,
162 MSEL1CR_09_0, MSEL1CR_09_1,
163 MSEL1CR_08_0, MSEL1CR_08_1,
164 MSEL1CR_07_0, MSEL1CR_07_1,
165 MSEL1CR_06_0, MSEL1CR_06_1,
166 MSEL1CR_05_0, MSEL1CR_05_1,
167 MSEL1CR_04_0, MSEL1CR_04_1,
168 MSEL1CR_03_0, MSEL1CR_03_1,
169 MSEL1CR_02_0, MSEL1CR_02_1,
170 MSEL1CR_01_0, MSEL1CR_01_1,
171 MSEL1CR_00_0, MSEL1CR_00_1,
172
173 MSEL3CR_31_0, MSEL3CR_31_1,
174 MSEL3CR_28_0, MSEL3CR_28_1,
175 MSEL3CR_27_0, MSEL3CR_27_1,
176 MSEL3CR_26_0, MSEL3CR_26_1,
177 MSEL3CR_23_0, MSEL3CR_23_1,
178 MSEL3CR_22_0, MSEL3CR_22_1,
179 MSEL3CR_21_0, MSEL3CR_21_1,
180 MSEL3CR_20_0, MSEL3CR_20_1,
181 MSEL3CR_19_0, MSEL3CR_19_1,
182 MSEL3CR_18_0, MSEL3CR_18_1,
183 MSEL3CR_17_0, MSEL3CR_17_1,
184 MSEL3CR_16_0, MSEL3CR_16_1,
185 MSEL3CR_15_0, MSEL3CR_15_1,
186 MSEL3CR_12_0, MSEL3CR_12_1,
187 MSEL3CR_11_0, MSEL3CR_11_1,
188 MSEL3CR_10_0, MSEL3CR_10_1,
189 MSEL3CR_09_0, MSEL3CR_09_1,
190 MSEL3CR_06_0, MSEL3CR_06_1,
191 MSEL3CR_03_0, MSEL3CR_03_1,
192 MSEL3CR_01_0, MSEL3CR_01_1,
193 MSEL3CR_00_0, MSEL3CR_00_1,
194
195 MSEL4CR_30_0, MSEL4CR_30_1,
196 MSEL4CR_29_0, MSEL4CR_29_1,
197 MSEL4CR_28_0, MSEL4CR_28_1,
198 MSEL4CR_27_0, MSEL4CR_27_1,
199 MSEL4CR_26_0, MSEL4CR_26_1,
200 MSEL4CR_25_0, MSEL4CR_25_1,
201 MSEL4CR_24_0, MSEL4CR_24_1,
202 MSEL4CR_23_0, MSEL4CR_23_1,
203 MSEL4CR_22_0, MSEL4CR_22_1,
204 MSEL4CR_21_0, MSEL4CR_21_1,
205 MSEL4CR_20_0, MSEL4CR_20_1,
206 MSEL4CR_19_0, MSEL4CR_19_1,
207 MSEL4CR_18_0, MSEL4CR_18_1,
208 MSEL4CR_17_0, MSEL4CR_17_1,
209 MSEL4CR_16_0, MSEL4CR_16_1,
210 MSEL4CR_15_0, MSEL4CR_15_1,
211 MSEL4CR_14_0, MSEL4CR_14_1,
212 MSEL4CR_13_0, MSEL4CR_13_1,
213 MSEL4CR_12_0, MSEL4CR_12_1,
214 MSEL4CR_11_0, MSEL4CR_11_1,
215 MSEL4CR_10_0, MSEL4CR_10_1,
216 MSEL4CR_09_0, MSEL4CR_09_1,
217 MSEL4CR_07_0, MSEL4CR_07_1,
218 MSEL4CR_04_0, MSEL4CR_04_1,
219 MSEL4CR_01_0, MSEL4CR_01_1,
220
221 MSEL5CR_31_0, MSEL5CR_31_1,
222 MSEL5CR_30_0, MSEL5CR_30_1,
223 MSEL5CR_29_0, MSEL5CR_29_1,
224 MSEL5CR_28_0, MSEL5CR_28_1,
225 MSEL5CR_27_0, MSEL5CR_27_1,
226 MSEL5CR_26_0, MSEL5CR_26_1,
227 MSEL5CR_25_0, MSEL5CR_25_1,
228 MSEL5CR_24_0, MSEL5CR_24_1,
229 MSEL5CR_23_0, MSEL5CR_23_1,
230 MSEL5CR_22_0, MSEL5CR_22_1,
231 MSEL5CR_21_0, MSEL5CR_21_1,
232 MSEL5CR_20_0, MSEL5CR_20_1,
233 MSEL5CR_19_0, MSEL5CR_19_1,
234 MSEL5CR_18_0, MSEL5CR_18_1,
235 MSEL5CR_17_0, MSEL5CR_17_1,
236 MSEL5CR_16_0, MSEL5CR_16_1,
237 MSEL5CR_15_0, MSEL5CR_15_1,
238 MSEL5CR_14_0, MSEL5CR_14_1,
239 MSEL5CR_13_0, MSEL5CR_13_1,
240 MSEL5CR_12_0, MSEL5CR_12_1,
241 MSEL5CR_11_0, MSEL5CR_11_1,
242 MSEL5CR_10_0, MSEL5CR_10_1,
243 MSEL5CR_09_0, MSEL5CR_09_1,
244 MSEL5CR_08_0, MSEL5CR_08_1,
245 MSEL5CR_07_0, MSEL5CR_07_1,
246 MSEL5CR_06_0, MSEL5CR_06_1,
247
248 MSEL8CR_16_0, MSEL8CR_16_1,
249 MSEL8CR_01_0, MSEL8CR_01_1,
250 MSEL8CR_00_0, MSEL8CR_00_1,
251
252 PINMUX_FUNCTION_END,
253
254 PINMUX_MARK_BEGIN,
255
256
257#define F1(a) a##_MARK
258#define F2(a) a##_MARK
259#define F3(a) a##_MARK
260#define F4(a) a##_MARK
261#define F5(a) a##_MARK
262#define F6(a) a##_MARK
263#define F7(a) a##_MARK
264#define IRQ(a) IRQ##a##_MARK
265
266 F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */
267 F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1),
268 F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2),
269 F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3),
270 F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4),
271 F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5),
272 F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6),
273 F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7),
274 F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8),
275 F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9),
276 F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */
277 F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11),
278 F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12),
279 F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13),
280 F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14),
281 F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15),
282 F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0),
283 F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1),
284 F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2),
285 F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3),
286 F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */
287 F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5),
288 F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6),
289 F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7),
290 F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24),
291 F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
292 F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
293 F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN),
294 F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT),
295 F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB),
296 F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE),
297 F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */
298
299 F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */
300 F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS),
301 F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK),
302 F1(SCIFA1_RTS), F7(CSCIF1_RTS),
303 F1(SCIFA1_CTS), F7(CSCIF1_CTS),
304 F1(SCIFA1_SCK), F7(CSCIF1_SCK),
305 F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS),
306 F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS),
307 F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40),
308 F7(CHSCIF0_HSCK), /* Port40 */
309
310 F1(PDM0_DATA), /* Port64 */
311 F1(PDM1_DATA),
312 F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4),
313 IRQ(40),
314 F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX),
315 F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68),
316 F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69),
317 F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0),
318 F7(CHSCIF1_HRTS), /* Port70 */
319 F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1),
320 F7(CHSCIF1_HCTS),
321 F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX),
322 F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73),
323 F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0),
324 F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */
325 F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */
326
327 F1(KEYIN0), /* Port96 */
328 F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */
329 F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42),
330 F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3),
331 F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */
332 F2(KEYOUT7), F5(RFANAEN), IRQ(45),
333 F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46),
334 F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47),
335 F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48),
336 F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49),
337 F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX),
338 F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX),
339 F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */
340 F3(SF_PORT_0_121), F4(SCIFB3_TXD_121),
341 F1(SCIFB0_TXD), F7(CHSCIF0_HTX),
342 F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124),
343 F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0),
344 F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1),
345 F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC),
346 F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1),
347 F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD),
348 F5(SIM0_VOLTSEL1), /* Port130 */
349 F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK),
350 F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK),
351 F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1),
352 IRQ(20), /* Port160 */
353 IRQ(21), IRQ(22), IRQ(23),
354 F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3),
355 F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */
356 F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST),
357 IRQ(24), IRQ(25), IRQ(26), IRQ(27),
358 F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */
359 F1(A9), F2(MMCD1_6), IRQ(32),
360 F1(A8), F2(MMCD1_5), IRQ(33),
361 F1(A7), F2(MMCD1_4), IRQ(34),
362 F1(A6), F2(MMCD1_3), IRQ(35),
363 F1(A5), F2(MMCD1_2), IRQ(36),
364 F1(A4), F2(MMCD1_1), IRQ(37),
365 F1(A3), F2(MMCD1_0), IRQ(38),
366 F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */
367 F1(A1),
368 F1(A0), F2(BS),
369 F1(CKO), F2(MMCCLK1),
370 F1(CS0_N), F5(SIM0_GPO1),
371 F1(CS2_N), F5(SIM0_GPO2),
372 F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0),
373 F1(D15), F5(GIO_OUT15),
374 F1(D14), F5(GIO_OUT14),
375 F1(D13), F5(GIO_OUT13),
376 F1(D12), F5(GIO_OUT12), /* Port210 */
377 F1(D11), F5(WGM_TXP2),
378 F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK),
379 F1(D9), F2(VIO_D9), F5(GIO_OUT9),
380 F1(D8), F2(VIO_D8), F5(GIO_OUT8),
381 F1(D7), F2(VIO_D7), F5(GIO_OUT7),
382 F1(D6), F2(VIO_D6), F5(GIO_OUT6),
383 F1(D5), F2(VIO_D5), F5(GIO_OUT5_217),
384 F1(D4), F2(VIO_D4), F5(GIO_OUT4_218),
385 F1(D3), F2(VIO_D3), F5(GIO_OUT3_219),
386 F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */
387 F1(D1), F2(VIO_D1), F5(GIO_OUT1_221),
388 F1(D0), F2(VIO_D0), F5(GIO_OUT0_222),
389 F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2),
390 F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1),
391 F1(WE0_N), F2(RDWR_227),
392 F1(WE1_N), F5(SIM0_GPO0),
393 F1(PWMO), F2(VIO_CKO1_229),
394 F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */
395 F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232),
396 F2(VIO_CKO3_233), F4(SF_PORT_1_233),
397 F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234),
398 F1(FSIAISLD), F2(PDM3_DATA_235),
399 F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236),
400 F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT),
401 F1(FSIAOSLD), F2(PDM0_OUTDATA_239),
402 F1(FSIBISLD), /* Port240 */
403 F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242),
404 F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF),
405 F1(FSIBCK), F3(ISP_SHUTTER0_245),
406 F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248),
407 F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */
408 F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2),
409 F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */
410 F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262),
411 F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD),
412 F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1),
413 F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK),
414 F1(MSIOF1_SYNC), F4(MSIOF5_SYNC),
415 F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */
416 F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272),
417 F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0),
418 F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP),
419 F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */
420 F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282),
421 F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2),
422 F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */
423 F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2),
424 F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2),
425 F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD),
426 F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52),
427 F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD),
428 F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC),
429 F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK),
430 F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300),
431 F4(MSIOF6_SS1), /* Port300 */
432 F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1),
433 F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1),
434 F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1),
435 F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */
436 IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54),
437 IRQ(55), IRQ(56), IRQ(57),
438 PINMUX_MARK_END,
439};
440
441static const pinmux_enum_t pinmux_data[] = {
442 /* specify valid pin states for each pin in GPIO mode */
443
444 PORT_DATA_IO_PU_PD(0), PORT_DATA_IO_PU_PD(1),
445 PORT_DATA_IO_PU_PD(2), PORT_DATA_IO_PU_PD(3),
446 PORT_DATA_IO_PU_PD(4), PORT_DATA_IO_PU_PD(5),
447 PORT_DATA_IO_PU_PD(6), PORT_DATA_IO_PU_PD(7),
448 PORT_DATA_IO_PU_PD(8), PORT_DATA_IO_PU_PD(9),
449
450 PORT_DATA_IO_PU_PD(10), PORT_DATA_IO_PU_PD(11),
451 PORT_DATA_IO_PU_PD(12), PORT_DATA_IO_PU_PD(13),
452 PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15),
453 PORT_DATA_IO_PU_PD(16), PORT_DATA_IO_PU_PD(17),
454 PORT_DATA_IO_PU_PD(18), PORT_DATA_IO_PU_PD(19),
455
456 PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PU_PD(21),
457 PORT_DATA_IO_PU_PD(22), PORT_DATA_IO_PU_PD(23),
458 PORT_DATA_IO_PU_PD(24), PORT_DATA_IO_PU_PD(25),
459 PORT_DATA_IO_PU_PD(26), PORT_DATA_IO_PU_PD(27),
460 PORT_DATA_IO_PU_PD(28), PORT_DATA_IO_PU_PD(29),
461
462 PORT_DATA_IO_PU_PD(30), PORT_DATA_IO_PU_PD(32),
463 PORT_DATA_IO_PU_PD(33), PORT_DATA_IO_PU_PD(34),
464 PORT_DATA_IO_PU_PD(35), PORT_DATA_IO_PU_PD(36),
465 PORT_DATA_IO_PU_PD(37), PORT_DATA_IO_PU_PD(38),
466 PORT_DATA_IO_PU_PD(39), PORT_DATA_IO_PU_PD(40),
467
468 PORT_DATA_IO_PU_PD(64), PORT_DATA_IO_PU_PD(65),
469 PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
470 PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
471
472 PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
473 PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
474 PORT_DATA_O(74), PORT_DATA_IO_PU_PD(75),
475 PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
476 PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
477
478 PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
479 PORT_DATA_IO_PU_PD(82), PORT_DATA_IO_PU_PD(83),
480 PORT_DATA_IO_PU_PD(84), PORT_DATA_IO_PU_PD(85),
481
482 PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
483 PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),
484
485 PORT_DATA_IO_PU_PD(100), PORT_DATA_IO_PU_PD(101),
486 PORT_DATA_IO_PU_PD(102), PORT_DATA_IO_PU_PD(103),
487 PORT_DATA_IO_PU_PD(104), PORT_DATA_IO_PU_PD(105),
488 PORT_DATA_IO_PU_PD(106), PORT_DATA_IO_PU_PD(107),
489 PORT_DATA_IO_PU_PD(108), PORT_DATA_IO_PU_PD(109),
490
491 PORT_DATA_IO_PU_PD(110), PORT_DATA_IO_PU_PD(111),
492 PORT_DATA_IO_PU_PD(112), PORT_DATA_IO_PU_PD(113),
493 PORT_DATA_IO_PU_PD(114), PORT_DATA_IO_PU_PD(115),
494 PORT_DATA_IO_PU_PD(116), PORT_DATA_IO_PU_PD(117),
495 PORT_DATA_IO_PU_PD(118), PORT_DATA_IO_PU_PD(119),
496
497 PORT_DATA_IO_PU_PD(120), PORT_DATA_IO_PU_PD(121),
498 PORT_DATA_IO_PU_PD(122), PORT_DATA_IO_PU_PD(123),
499 PORT_DATA_IO_PU_PD(124), PORT_DATA_IO_PU_PD(125),
500 PORT_DATA_IO_PU_PD(126),
501 PORT_DATA_IO_PU_PD(128), PORT_DATA_IO_PU_PD(129),
502
503 PORT_DATA_IO_PU_PD(130), PORT_DATA_IO_PU_PD(131),
504 PORT_DATA_IO_PU_PD(132), PORT_DATA_IO_PU_PD(133),
505 PORT_DATA_IO_PU_PD(134),
506
507 PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PU_PD(161),
508 PORT_DATA_IO_PU_PD(162), PORT_DATA_IO_PU_PD(163),
509 PORT_DATA_IO_PU_PD(164), PORT_DATA_IO_PU_PD(165),
510 PORT_DATA_IO_PU_PD(166), PORT_DATA_IO_PU_PD(167),
511 PORT_DATA_IO_PU_PD(168), PORT_DATA_IO_PU_PD(169),
512
513 PORT_DATA_IO_PU_PD(170), PORT_DATA_IO_PU_PD(171),
514 PORT_DATA_IO_PU_PD(172), PORT_DATA_IO_PU_PD(173),
515 PORT_DATA_IO_PU_PD(174), PORT_DATA_IO_PU_PD(175),
516 PORT_DATA_IO_PU_PD(176), PORT_DATA_IO_PU_PD(177),
517 PORT_DATA_IO_PU_PD(178),
518
519 PORT_DATA_IO_PU_PD(192), PORT_DATA_IO_PU_PD(193),
520 PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PU_PD(195),
521 PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PU_PD(197),
522 PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),
523
524 PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU_PD(201),
525 PORT_DATA_IO_PU_PD(202), PORT_DATA_IO_PU_PD(203),
526 PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
527 PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
528 PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PU_PD(209),
529
530 PORT_DATA_IO_PU_PD(210), PORT_DATA_IO_PU_PD(211),
531 PORT_DATA_IO_PU_PD(212), PORT_DATA_IO_PU_PD(213),
532 PORT_DATA_IO_PU_PD(214), PORT_DATA_IO_PU_PD(215),
533 PORT_DATA_IO_PU_PD(216), PORT_DATA_IO_PU_PD(217),
534 PORT_DATA_IO_PU_PD(218), PORT_DATA_IO_PU_PD(219),
535
536 PORT_DATA_IO_PU_PD(220), PORT_DATA_IO_PU_PD(221),
537 PORT_DATA_IO_PU_PD(222), PORT_DATA_IO_PU_PD(224),
538 PORT_DATA_IO_PU_PD(225), PORT_DATA_IO_PU_PD(226),
539 PORT_DATA_IO_PU_PD(227), PORT_DATA_IO_PU_PD(228),
540 PORT_DATA_IO_PU_PD(229),
541
542 PORT_DATA_IO_PU_PD(230), PORT_DATA_IO_PU_PD(231),
543 PORT_DATA_IO_PU_PD(232), PORT_DATA_IO_PU_PD(233),
544 PORT_DATA_IO_PU_PD(234), PORT_DATA_IO_PU_PD(235),
545 PORT_DATA_IO_PU_PD(236), PORT_DATA_IO_PU_PD(237),
546 PORT_DATA_IO_PU_PD(238), PORT_DATA_IO_PU_PD(239),
547
548 PORT_DATA_IO_PU_PD(240), PORT_DATA_IO_PU_PD(241),
549 PORT_DATA_IO_PU_PD(242), PORT_DATA_IO_PU_PD(243),
550 PORT_DATA_IO_PU_PD(244), PORT_DATA_IO_PU_PD(245),
551 PORT_DATA_IO_PU_PD(246), PORT_DATA_IO_PU_PD(247),
552 PORT_DATA_IO_PU_PD(248), PORT_DATA_IO_PU_PD(249),
553
554 PORT_DATA_IO_PU_PD(250),
555 PORT_DATA_IO_PU_PD(256), PORT_DATA_IO_PU_PD(257),
556 PORT_DATA_IO_PU_PD(258), PORT_DATA_IO_PU_PD(259),
557
558 PORT_DATA_IO_PU_PD(260), PORT_DATA_IO_PU_PD(261),
559 PORT_DATA_IO_PU_PD(262), PORT_DATA_IO_PU_PD(263),
560 PORT_DATA_IO_PU_PD(264), PORT_DATA_IO_PU_PD(265),
561 PORT_DATA_IO_PU_PD(266), PORT_DATA_IO_PU_PD(267),
562 PORT_DATA_IO_PU_PD(268), PORT_DATA_IO_PU_PD(269),
563
564 PORT_DATA_IO_PU_PD(270), PORT_DATA_IO_PU_PD(271),
565 PORT_DATA_IO_PU_PD(272), PORT_DATA_IO_PU_PD(273),
566 PORT_DATA_IO_PU_PD(274), PORT_DATA_IO_PU_PD(275),
567 PORT_DATA_IO_PU_PD(276), PORT_DATA_IO_PU_PD(277),
568 PORT_DATA_IO_PU_PD(278), PORT_DATA_IO_PU_PD(279),
569
570 PORT_DATA_IO_PU_PD(280), PORT_DATA_IO_PU_PD(281),
571 PORT_DATA_IO_PU_PD(282), PORT_DATA_IO_PU_PD(283),
572 PORT_DATA_O(288), PORT_DATA_IO_PU_PD(289),
573
574 PORT_DATA_IO_PU_PD(290), PORT_DATA_IO_PU_PD(291),
575 PORT_DATA_IO_PU_PD(292), PORT_DATA_IO_PU_PD(293),
576 PORT_DATA_IO_PU_PD(294), PORT_DATA_IO_PU_PD(295),
577 PORT_DATA_IO_PU_PD(296), PORT_DATA_IO_PU_PD(297),
578 PORT_DATA_IO_PU_PD(298), PORT_DATA_IO_PU_PD(299),
579
580 PORT_DATA_IO_PU_PD(300), PORT_DATA_IO_PU_PD(301),
581 PORT_DATA_IO_PU_PD(302), PORT_DATA_IO_PU_PD(303),
582 PORT_DATA_IO_PU_PD(304), PORT_DATA_IO_PU_PD(305),
583 PORT_DATA_IO_PU_PD(306), PORT_DATA_IO_PU_PD(307),
584 PORT_DATA_IO_PU_PD(308),
585
586 PORT_DATA_IO_PU_PD(320), PORT_DATA_IO_PU_PD(321),
587 PORT_DATA_IO_PU_PD(322), PORT_DATA_IO_PU_PD(323),
588 PORT_DATA_IO_PU_PD(324), PORT_DATA_IO_PU_PD(325),
589 PORT_DATA_IO_PU_PD(326), PORT_DATA_IO_PU_PD(327),
590 PORT_DATA_IO_PU_PD(328), PORT_DATA_IO_PU_PD(329),
591
592 /* Port0 */
593 PINMUX_DATA(LCDD0_MARK, PORT0_FN1),
594 PINMUX_DATA(PDM2_CLK_0_MARK, PORT0_FN3),
595 PINMUX_DATA(DU0_DR0_MARK, PORT0_FN7),
596 PINMUX_DATA(IRQ0_MARK, PORT0_FN0),
597
598 /* Port1 */
599 PINMUX_DATA(LCDD1_MARK, PORT1_FN1),
600 PINMUX_DATA(PDM2_DATA_1_MARK, PORT1_FN3, MSEL3CR_12_0),
601 PINMUX_DATA(DU0_DR19_MARK, PORT1_FN7),
602 PINMUX_DATA(IRQ1_MARK, PORT1_FN0),
603
604 /* Port2 */
605 PINMUX_DATA(LCDD2_MARK, PORT2_FN1),
606 PINMUX_DATA(PDM3_CLK_2_MARK, PORT2_FN3),
607 PINMUX_DATA(DU0_DR2_MARK, PORT2_FN7),
608 PINMUX_DATA(IRQ2_MARK, PORT2_FN0),
609
610 /* Port3 */
611 PINMUX_DATA(LCDD3_MARK, PORT3_FN1),
612 PINMUX_DATA(PDM3_DATA_3_MARK, PORT3_FN3, MSEL3CR_12_0),
613 PINMUX_DATA(DU0_DR3_MARK, PORT3_FN7),
614 PINMUX_DATA(IRQ3_MARK, PORT3_FN0),
615
616 /* Port4 */
617 PINMUX_DATA(LCDD4_MARK, PORT4_FN1),
618 PINMUX_DATA(PDM4_CLK_4_MARK, PORT4_FN3),
619 PINMUX_DATA(DU0_DR4_MARK, PORT4_FN7),
620 PINMUX_DATA(IRQ4_MARK, PORT4_FN0),
621
622 /* Port5 */
623 PINMUX_DATA(LCDD5_MARK, PORT5_FN1),
624 PINMUX_DATA(PDM4_DATA_5_MARK, PORT5_FN3, MSEL3CR_12_0),
625 PINMUX_DATA(DU0_DR5_MARK, PORT5_FN7),
626 PINMUX_DATA(IRQ5_MARK, PORT5_FN0),
627
628 /* Port6 */
629 PINMUX_DATA(LCDD6_MARK, PORT6_FN1),
630 PINMUX_DATA(PDM0_OUTCLK_6_MARK, PORT6_FN3),
631 PINMUX_DATA(DU0_DR6_MARK, PORT6_FN7),
632 PINMUX_DATA(IRQ6_MARK, PORT6_FN0),
633
634 /* Port7 */
635 PINMUX_DATA(LCDD7_MARK, PORT7_FN1),
636 PINMUX_DATA(PDM0_OUTDATA_7_MARK, PORT7_FN3),
637 PINMUX_DATA(DU0_DR7_MARK, PORT7_FN7),
638 PINMUX_DATA(IRQ7_MARK, PORT7_FN0),
639
640 /* Port8 */
641 PINMUX_DATA(LCDD8_MARK, PORT8_FN1),
642 PINMUX_DATA(PDM1_OUTCLK_8_MARK, PORT8_FN3),
643 PINMUX_DATA(DU0_DG0_MARK, PORT8_FN7),
644 PINMUX_DATA(IRQ8_MARK, PORT8_FN0),
645
646 /* Port9 */
647 PINMUX_DATA(LCDD9_MARK, PORT9_FN1),
648 PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3),
649 PINMUX_DATA(DU0_DG1_MARK, PORT9_FN7),
650 PINMUX_DATA(IRQ9_MARK, PORT9_FN0),
651
652 /* Port10 */
653 PINMUX_DATA(LCDD10_MARK, PORT10_FN1),
654 PINMUX_DATA(FSICCK_MARK, PORT10_FN3),
655 PINMUX_DATA(DU0_DG2_MARK, PORT10_FN7),
656 PINMUX_DATA(IRQ10_MARK, PORT10_FN0),
657
658 /* Port11 */
659 PINMUX_DATA(LCDD11_MARK, PORT11_FN1),
660 PINMUX_DATA(FSICISLD_MARK, PORT11_FN3),
661 PINMUX_DATA(DU0_DG3_MARK, PORT11_FN7),
662 PINMUX_DATA(IRQ11_MARK, PORT11_FN0),
663
664 /* Port12 */
665 PINMUX_DATA(LCDD12_MARK, PORT12_FN1),
666 PINMUX_DATA(FSICOMC_MARK, PORT12_FN3),
667 PINMUX_DATA(DU0_DG4_MARK, PORT12_FN7),
668 PINMUX_DATA(IRQ12_MARK, PORT12_FN0),
669
670 /* Port13 */
671 PINMUX_DATA(LCDD13_MARK, PORT13_FN1),
672 PINMUX_DATA(FSICOLR_MARK, PORT13_FN3),
673 PINMUX_DATA(FSICILR_MARK, PORT13_FN4),
674 PINMUX_DATA(DU0_DG5_MARK, PORT13_FN7),
675 PINMUX_DATA(IRQ13_MARK, PORT13_FN0),
676
677 /* Port14 */
678 PINMUX_DATA(LCDD14_MARK, PORT14_FN1),
679 PINMUX_DATA(FSICOBT_MARK, PORT14_FN3),
680 PINMUX_DATA(FSICIBT_MARK, PORT14_FN4),
681 PINMUX_DATA(DU0_DG6_MARK, PORT14_FN7),
682 PINMUX_DATA(IRQ14_MARK, PORT14_FN0),
683
684 /* Port15 */
685 PINMUX_DATA(LCDD15_MARK, PORT15_FN1),
686 PINMUX_DATA(FSICOSLD_MARK, PORT15_FN3),
687 PINMUX_DATA(DU0_DG7_MARK, PORT15_FN7),
688 PINMUX_DATA(IRQ15_MARK, PORT15_FN0),
689
690 /* Port16 */
691 PINMUX_DATA(LCDD16_MARK, PORT16_FN1),
692 PINMUX_DATA(TPU1TO1_MARK, PORT16_FN4),
693 PINMUX_DATA(DU0_DB0_MARK, PORT16_FN7),
694
695 /* Port17 */
696 PINMUX_DATA(LCDD17_MARK, PORT17_FN1),
697 PINMUX_DATA(SF_IRQ_00_MARK, PORT17_FN4),
698 PINMUX_DATA(DU0_DB1_MARK, PORT17_FN7),
699
700 /* Port18 */
701 PINMUX_DATA(LCDD18_MARK, PORT18_FN1),
702 PINMUX_DATA(SF_IRQ_01_MARK, PORT18_FN4),
703 PINMUX_DATA(DU0_DB2_MARK, PORT18_FN7),
704
705 /* Port19 */
706 PINMUX_DATA(LCDD19_MARK, PORT19_FN1),
707 PINMUX_DATA(SCIFB3_RTS_19_MARK, PORT19_FN3),
708 PINMUX_DATA(DU0_DB3_MARK, PORT19_FN7),
709
710 /* Port20 */
711 PINMUX_DATA(LCDD20_MARK, PORT20_FN1),
712 PINMUX_DATA(SCIFB3_CTS_20_MARK, PORT20_FN3, MSEL3CR_09_0),
713 PINMUX_DATA(DU0_DB4_MARK, PORT20_FN7),
714
715 /* Port21 */
716 PINMUX_DATA(LCDD21_MARK, PORT21_FN1),
717 PINMUX_DATA(SCIFB3_TXD_21_MARK, PORT21_FN3, MSEL3CR_09_0),
718 PINMUX_DATA(DU0_DB5_MARK, PORT21_FN7),
719
720 /* Port22 */
721 PINMUX_DATA(LCDD22_MARK, PORT22_FN1),
722 PINMUX_DATA(SCIFB3_RXD_22_MARK, PORT22_FN3, MSEL3CR_09_0),
723 PINMUX_DATA(DU0_DB6_MARK, PORT22_FN7),
724
725 /* Port23 */
726 PINMUX_DATA(LCDD23_MARK, PORT23_FN1),
727 PINMUX_DATA(SCIFB3_SCK_23_MARK, PORT23_FN3),
728 PINMUX_DATA(DU0_DB7_MARK, PORT23_FN7),
729
730 /* Port24 */
731 PINMUX_DATA(LCDHSYN_MARK, PORT24_FN1),
732 PINMUX_DATA(LCDCS_MARK, PORT24_FN2),
733 PINMUX_DATA(SCIFB1_RTS_24_MARK, PORT24_FN3),
734 PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK, PORT24_FN7),
735
736 /* Port25 */
737 PINMUX_DATA(LCDVSYN_MARK, PORT25_FN1),
738 PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0),
739 PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK, PORT25_FN7),
740
741 /* Port26 */
742 PINMUX_DATA(LCDDCK_MARK, PORT26_FN1),
743 PINMUX_DATA(LCDWR_MARK, PORT26_FN2),
744 PINMUX_DATA(SCIFB1_TXD_26_MARK, PORT26_FN3, MSEL3CR_11_0),
745 PINMUX_DATA(DU0_DOTCLKIN_MARK, PORT26_FN7),
746
747 /* Port27 */
748 PINMUX_DATA(LCDDISP_MARK, PORT27_FN1),
749 PINMUX_DATA(LCDRS_MARK, PORT27_FN2),
750 PINMUX_DATA(SCIFB1_RXD_27_MARK, PORT27_FN3, MSEL3CR_11_0),
751 PINMUX_DATA(DU0_DOTCLKOUT_MARK, PORT27_FN7),
752
753 /* Port28 */
754 PINMUX_DATA(LCDRD_N_MARK, PORT28_FN1),
755 PINMUX_DATA(SCIFB1_SCK_28_MARK, PORT28_FN3),
756 PINMUX_DATA(DU0_DOTCLKOUTB_MARK, PORT28_FN7),
757
758 /* Port29 */
759 PINMUX_DATA(LCDLCLK_MARK, PORT29_FN1),
760 PINMUX_DATA(SF_IRQ_02_MARK, PORT29_FN4),
761 PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK, PORT29_FN7),
762
763 /* Port30 */
764 PINMUX_DATA(LCDDON_MARK, PORT30_FN1),
765 PINMUX_DATA(SF_IRQ_03_MARK, PORT30_FN4),
766 PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK, PORT30_FN7),
767
768 /* Port32 */
769 PINMUX_DATA(SCIFA0_RTS_MARK, PORT32_FN1),
770 PINMUX_DATA(SIM0_DET_MARK, PORT32_FN5),
771 PINMUX_DATA(CSCIF0_RTS_MARK, PORT32_FN7),
772
773 /* Port33 */
774 PINMUX_DATA(SCIFA0_CTS_MARK, PORT33_FN1),
775 PINMUX_DATA(SIM1_DET_MARK, PORT33_FN5),
776 PINMUX_DATA(CSCIF0_CTS_MARK, PORT33_FN7),
777
778 /* Port34 */
779 PINMUX_DATA(SCIFA0_SCK_MARK, PORT34_FN1),
780 PINMUX_DATA(SIM0_PWRON_MARK, PORT34_FN5),
781 PINMUX_DATA(CSCIF0_SCK_MARK, PORT34_FN7),
782
783 /* Port35 */
784 PINMUX_DATA(SCIFA1_RTS_MARK, PORT35_FN1),
785 PINMUX_DATA(CSCIF1_RTS_MARK, PORT35_FN7),
786
787 /* Port36 */
788 PINMUX_DATA(SCIFA1_CTS_MARK, PORT36_FN1),
789 PINMUX_DATA(CSCIF1_CTS_MARK, PORT36_FN7),
790
791 /* Port37 */
792 PINMUX_DATA(SCIFA1_SCK_MARK, PORT37_FN1),
793 PINMUX_DATA(CSCIF1_SCK_MARK, PORT37_FN7),
794
795 /* Port38 */
796 PINMUX_DATA(SCIFB0_RTS_MARK, PORT38_FN1),
797 PINMUX_DATA(TPU0TO1_MARK, PORT38_FN3),
798 PINMUX_DATA(SCIFB3_RTS_38_MARK, PORT38_FN4),
799 PINMUX_DATA(CHSCIF0_HRTS_MARK, PORT38_FN7),
800
801 /* Port39 */
802 PINMUX_DATA(SCIFB0_CTS_MARK, PORT39_FN1),
803 PINMUX_DATA(TPU0TO2_MARK, PORT39_FN3),
804 PINMUX_DATA(SCIFB3_CTS_39_MARK, PORT39_FN4, MSEL3CR_09_1),
805 PINMUX_DATA(CHSCIF0_HCTS_MARK, PORT39_FN7),
806
807 /* Port40 */
808 PINMUX_DATA(SCIFB0_SCK_MARK, PORT40_FN1),
809 PINMUX_DATA(TPU0TO3_MARK, PORT40_FN3),
810 PINMUX_DATA(SCIFB3_SCK_40_MARK, PORT40_FN4),
811 PINMUX_DATA(CHSCIF0_HSCK_MARK, PORT40_FN7),
812
813 /* Port64 */
814 PINMUX_DATA(PDM0_DATA_MARK, PORT64_FN1),
815
816 /* Port65 */
817 PINMUX_DATA(PDM1_DATA_MARK, PORT65_FN1),
818
819 /* Port66 */
820 PINMUX_DATA(HSI_RX_WAKE_MARK, PORT66_FN1),
821 PINMUX_DATA(SCIFB2_CTS_66_MARK, PORT66_FN2, MSEL3CR_10_0),
822 PINMUX_DATA(MSIOF3_SYNC_MARK, PORT66_FN3),
823 PINMUX_DATA(GenIO4_MARK, PORT66_FN5),
824 PINMUX_DATA(IRQ40_MARK, PORT66_FN0),
825
826 /* Port67 */
827 PINMUX_DATA(HSI_RX_READY_MARK, PORT67_FN1),
828 PINMUX_DATA(SCIFB1_TXD_67_MARK, PORT67_FN2, MSEL3CR_11_1),
829 PINMUX_DATA(GIO_OUT3_67_MARK, PORT67_FN5),
830 PINMUX_DATA(CHSCIF1_HTX_MARK, PORT67_FN7),
831
832 /* Port68 */
833 PINMUX_DATA(HSI_RX_FLAG_MARK, PORT68_FN1),
834 PINMUX_DATA(SCIFB2_TXD_68_MARK, PORT68_FN2, MSEL3CR_10_0),
835 PINMUX_DATA(MSIOF3_TXD_MARK, PORT68_FN3),
836 PINMUX_DATA(GIO_OUT4_68_MARK, PORT68_FN5),
837
838 /* Port69 */
839 PINMUX_DATA(HSI_RX_DATA_MARK, PORT69_FN1),
840 PINMUX_DATA(SCIFB2_RXD_69_MARK, PORT69_FN2, MSEL3CR_10_0),
841 PINMUX_DATA(MSIOF3_RXD_MARK, PORT69_FN3),
842 PINMUX_DATA(GIO_OUT5_69_MARK, PORT69_FN5),
843
844 /* Port70 */
845 PINMUX_DATA(HSI_TX_FLAG_MARK, PORT70_FN1),
846 PINMUX_DATA(SCIFB1_RTS_70_MARK, PORT70_FN2),
847 PINMUX_DATA(GIO_OUT1_70_MARK, PORT70_FN5),
848 PINMUX_DATA(HSIC_TSTCLK0_MARK, PORT70_FN6),
849 PINMUX_DATA(CHSCIF1_HRTS_MARK, PORT70_FN7),
850
851 /* Port71 */
852 PINMUX_DATA(HSI_TX_DATA_MARK, PORT71_FN1),
853 PINMUX_DATA(SCIFB1_CTS_71_MARK, PORT71_FN2, MSEL3CR_11_1),
854 PINMUX_DATA(GIO_OUT2_71_MARK, PORT71_FN5),
855 PINMUX_DATA(HSIC_TSTCLK1_MARK, PORT71_FN6),
856 PINMUX_DATA(CHSCIF1_HCTS_MARK, PORT71_FN7),
857
858 /* Port72 */
859 PINMUX_DATA(HSI_TX_WAKE_MARK, PORT72_FN1),
860 PINMUX_DATA(SCIFB1_RXD_72_MARK, PORT72_FN2, MSEL3CR_11_1),
861 PINMUX_DATA(GenIO8_MARK, PORT72_FN5),
862 PINMUX_DATA(CHSCIF1_HRX_MARK, PORT72_FN7),
863
864 /* Port73 */
865 PINMUX_DATA(HSI_TX_READY_MARK, PORT73_FN1),
866 PINMUX_DATA(SCIFB2_RTS_73_MARK, PORT73_FN2),
867 PINMUX_DATA(MSIOF3_SCK_MARK, PORT73_FN3),
868 PINMUX_DATA(GIO_OUT0_73_MARK, PORT73_FN5),
869
870 /* Port74 - Port85 */
871 PINMUX_DATA(IRDA_OUT_MARK, PORT74_FN1),
872 PINMUX_DATA(IRDA_IN_MARK, PORT75_FN1),
873 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT76_FN1),
874 PINMUX_DATA(TPU0TO0_MARK, PORT77_FN1),
875 PINMUX_DATA(DIGRFEN_MARK, PORT78_FN1),
876 PINMUX_DATA(GPS_TIMESTAMP_MARK, PORT79_FN1),
877 PINMUX_DATA(TXP_MARK, PORT80_FN1),
878 PINMUX_DATA(TXP2_MARK, PORT81_FN1),
879 PINMUX_DATA(COEX_0_MARK, PORT82_FN1),
880 PINMUX_DATA(COEX_1_MARK, PORT83_FN1),
881 PINMUX_DATA(IRQ19_MARK, PORT84_FN0),
882 PINMUX_DATA(IRQ18_MARK, PORT85_FN0),
883
884 /* Port96 - Port101 */
885 PINMUX_DATA(KEYIN0_MARK, PORT96_FN1),
886 PINMUX_DATA(KEYIN1_MARK, PORT97_FN1),
887 PINMUX_DATA(KEYIN2_MARK, PORT98_FN1),
888 PINMUX_DATA(KEYIN3_MARK, PORT99_FN1),
889 PINMUX_DATA(KEYIN4_MARK, PORT100_FN1),
890 PINMUX_DATA(KEYIN5_MARK, PORT101_FN1),
891
892 /* Port102 */
893 PINMUX_DATA(KEYIN6_MARK, PORT102_FN1),
894 PINMUX_DATA(IRQ41_MARK, PORT102_FN0),
895
896 /* Port103 */
897 PINMUX_DATA(KEYIN7_MARK, PORT103_FN1),
898 PINMUX_DATA(IRQ42_MARK, PORT103_FN0),
899
900 /* Port104 - Port108 */
901 PINMUX_DATA(KEYOUT0_MARK, PORT104_FN2),
902 PINMUX_DATA(KEYOUT1_MARK, PORT105_FN2),
903 PINMUX_DATA(KEYOUT2_MARK, PORT106_FN2),
904 PINMUX_DATA(KEYOUT3_MARK, PORT107_FN2),
905 PINMUX_DATA(KEYOUT4_MARK, PORT108_FN2),
906
907 /* Port109 */
908 PINMUX_DATA(KEYOUT5_MARK, PORT109_FN2),
909 PINMUX_DATA(IRQ43_MARK, PORT109_FN0),
910
911 /* Port110 */
912 PINMUX_DATA(KEYOUT6_MARK, PORT110_FN2),
913 PINMUX_DATA(IRQ44_MARK, PORT110_FN0),
914
915 /* Port111 */
916 PINMUX_DATA(KEYOUT7_MARK, PORT111_FN2),
917 PINMUX_DATA(RFANAEN_MARK, PORT111_FN5),
918 PINMUX_DATA(IRQ45_MARK, PORT111_FN0),
919
920 /* Port112 */
921 PINMUX_DATA(KEYIN8_MARK, PORT112_FN1),
922 PINMUX_DATA(KEYOUT8_MARK, PORT112_FN2),
923 PINMUX_DATA(SF_IRQ_04_MARK, PORT112_FN4),
924 PINMUX_DATA(IRQ46_MARK, PORT112_FN0),
925
926 /* Port113 */
927 PINMUX_DATA(KEYIN9_MARK, PORT113_FN1),
928 PINMUX_DATA(KEYOUT9_MARK, PORT113_FN2),
929 PINMUX_DATA(SF_IRQ_05_MARK, PORT113_FN4),
930 PINMUX_DATA(IRQ47_MARK, PORT113_FN0),
931
932 /* Port114 */
933 PINMUX_DATA(KEYIN10_MARK, PORT114_FN1),
934 PINMUX_DATA(KEYOUT10_MARK, PORT114_FN2),
935 PINMUX_DATA(SF_IRQ_06_MARK, PORT114_FN4),
936 PINMUX_DATA(IRQ48_MARK, PORT114_FN0),
937
938 /* Port115 */
939 PINMUX_DATA(KEYIN11_MARK, PORT115_FN1),
940 PINMUX_DATA(KEYOUT11_MARK, PORT115_FN2),
941 PINMUX_DATA(SF_IRQ_07_MARK, PORT115_FN4),
942 PINMUX_DATA(IRQ49_MARK, PORT115_FN0),
943
944 /* Port116 */
945 PINMUX_DATA(SCIFA0_TXD_MARK, PORT116_FN1),
946 PINMUX_DATA(CSCIF0_TX_MARK, PORT116_FN7),
947
948 /* Port117 */
949 PINMUX_DATA(SCIFA0_RXD_MARK, PORT117_FN1),
950 PINMUX_DATA(CSCIF0_RX_MARK, PORT117_FN7),
951
952 /* Port118 */
953 PINMUX_DATA(SCIFA1_TXD_MARK, PORT118_FN1),
954 PINMUX_DATA(CSCIF1_TX_MARK, PORT118_FN7),
955
956 /* Port119 */
957 PINMUX_DATA(SCIFA1_RXD_MARK, PORT119_FN1),
958 PINMUX_DATA(CSCIF1_RX_MARK, PORT119_FN7),
959
960 /* Port120 */
961 PINMUX_DATA(SF_PORT_1_120_MARK, PORT120_FN3),
962 PINMUX_DATA(SCIFB3_RXD_120_MARK, PORT120_FN4, MSEL3CR_09_1),
963 PINMUX_DATA(DU0_CDE_MARK, PORT120_FN7),
964
965 /* Port121 */
966 PINMUX_DATA(SF_PORT_0_121_MARK, PORT121_FN3),
967 PINMUX_DATA(SCIFB3_TXD_121_MARK, PORT121_FN4, MSEL3CR_09_1),
968
969 /* Port122 */
970 PINMUX_DATA(SCIFB0_TXD_MARK, PORT122_FN1),
971 PINMUX_DATA(CHSCIF0_HTX_MARK, PORT122_FN7),
972
973 /* Port123 */
974 PINMUX_DATA(SCIFB0_RXD_MARK, PORT123_FN1),
975 PINMUX_DATA(CHSCIF0_HRX_MARK, PORT123_FN7),
976
977 /* Port124 */
978 PINMUX_DATA(ISP_STROBE_124_MARK, PORT124_FN3),
979
980 /* Port125 */
981 PINMUX_DATA(STP_ISD_0_MARK, PORT125_FN1),
982 PINMUX_DATA(PDM4_CLK_125_MARK, PORT125_FN2),
983 PINMUX_DATA(MSIOF2_TXD_MARK, PORT125_FN3),
984 PINMUX_DATA(SIM0_VOLTSEL0_MARK, PORT125_FN5),
985
986 /* Port126 */
987 PINMUX_DATA(TS_SDEN_MARK, PORT126_FN1),
988 PINMUX_DATA(MSIOF7_SYNC_MARK, PORT126_FN2),
989 PINMUX_DATA(STP_ISEN_1_MARK, PORT126_FN3),
990
991 /* Port128 */
992 PINMUX_DATA(STP_ISEN_0_MARK, PORT128_FN1),
993 PINMUX_DATA(PDM1_OUTDATA_128_MARK, PORT128_FN2),
994 PINMUX_DATA(MSIOF2_SYNC_MARK, PORT128_FN3),
995 PINMUX_DATA(SIM1_VOLTSEL1_MARK, PORT128_FN5),
996
997 /* Port129 */
998 PINMUX_DATA(TS_SPSYNC_MARK, PORT129_FN1),
999 PINMUX_DATA(MSIOF7_RXD_MARK, PORT129_FN2),
1000 PINMUX_DATA(STP_ISSYNC_1_MARK, PORT129_FN3),
1001
1002 /* Port130 */
1003 PINMUX_DATA(STP_ISSYNC_0_MARK, PORT130_FN1),
1004 PINMUX_DATA(PDM4_DATA_130_MARK, PORT130_FN2, MSEL3CR_12_1),
1005 PINMUX_DATA(MSIOF2_RXD_MARK, PORT130_FN3),
1006 PINMUX_DATA(SIM0_VOLTSEL1_MARK, PORT130_FN5),
1007
1008 /* Port131 */
1009 PINMUX_DATA(STP_OPWM_0_MARK, PORT131_FN1),
1010 PINMUX_DATA(SIM1_PWRON_MARK, PORT131_FN5),
1011
1012 /* Port132 */
1013 PINMUX_DATA(TS_SCK_MARK, PORT132_FN1),
1014 PINMUX_DATA(MSIOF7_SCK_MARK, PORT132_FN2),
1015 PINMUX_DATA(STP_ISCLK_1_MARK, PORT132_FN3),
1016
1017 /* Port133 */
1018 PINMUX_DATA(STP_ISCLK_0_MARK, PORT133_FN1),
1019 PINMUX_DATA(PDM1_OUTCLK_133_MARK, PORT133_FN2),
1020 PINMUX_DATA(MSIOF2_SCK_MARK, PORT133_FN3),
1021 PINMUX_DATA(SIM1_VOLTSEL0_MARK, PORT133_FN5),
1022
1023 /* Port134 */
1024 PINMUX_DATA(TS_SDAT_MARK, PORT134_FN1),
1025 PINMUX_DATA(MSIOF7_TXD_MARK, PORT134_FN2),
1026 PINMUX_DATA(STP_ISD_1_MARK, PORT134_FN3),
1027
1028 /* Port160 - Port178 */
1029 PINMUX_DATA(IRQ20_MARK, PORT160_FN0),
1030 PINMUX_DATA(IRQ21_MARK, PORT161_FN0),
1031 PINMUX_DATA(IRQ22_MARK, PORT162_FN0),
1032 PINMUX_DATA(IRQ23_MARK, PORT163_FN0),
1033 PINMUX_DATA(MMCD0_0_MARK, PORT164_FN1),
1034 PINMUX_DATA(MMCD0_1_MARK, PORT165_FN1),
1035 PINMUX_DATA(MMCD0_2_MARK, PORT166_FN1),
1036 PINMUX_DATA(MMCD0_3_MARK, PORT167_FN1),
1037 PINMUX_DATA(MMCD0_4_MARK, PORT168_FN1),
1038 PINMUX_DATA(MMCD0_5_MARK, PORT169_FN1),
1039 PINMUX_DATA(MMCD0_6_MARK, PORT170_FN1),
1040 PINMUX_DATA(MMCD0_7_MARK, PORT171_FN1),
1041 PINMUX_DATA(MMCCMD0_MARK, PORT172_FN1),
1042 PINMUX_DATA(MMCCLK0_MARK, PORT173_FN1),
1043 PINMUX_DATA(MMCRST_MARK, PORT174_FN1),
1044 PINMUX_DATA(IRQ24_MARK, PORT175_FN0),
1045 PINMUX_DATA(IRQ25_MARK, PORT176_FN0),
1046 PINMUX_DATA(IRQ26_MARK, PORT177_FN0),
1047 PINMUX_DATA(IRQ27_MARK, PORT178_FN0),
1048
1049 /* Port192 - Port200 FN1 */
1050 PINMUX_DATA(A10_MARK, PORT192_FN1),
1051 PINMUX_DATA(A9_MARK, PORT193_FN1),
1052 PINMUX_DATA(A8_MARK, PORT194_FN1),
1053 PINMUX_DATA(A7_MARK, PORT195_FN1),
1054 PINMUX_DATA(A6_MARK, PORT196_FN1),
1055 PINMUX_DATA(A5_MARK, PORT197_FN1),
1056 PINMUX_DATA(A4_MARK, PORT198_FN1),
1057 PINMUX_DATA(A3_MARK, PORT199_FN1),
1058 PINMUX_DATA(A2_MARK, PORT200_FN1),
1059
1060 /* Port192 - Port200 FN2 */
1061 PINMUX_DATA(MMCD1_7_MARK, PORT192_FN2),
1062 PINMUX_DATA(MMCD1_6_MARK, PORT193_FN2),
1063 PINMUX_DATA(MMCD1_5_MARK, PORT194_FN2),
1064 PINMUX_DATA(MMCD1_4_MARK, PORT195_FN2),
1065 PINMUX_DATA(MMCD1_3_MARK, PORT196_FN2),
1066 PINMUX_DATA(MMCD1_2_MARK, PORT197_FN2),
1067 PINMUX_DATA(MMCD1_1_MARK, PORT198_FN2),
1068 PINMUX_DATA(MMCD1_0_MARK, PORT199_FN2),
1069 PINMUX_DATA(MMCCMD1_MARK, PORT200_FN2),
1070
1071 /* Port192 - Port200 IRQ */
1072 PINMUX_DATA(IRQ31_MARK, PORT192_FN0),
1073 PINMUX_DATA(IRQ32_MARK, PORT193_FN0),
1074 PINMUX_DATA(IRQ33_MARK, PORT194_FN0),
1075 PINMUX_DATA(IRQ34_MARK, PORT195_FN0),
1076 PINMUX_DATA(IRQ35_MARK, PORT196_FN0),
1077 PINMUX_DATA(IRQ36_MARK, PORT197_FN0),
1078 PINMUX_DATA(IRQ37_MARK, PORT198_FN0),
1079 PINMUX_DATA(IRQ38_MARK, PORT199_FN0),
1080 PINMUX_DATA(IRQ39_MARK, PORT200_FN0),
1081
1082 /* Port201 */
1083 PINMUX_DATA(A1_MARK, PORT201_FN1),
1084
1085 /* Port202 */
1086 PINMUX_DATA(A0_MARK, PORT202_FN1),
1087 PINMUX_DATA(BS_MARK, PORT202_FN2),
1088
1089 /* Port203 */
1090 PINMUX_DATA(CKO_MARK, PORT203_FN1),
1091 PINMUX_DATA(MMCCLK1_MARK, PORT203_FN2),
1092
1093 /* Port204 */
1094 PINMUX_DATA(CS0_N_MARK, PORT204_FN1),
1095 PINMUX_DATA(SIM0_GPO1_MARK, PORT204_FN5),
1096
1097 /* Port205 */
1098 PINMUX_DATA(CS2_N_MARK, PORT205_FN1),
1099 PINMUX_DATA(SIM0_GPO2_MARK, PORT205_FN5),
1100
1101 /* Port206 */
1102 PINMUX_DATA(CS4_N_MARK, PORT206_FN1),
1103 PINMUX_DATA(VIO_VD_MARK, PORT206_FN2),
1104 PINMUX_DATA(SIM1_GPO0_MARK, PORT206_FN5),
1105
1106 /* Port207 - Port212 FN1 */
1107 PINMUX_DATA(D15_MARK, PORT207_FN1),
1108 PINMUX_DATA(D14_MARK, PORT208_FN1),
1109 PINMUX_DATA(D13_MARK, PORT209_FN1),
1110 PINMUX_DATA(D12_MARK, PORT210_FN1),
1111 PINMUX_DATA(D11_MARK, PORT211_FN1),
1112 PINMUX_DATA(D10_MARK, PORT212_FN1),
1113
1114 /* Port207 - Port212 FN5 */
1115 PINMUX_DATA(GIO_OUT15_MARK, PORT207_FN5),
1116 PINMUX_DATA(GIO_OUT14_MARK, PORT208_FN5),
1117 PINMUX_DATA(GIO_OUT13_MARK, PORT209_FN5),
1118 PINMUX_DATA(GIO_OUT12_MARK, PORT210_FN5),
1119 PINMUX_DATA(WGM_TXP2_MARK, PORT211_FN5),
1120 PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK, PORT212_FN5),
1121
1122 /* Port213 - Port222 FN1 */
1123 PINMUX_DATA(D9_MARK, PORT213_FN1),
1124 PINMUX_DATA(D8_MARK, PORT214_FN1),
1125 PINMUX_DATA(D7_MARK, PORT215_FN1),
1126 PINMUX_DATA(D6_MARK, PORT216_FN1),
1127 PINMUX_DATA(D5_MARK, PORT217_FN1),
1128 PINMUX_DATA(D4_MARK, PORT218_FN1),
1129 PINMUX_DATA(D3_MARK, PORT219_FN1),
1130 PINMUX_DATA(D2_MARK, PORT220_FN1),
1131 PINMUX_DATA(D1_MARK, PORT221_FN1),
1132 PINMUX_DATA(D0_MARK, PORT222_FN1),
1133
1134 /* Port213 - Port222 FN2 */
1135 PINMUX_DATA(VIO_D9_MARK, PORT213_FN2),
1136 PINMUX_DATA(VIO_D8_MARK, PORT214_FN2),
1137 PINMUX_DATA(VIO_D7_MARK, PORT215_FN2),
1138 PINMUX_DATA(VIO_D6_MARK, PORT216_FN2),
1139 PINMUX_DATA(VIO_D5_MARK, PORT217_FN2),
1140 PINMUX_DATA(VIO_D4_MARK, PORT218_FN2),
1141 PINMUX_DATA(VIO_D3_MARK, PORT219_FN2),
1142 PINMUX_DATA(VIO_D2_MARK, PORT220_FN2),
1143 PINMUX_DATA(VIO_D1_MARK, PORT221_FN2),
1144 PINMUX_DATA(VIO_D0_MARK, PORT222_FN2),
1145
1146 /* Port213 - Port222 FN5 */
1147 PINMUX_DATA(GIO_OUT9_MARK, PORT213_FN5),
1148 PINMUX_DATA(GIO_OUT8_MARK, PORT214_FN5),
1149 PINMUX_DATA(GIO_OUT7_MARK, PORT215_FN5),
1150 PINMUX_DATA(GIO_OUT6_MARK, PORT216_FN5),
1151 PINMUX_DATA(GIO_OUT5_217_MARK, PORT217_FN5),
1152 PINMUX_DATA(GIO_OUT4_218_MARK, PORT218_FN5),
1153 PINMUX_DATA(GIO_OUT3_219_MARK, PORT219_FN5),
1154 PINMUX_DATA(GIO_OUT2_220_MARK, PORT220_FN5),
1155 PINMUX_DATA(GIO_OUT1_221_MARK, PORT221_FN5),
1156 PINMUX_DATA(GIO_OUT0_222_MARK, PORT222_FN5),
1157
1158 /* Port224 */
1159 PINMUX_DATA(RDWR_224_MARK, PORT224_FN1),
1160 PINMUX_DATA(VIO_HD_MARK, PORT224_FN2),
1161 PINMUX_DATA(SIM1_GPO2_MARK, PORT224_FN5),
1162
1163 /* Port225 */
1164 PINMUX_DATA(RD_N_MARK, PORT225_FN1),
1165
1166 /* Port226 */
1167 PINMUX_DATA(WAIT_N_MARK, PORT226_FN1),
1168 PINMUX_DATA(VIO_CLK_MARK, PORT226_FN2),
1169 PINMUX_DATA(SIM1_GPO1_MARK, PORT226_FN5),
1170
1171 /* Port227 */
1172 PINMUX_DATA(WE0_N_MARK, PORT227_FN1),
1173 PINMUX_DATA(RDWR_227_MARK, PORT227_FN2),
1174
1175 /* Port228 */
1176 PINMUX_DATA(WE1_N_MARK, PORT228_FN1),
1177 PINMUX_DATA(SIM0_GPO0_MARK, PORT228_FN5),
1178
1179 /* Port229 */
1180 PINMUX_DATA(PWMO_MARK, PORT229_FN1),
1181 PINMUX_DATA(VIO_CKO1_229_MARK, PORT229_FN2),
1182
1183 /* Port230 */
1184 PINMUX_DATA(SLIM_CLK_MARK, PORT230_FN1),
1185 PINMUX_DATA(VIO_CKO4_230_MARK, PORT230_FN2),
1186
1187 /* Port231 */
1188 PINMUX_DATA(SLIM_DATA_MARK, PORT231_FN1),
1189 PINMUX_DATA(VIO_CKO5_231_MARK, PORT231_FN2),
1190
1191 /* Port232 */
1192 PINMUX_DATA(VIO_CKO2_232_MARK, PORT232_FN2),
1193 PINMUX_DATA(SF_PORT_0_232_MARK, PORT232_FN4),
1194
1195 /* Port233 */
1196 PINMUX_DATA(VIO_CKO3_233_MARK, PORT233_FN2),
1197 PINMUX_DATA(SF_PORT_1_233_MARK, PORT233_FN4),
1198
1199 /* Port234 */
1200 PINMUX_DATA(FSIACK_MARK, PORT234_FN1),
1201 PINMUX_DATA(PDM3_CLK_234_MARK, PORT234_FN2),
1202 PINMUX_DATA(ISP_IRIS1_234_MARK, PORT234_FN3),
1203
1204 /* Port235 */
1205 PINMUX_DATA(FSIAISLD_MARK, PORT235_FN1),
1206 PINMUX_DATA(PDM3_DATA_235_MARK, PORT235_FN2, MSEL3CR_12_1),
1207
1208 /* Port236 */
1209 PINMUX_DATA(FSIAOMC_MARK, PORT236_FN1),
1210 PINMUX_DATA(PDM0_OUTCLK_236_MARK, PORT236_FN2),
1211 PINMUX_DATA(ISP_IRIS0_236_MARK, PORT236_FN3),
1212
1213 /* Port237 */
1214 PINMUX_DATA(FSIAOLR_MARK, PORT237_FN1),
1215 PINMUX_DATA(FSIAILR_MARK, PORT237_FN2),
1216
1217 /* Port238 */
1218 PINMUX_DATA(FSIAOBT_MARK, PORT238_FN1),
1219 PINMUX_DATA(FSIAIBT_MARK, PORT238_FN2),
1220
1221 /* Port239 */
1222 PINMUX_DATA(FSIAOSLD_MARK, PORT239_FN1),
1223 PINMUX_DATA(PDM0_OUTDATA_239_MARK, PORT239_FN2),
1224
1225 /* Port240 */
1226 PINMUX_DATA(FSIBISLD_MARK, PORT240_FN1),
1227
1228 /* Port241 */
1229 PINMUX_DATA(FSIBOLR_MARK, PORT241_FN1),
1230 PINMUX_DATA(FSIBILR_MARK, PORT241_FN2),
1231
1232 /* Port242 */
1233 PINMUX_DATA(FSIBOMC_MARK, PORT242_FN1),
1234 PINMUX_DATA(ISP_SHUTTER1_242_MARK, PORT242_FN3),
1235
1236 /* Port243 */
1237 PINMUX_DATA(FSIBOBT_MARK, PORT243_FN1),
1238 PINMUX_DATA(FSIBIBT_MARK, PORT243_FN2),
1239
1240 /* Port244 */
1241 PINMUX_DATA(FSIBOSLD_MARK, PORT244_FN1),
1242 PINMUX_DATA(FSIASPDIF_MARK, PORT244_FN2),
1243
1244 /* Port245 */
1245 PINMUX_DATA(FSIBCK_MARK, PORT245_FN1),
1246 PINMUX_DATA(ISP_SHUTTER0_245_MARK, PORT245_FN3),
1247
1248 /* Port246 - Port250 FN1 */
1249 PINMUX_DATA(ISP_IRIS1_246_MARK, PORT246_FN1),
1250 PINMUX_DATA(ISP_IRIS0_247_MARK, PORT247_FN1),
1251 PINMUX_DATA(ISP_SHUTTER1_248_MARK, PORT248_FN1),
1252 PINMUX_DATA(ISP_SHUTTER0_249_MARK, PORT249_FN1),
1253 PINMUX_DATA(ISP_STROBE_250_MARK, PORT250_FN1),
1254
1255 /* Port256 - Port258 */
1256 PINMUX_DATA(MSIOF0_SYNC_MARK, PORT256_FN1),
1257 PINMUX_DATA(MSIOF0_RXD_MARK, PORT257_FN1),
1258 PINMUX_DATA(MSIOF0_SCK_MARK, PORT258_FN1),
1259
1260 /* Port259 */
1261 PINMUX_DATA(MSIOF0_SS2_MARK, PORT259_FN1),
1262 PINMUX_DATA(VIO_CKO3_259_MARK, PORT259_FN3),
1263
1264 /* Port260 */
1265 PINMUX_DATA(MSIOF0_TXD_MARK, PORT260_FN1),
1266
1267 /* Port261 */
1268 PINMUX_DATA(SCIFB1_SCK_261_MARK, PORT261_FN2),
1269 PINMUX_DATA(CHSCIF1_HSCK_MARK, PORT261_FN7),
1270
1271 /* Port262 */
1272 PINMUX_DATA(SCIFB2_SCK_262_MARK, PORT262_FN2),
1273
1274 /* Port263 - Port266 FN1 */
1275 PINMUX_DATA(MSIOF1_SS2_MARK, PORT263_FN1),
1276 PINMUX_DATA(MSIOF1_TXD_MARK, PORT264_FN1),
1277 PINMUX_DATA(MSIOF1_RXD_MARK, PORT265_FN1),
1278 PINMUX_DATA(MSIOF1_SS1_MARK, PORT266_FN1),
1279
1280 /* Port263 - Port266 FN4 */
1281 PINMUX_DATA(MSIOF5_SS2_MARK, PORT263_FN4),
1282 PINMUX_DATA(MSIOF5_TXD_MARK, PORT264_FN4),
1283 PINMUX_DATA(MSIOF5_RXD_MARK, PORT265_FN4),
1284 PINMUX_DATA(MSIOF5_SS1_MARK, PORT266_FN4),
1285
1286 /* Port267 */
1287 PINMUX_DATA(MSIOF0_SS1_MARK, PORT267_FN1),
1288
1289 /* Port268 */
1290 PINMUX_DATA(MSIOF1_SCK_MARK, PORT268_FN1),
1291 PINMUX_DATA(MSIOF5_SCK_MARK, PORT268_FN4),
1292
1293 /* Port269 */
1294 PINMUX_DATA(MSIOF1_SYNC_MARK, PORT269_FN1),
1295 PINMUX_DATA(MSIOF5_SYNC_MARK, PORT269_FN4),
1296
1297 /* Port270 - Port273 FN1 */
1298 PINMUX_DATA(MSIOF2_SS1_MARK, PORT270_FN1),
1299 PINMUX_DATA(MSIOF2_SS2_MARK, PORT271_FN1),
1300 PINMUX_DATA(MSIOF3_SS2_MARK, PORT272_FN1),
1301 PINMUX_DATA(MSIOF3_SS1_MARK, PORT273_FN1),
1302
1303 /* Port270 - Port273 FN3 */
1304 PINMUX_DATA(VIO_CKO5_270_MARK, PORT270_FN3),
1305 PINMUX_DATA(VIO_CKO2_271_MARK, PORT271_FN3),
1306 PINMUX_DATA(VIO_CKO1_272_MARK, PORT272_FN3),
1307 PINMUX_DATA(VIO_CKO4_273_MARK, PORT273_FN3),
1308
1309 /* Port274 */
1310 PINMUX_DATA(MSIOF4_SS2_MARK, PORT274_FN1),
1311 PINMUX_DATA(TPU1TO0_MARK, PORT274_FN4),
1312
1313 /* Port275 - Port280 */
1314 PINMUX_DATA(IC_DP_MARK, PORT275_FN1),
1315 PINMUX_DATA(SIM0_RST_MARK, PORT276_FN1),
1316 PINMUX_DATA(IC_DM_MARK, PORT277_FN1),
1317 PINMUX_DATA(SIM0_BSICOMP_MARK, PORT278_FN1),
1318 PINMUX_DATA(SIM0_CLK_MARK, PORT279_FN1),
1319 PINMUX_DATA(SIM0_IO_MARK, PORT280_FN1),
1320
1321 /* Port281 */
1322 PINMUX_DATA(SIM1_IO_MARK, PORT281_FN1),
1323 PINMUX_DATA(PDM2_DATA_281_MARK, PORT281_FN2, MSEL3CR_12_1),
1324
1325 /* Port282 */
1326 PINMUX_DATA(SIM1_CLK_MARK, PORT282_FN1),
1327 PINMUX_DATA(PDM2_CLK_282_MARK, PORT282_FN2),
1328
1329 /* Port283 */
1330 PINMUX_DATA(SIM1_RST_MARK, PORT283_FN1),
1331
1332 /* Port289 */
1333 PINMUX_DATA(SDHID1_0_MARK, PORT289_FN1),
1334 PINMUX_DATA(STMDATA0_2_MARK, PORT289_FN3),
1335
1336 /* Port290 */
1337 PINMUX_DATA(SDHID1_1_MARK, PORT290_FN1),
1338 PINMUX_DATA(STMDATA1_2_MARK, PORT290_FN3),
1339 PINMUX_DATA(IRQ51_MARK, PORT290_FN0),
1340
1341 /* Port291 - Port294 FN1 */
1342 PINMUX_DATA(SDHID1_2_MARK, PORT291_FN1),
1343 PINMUX_DATA(SDHID1_3_MARK, PORT292_FN1),
1344 PINMUX_DATA(SDHICLK1_MARK, PORT293_FN1),
1345 PINMUX_DATA(SDHICMD1_MARK, PORT294_FN1),
1346
1347 /* Port291 - Port294 FN3 */
1348 PINMUX_DATA(STMDATA2_2_MARK, PORT291_FN3),
1349 PINMUX_DATA(STMDATA3_2_MARK, PORT292_FN3),
1350 PINMUX_DATA(STMCLK_2_MARK, PORT293_FN3),
1351 PINMUX_DATA(STMSIDI_2_MARK, PORT294_FN3),
1352
1353 /* Port295 */
1354 PINMUX_DATA(SDHID2_0_MARK, PORT295_FN1),
1355 PINMUX_DATA(MSIOF4_TXD_MARK, PORT295_FN2),
1356 PINMUX_DATA(SCIFB2_TXD_295_MARK, PORT295_FN3, MSEL3CR_10_1),
1357 PINMUX_DATA(MSIOF6_TXD_MARK, PORT295_FN4),
1358
1359 /* Port296 */
1360 PINMUX_DATA(SDHID2_1_MARK, PORT296_FN1),
1361 PINMUX_DATA(MSIOF6_SS2_MARK, PORT296_FN4),
1362 PINMUX_DATA(IRQ52_MARK, PORT296_FN0),
1363
1364 /* Port297 - Port300 FN1 */
1365 PINMUX_DATA(SDHID2_2_MARK, PORT297_FN1),
1366 PINMUX_DATA(SDHID2_3_MARK, PORT298_FN1),
1367 PINMUX_DATA(SDHICLK2_MARK, PORT299_FN1),
1368 PINMUX_DATA(SDHICMD2_MARK, PORT300_FN1),
1369
1370 /* Port297 - Port300 FN2 */
1371 PINMUX_DATA(MSIOF4_RXD_MARK, PORT297_FN2),
1372 PINMUX_DATA(MSIOF4_SYNC_MARK, PORT298_FN2),
1373 PINMUX_DATA(MSIOF4_SCK_MARK, PORT299_FN2),
1374 PINMUX_DATA(MSIOF4_SS1_MARK, PORT300_FN2),
1375
1376 /* Port297 - Port300 FN3 */
1377 PINMUX_DATA(SCIFB2_RXD_297_MARK, PORT297_FN3, MSEL3CR_10_1),
1378 PINMUX_DATA(SCIFB2_CTS_298_MARK, PORT298_FN3, MSEL3CR_10_1),
1379 PINMUX_DATA(SCIFB2_SCK_299_MARK, PORT299_FN3),
1380 PINMUX_DATA(SCIFB2_RTS_300_MARK, PORT300_FN3),
1381
1382 /* Port297 - Port300 FN4 */
1383 PINMUX_DATA(MSIOF6_RXD_MARK, PORT297_FN4),
1384 PINMUX_DATA(MSIOF6_SYNC_MARK, PORT298_FN4),
1385 PINMUX_DATA(MSIOF6_SCK_MARK, PORT299_FN4),
1386 PINMUX_DATA(MSIOF6_SS1_MARK, PORT300_FN4),
1387
1388 /* Port301 */
1389 PINMUX_DATA(SDHICD0_MARK, PORT301_FN1),
1390 PINMUX_DATA(IRQ50_MARK, PORT301_FN0),
1391
1392 /* Port302 - Port306 FN1 */
1393 PINMUX_DATA(SDHID0_0_MARK, PORT302_FN1),
1394 PINMUX_DATA(SDHID0_1_MARK, PORT303_FN1),
1395 PINMUX_DATA(SDHID0_2_MARK, PORT304_FN1),
1396 PINMUX_DATA(SDHID0_3_MARK, PORT305_FN1),
1397 PINMUX_DATA(SDHICMD0_MARK, PORT306_FN1),
1398
1399 /* Port302 - Port306 FN3 */
1400 PINMUX_DATA(STMDATA0_1_MARK, PORT302_FN3),
1401 PINMUX_DATA(STMDATA1_1_MARK, PORT303_FN3),
1402 PINMUX_DATA(STMDATA2_1_MARK, PORT304_FN3),
1403 PINMUX_DATA(STMDATA3_1_MARK, PORT305_FN3),
1404 PINMUX_DATA(STMSIDI_1_MARK, PORT306_FN3),
1405
1406 /* Port307 */
1407 PINMUX_DATA(SDHIWP0_MARK, PORT307_FN1),
1408
1409 /* Port308 */
1410 PINMUX_DATA(SDHICLK0_MARK, PORT308_FN1),
1411 PINMUX_DATA(STMCLK_1_MARK, PORT308_FN3),
1412
1413 /* Port320 - Port329 */
1414 PINMUX_DATA(IRQ16_MARK, PORT320_FN0),
1415 PINMUX_DATA(IRQ17_MARK, PORT321_FN0),
1416 PINMUX_DATA(IRQ28_MARK, PORT322_FN0),
1417 PINMUX_DATA(IRQ29_MARK, PORT323_FN0),
1418 PINMUX_DATA(IRQ30_MARK, PORT324_FN0),
1419 PINMUX_DATA(IRQ53_MARK, PORT325_FN0),
1420 PINMUX_DATA(IRQ54_MARK, PORT326_FN0),
1421 PINMUX_DATA(IRQ55_MARK, PORT327_FN0),
1422 PINMUX_DATA(IRQ56_MARK, PORT328_FN0),
1423 PINMUX_DATA(IRQ57_MARK, PORT329_FN0),
1424};
1425
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]1426#define R8A73A4_PIN(pin, cfgs) \
1427 { \
1428 .name = __stringify(PORT##pin), \
1429 .enum_id = PORT##pin##_DATA, \
1430 .configs = cfgs, \
1431 }
1432
1433#define __O (SH_PFC_PIN_CFG_OUTPUT)
1434#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1435#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1436
1437#define R8A73A4_PIN_IO_PU_PD(pin) R8A73A4_PIN(pin, __IO | __PUD)
1438#define R8A73A4_PIN_O(pin) R8A73A4_PIN(pin, __O)
1439
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]1440static struct sh_pfc_pin pinmux_pins[] = {
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]1441 R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
1442 R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
1443 R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
1444 R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
1445 R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
1446 R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
1447 R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
1448 R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
1449 R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
1450 R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
1451 R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
1452 R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
1453 R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
1454 R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
1455 R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
1456 R8A73A4_PIN_IO_PU_PD(30),
1457 R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
1458 R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
1459 R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
1460 R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
1461 R8A73A4_PIN_IO_PU_PD(40),
1462 R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
1463 R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
1464 R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
1465 R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
1466 R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
1467 R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
1468 R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
1469 R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
1470 R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
1471 R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
1472 R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
1473 R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
1474 R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
1475 R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
1476 R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
1477 R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
1478 R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
1479 R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
1480 R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
1481 R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
1482 R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
1483 R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
1484 R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
1485 R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
1486 R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
1487 R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
1488 R8A73A4_PIN_IO_PU_PD(126),
1489 R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
1490 R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
1491 R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
1492 R8A73A4_PIN_IO_PU_PD(134),
1493 R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
1494 R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
1495 R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
1496 R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
1497 R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
1498 R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
1499 R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
1500 R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
1501 R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
1502 R8A73A4_PIN_IO_PU_PD(178),
1503 R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
1504 R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
1505 R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
1506 R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
1507 R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
1508 R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
1509 R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
1510 R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
1511 R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
1512 R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
1513 R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
1514 R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
1515 R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
1516 R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
1517 R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
1518 R8A73A4_PIN_IO_PU_PD(222),
1519 R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
1520 R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
1521 R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
1522 R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
1523 R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
1524 R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
1525 R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
1526 R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
1527 R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
1528 R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
1529 R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
1530 R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
1531 R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
1532 R8A73A4_PIN_IO_PU_PD(250),
1533 R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
1534 R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
1535 R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
1536 R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
1537 R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
1538 R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
1539 R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
1540 R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
1541 R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
1542 R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
1543 R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
1544 R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
1545 R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
1546 R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
1547 R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
1548 R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
1549 R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
1550 R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
1551 R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
1552 R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
1553 R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
1554 R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
1555 R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
1556 R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
1557 R8A73A4_PIN_IO_PU_PD(308),
1558 R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
1559 R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
1560 R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
1561 R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
1562 R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]1563};
1564
Magnus Dammf365bfc2013-03-26 22:49:59 +0900[diff] [blame]1565static const struct pinmux_range pinmux_ranges[] = {
1566 {.begin = 0, .end = 30,},
1567 {.begin = 32, .end = 40,},
1568 {.begin = 64, .end = 85,},
1569 {.begin = 96, .end = 126,},
1570 {.begin = 128, .end = 134,},
1571 {.begin = 160, .end = 178,},
1572 {.begin = 192, .end = 222,},
1573 {.begin = 224, .end = 250,},
1574 {.begin = 256, .end = 283,},
1575 {.begin = 288, .end = 308,},
1576 {.begin = 320, .end = 329,},
1577};
1578
Magnus Damm172fd612013-03-26 22:50:36 +0900[diff] [blame^]1579/* - SCIFA0 ----------------------------------------------------------------- */
1580static const unsigned int scifa0_data_pins[] = {
1581 /* SCIFA0_RXD, SCIFA0_TXD */
1582 117, 116,
1583};
1584static const unsigned int scifa0_data_mux[] = {
1585 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1586};
1587static const unsigned int scifa0_clk_pins[] = {
1588 /* SCIFA0_SCK */
1589 34,
1590};
1591static const unsigned int scifa0_clk_mux[] = {
1592 SCIFA0_SCK_MARK,
1593};
1594static const unsigned int scifa0_ctrl_pins[] = {
1595 /* SCIFA0_RTS, SCIFA0_CTS */
1596 32, 33,
1597};
1598static const unsigned int scifa0_ctrl_mux[] = {
1599 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1600};
1601/* - SCIFA1 ----------------------------------------------------------------- */
1602static const unsigned int scifa1_data_pins[] = {
1603 /* SCIFA1_RXD, SCIFA1_TXD */
1604 119, 118,
1605};
1606static const unsigned int scifa1_data_mux[] = {
1607 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1608};
1609static const unsigned int scifa1_clk_pins[] = {
1610 /* SCIFA1_SCK */
1611 37,
1612};
1613static const unsigned int scifa1_clk_mux[] = {
1614 SCIFA1_SCK_MARK,
1615};
1616static const unsigned int scifa1_ctrl_pins[] = {
1617 /* SCIFA1_RTS, SCIFA1_CTS */
1618 35, 36,
1619};
1620static const unsigned int scifa1_ctrl_mux[] = {
1621 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1622};
1623/* - SCIFB0 ----------------------------------------------------------------- */
1624static const unsigned int scifb0_data_pins[] = {
1625 /* SCIFB0_RXD, SCIFB0_TXD */
1626 123, 122,
1627};
1628static const unsigned int scifb0_data_mux[] = {
1629 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
1630};
1631static const unsigned int scifb0_clk_pins[] = {
1632 /* SCIFB0_SCK */
1633 40,
1634};
1635static const unsigned int scifb0_clk_mux[] = {
1636 SCIFB0_SCK_MARK,
1637};
1638static const unsigned int scifb0_ctrl_pins[] = {
1639 /* SCIFB0_RTS, SCIFB0_CTS */
1640 38, 39,
1641};
1642static const unsigned int scifb0_ctrl_mux[] = {
1643 SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
1644};
1645/* - SCIFB1 ----------------------------------------------------------------- */
1646static const unsigned int scifb1_data_pins[] = {
1647 /* SCIFB1_RXD, SCIFB1_TXD */
1648 27, 26,
1649};
1650static const unsigned int scifb1_data_mux[] = {
1651 SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
1652};
1653static const unsigned int scifb1_clk_pins[] = {
1654 /* SCIFB1_SCK */
1655 28,
1656};
1657static const unsigned int scifb1_clk_mux[] = {
1658 SCIFB1_SCK_28_MARK,
1659};
1660static const unsigned int scifb1_ctrl_pins[] = {
1661 /* SCIFB1_RTS, SCIFB1_CTS */
1662 24, 25,
1663};
1664static const unsigned int scifb1_ctrl_mux[] = {
1665 SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
1666};
1667static const unsigned int scifb1_data_b_pins[] = {
1668 /* SCIFB1_RXD, SCIFB1_TXD */
1669 72, 67,
1670};
1671static const unsigned int scifb1_data_b_mux[] = {
1672 SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
1673};
1674static const unsigned int scifb1_clk_b_pins[] = {
1675 /* SCIFB1_SCK */
1676 261,
1677};
1678static const unsigned int scifb1_clk_b_mux[] = {
1679 SCIFB1_SCK_261_MARK,
1680};
1681static const unsigned int scifb1_ctrl_b_pins[] = {
1682 /* SCIFB1_RTS, SCIFB1_CTS */
1683 70, 71,
1684};
1685static const unsigned int scifb1_ctrl_b_mux[] = {
1686 SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
1687};
1688/* - SCIFB2 ----------------------------------------------------------------- */
1689static const unsigned int scifb2_data_pins[] = {
1690 /* SCIFB2_RXD, SCIFB2_TXD */
1691 69, 68,
1692};
1693static const unsigned int scifb2_data_mux[] = {
1694 SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
1695};
1696static const unsigned int scifb2_clk_pins[] = {
1697 /* SCIFB2_SCK */
1698 262,
1699};
1700static const unsigned int scifb2_clk_mux[] = {
1701 SCIFB2_SCK_262_MARK,
1702};
1703static const unsigned int scifb2_ctrl_pins[] = {
1704 /* SCIFB2_RTS, SCIFB2_CTS */
1705 73, 66,
1706};
1707static const unsigned int scifb2_ctrl_mux[] = {
1708 SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
1709};
1710static const unsigned int scifb2_data_b_pins[] = {
1711 /* SCIFB2_RXD, SCIFB2_TXD */
1712 297, 295,
1713};
1714static const unsigned int scifb2_data_b_mux[] = {
1715 SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
1716};
1717static const unsigned int scifb2_clk_b_pins[] = {
1718 /* SCIFB2_SCK */
1719 299,
1720};
1721static const unsigned int scifb2_clk_b_mux[] = {
1722 SCIFB2_SCK_299_MARK,
1723};
1724static const unsigned int scifb2_ctrl_b_pins[] = {
1725 /* SCIFB2_RTS, SCIFB2_CTS */
1726 300, 298,
1727};
1728static const unsigned int scifb2_ctrl_b_mux[] = {
1729 SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
1730};
1731/* - SCIFB3 ----------------------------------------------------------------- */
1732static const unsigned int scifb3_data_pins[] = {
1733 /* SCIFB3_RXD, SCIFB3_TXD */
1734 22, 21,
1735};
1736static const unsigned int scifb3_data_mux[] = {
1737 SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
1738};
1739static const unsigned int scifb3_clk_pins[] = {
1740 /* SCIFB3_SCK */
1741 23,
1742};
1743static const unsigned int scifb3_clk_mux[] = {
1744 SCIFB3_SCK_23_MARK,
1745};
1746static const unsigned int scifb3_ctrl_pins[] = {
1747 /* SCIFB3_RTS, SCIFB3_CTS */
1748 19, 20,
1749};
1750static const unsigned int scifb3_ctrl_mux[] = {
1751 SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
1752};
1753static const unsigned int scifb3_data_b_pins[] = {
1754 /* SCIFB3_RXD, SCIFB3_TXD */
1755 120, 121,
1756};
1757static const unsigned int scifb3_data_b_mux[] = {
1758 SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
1759};
1760static const unsigned int scifb3_clk_b_pins[] = {
1761 /* SCIFB3_SCK */
1762 40,
1763};
1764static const unsigned int scifb3_clk_b_mux[] = {
1765 SCIFB3_SCK_40_MARK,
1766};
1767static const unsigned int scifb3_ctrl_b_pins[] = {
1768 /* SCIFB3_RTS, SCIFB3_CTS */
1769 38, 39,
1770};
1771static const unsigned int scifb3_ctrl_b_mux[] = {
1772 SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
1773};
1774
1775static const struct sh_pfc_pin_group pinmux_groups[] = {
1776 SH_PFC_PIN_GROUP(scifa0_data),
1777 SH_PFC_PIN_GROUP(scifa0_clk),
1778 SH_PFC_PIN_GROUP(scifa0_ctrl),
1779 SH_PFC_PIN_GROUP(scifa1_data),
1780 SH_PFC_PIN_GROUP(scifa1_clk),
1781 SH_PFC_PIN_GROUP(scifa1_ctrl),
1782 SH_PFC_PIN_GROUP(scifb0_data),
1783 SH_PFC_PIN_GROUP(scifb0_clk),
1784 SH_PFC_PIN_GROUP(scifb0_ctrl),
1785 SH_PFC_PIN_GROUP(scifb1_data),
1786 SH_PFC_PIN_GROUP(scifb1_clk),
1787 SH_PFC_PIN_GROUP(scifb1_ctrl),
1788 SH_PFC_PIN_GROUP(scifb1_data_b),
1789 SH_PFC_PIN_GROUP(scifb1_clk_b),
1790 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
1791 SH_PFC_PIN_GROUP(scifb2_data),
1792 SH_PFC_PIN_GROUP(scifb2_clk),
1793 SH_PFC_PIN_GROUP(scifb2_ctrl),
1794 SH_PFC_PIN_GROUP(scifb2_data_b),
1795 SH_PFC_PIN_GROUP(scifb2_clk_b),
1796 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
1797 SH_PFC_PIN_GROUP(scifb3_data),
1798 SH_PFC_PIN_GROUP(scifb3_clk),
1799 SH_PFC_PIN_GROUP(scifb3_ctrl),
1800 SH_PFC_PIN_GROUP(scifb3_data_b),
1801 SH_PFC_PIN_GROUP(scifb3_clk_b),
1802 SH_PFC_PIN_GROUP(scifb3_ctrl_b),
1803};
1804
1805static const char * const scifa0_groups[] = {
1806 "scifa0_data",
1807 "scifa0_clk",
1808 "scifa0_ctrl",
1809};
1810
1811static const char * const scifa1_groups[] = {
1812 "scifa1_data",
1813 "scifa1_clk",
1814 "scifa1_ctrl",
1815};
1816
1817static const char * const scifb0_groups[] = {
1818 "scifb0_data",
1819 "scifb0_clk",
1820 "scifb0_ctrl",
1821};
1822
1823static const char * const scifb1_groups[] = {
1824 "scifb1_data",
1825 "scifb1_clk",
1826 "scifb1_ctrl",
1827 "scifb1_data_b",
1828 "scifb1_clk_b",
1829 "scifb1_ctrl_b",
1830};
1831
1832static const char * const scifb2_groups[] = {
1833 "scifb2_data",
1834 "scifb2_clk",
1835 "scifb2_ctrl",
1836 "scifb2_data_b",
1837 "scifb2_clk_b",
1838 "scifb2_ctrl_b",
1839};
1840
1841static const char * const scifb3_groups[] = {
1842 "scifb3_data",
1843 "scifb3_clk",
1844 "scifb3_ctrl",
1845 "scifb3_data_b",
1846 "scifb3_clk_b",
1847 "scifb3_ctrl_b",
1848};
1849
1850static const struct sh_pfc_function pinmux_functions[] = {
1851 SH_PFC_FUNCTION(scifa0),
1852 SH_PFC_FUNCTION(scifa1),
1853 SH_PFC_FUNCTION(scifb0),
1854 SH_PFC_FUNCTION(scifb1),
1855 SH_PFC_FUNCTION(scifb2),
1856 SH_PFC_FUNCTION(scifb3),
1857};
1858
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]1859#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
1860
1861static const struct pinmux_func pinmux_func_gpios[] = {
1862 /* Port0 */
1863 GPIO_FN(LCDD0),
1864 GPIO_FN(PDM2_CLK_0),
1865 GPIO_FN(DU0_DR0),
1866 GPIO_FN(IRQ0),
1867
1868 /* Port1 */
1869 GPIO_FN(LCDD1),
1870 GPIO_FN(PDM2_DATA_1),
1871 GPIO_FN(DU0_DR19),
1872 GPIO_FN(IRQ1),
1873
1874 /* Port2 */
1875 GPIO_FN(LCDD2),
1876 GPIO_FN(PDM3_CLK_2),
1877 GPIO_FN(DU0_DR2),
1878 GPIO_FN(IRQ2),
1879
1880 /* Port3 */
1881 GPIO_FN(LCDD3),
1882 GPIO_FN(PDM3_DATA_3),
1883 GPIO_FN(DU0_DR3),
1884 GPIO_FN(IRQ3),
1885
1886 /* Port4 */
1887 GPIO_FN(LCDD4),
1888 GPIO_FN(PDM4_CLK_4),
1889 GPIO_FN(DU0_DR4),
1890 GPIO_FN(IRQ4),
1891
1892 /* Port5 */
1893 GPIO_FN(LCDD5),
1894 GPIO_FN(PDM4_DATA_5),
1895 GPIO_FN(DU0_DR5),
1896 GPIO_FN(IRQ5),
1897
1898 /* Port6 */
1899 GPIO_FN(LCDD6),
1900 GPIO_FN(PDM0_OUTCLK_6),
1901 GPIO_FN(DU0_DR6),
1902 GPIO_FN(IRQ6),
1903
1904 /* Port7 */
1905 GPIO_FN(LCDD7),
1906 GPIO_FN(PDM0_OUTDATA_7),
1907 GPIO_FN(DU0_DR7),
1908 GPIO_FN(IRQ7),
1909
1910 /* Port8 */
1911 GPIO_FN(LCDD8),
1912 GPIO_FN(PDM1_OUTCLK_8),
1913 GPIO_FN(DU0_DG0),
1914 GPIO_FN(IRQ8),
1915
1916 /* Port9 */
1917 GPIO_FN(LCDD9),
1918 GPIO_FN(PDM1_OUTDATA_9),
1919 GPIO_FN(DU0_DG1),
1920 GPIO_FN(IRQ9),
1921
1922 /* Port10 */
1923 GPIO_FN(LCDD10),
1924 GPIO_FN(FSICCK),
1925 GPIO_FN(DU0_DG2),
1926 GPIO_FN(IRQ10),
1927
1928 /* Port11 */
1929 GPIO_FN(LCDD11),
1930 GPIO_FN(FSICISLD),
1931 GPIO_FN(DU0_DG3),
1932 GPIO_FN(IRQ11),
1933
1934 /* Port12 */
1935 GPIO_FN(LCDD12),
1936 GPIO_FN(FSICOMC),
1937 GPIO_FN(DU0_DG4),
1938 GPIO_FN(IRQ12),
1939
1940 /* Port13 */
1941 GPIO_FN(LCDD13),
1942 GPIO_FN(FSICOLR),
1943 GPIO_FN(FSICILR),
1944 GPIO_FN(DU0_DG5),
1945 GPIO_FN(IRQ13),
1946
1947 /* Port14 */
1948 GPIO_FN(LCDD14),
1949 GPIO_FN(FSICOBT),
1950 GPIO_FN(FSICIBT),
1951 GPIO_FN(DU0_DG6),
1952 GPIO_FN(IRQ14),
1953
1954 /* Port15 */
1955 GPIO_FN(LCDD15),
1956 GPIO_FN(FSICOSLD),
1957 GPIO_FN(DU0_DG7),
1958 GPIO_FN(IRQ15),
1959
1960 /* Port16 */
1961 GPIO_FN(LCDD16),
1962 GPIO_FN(TPU1TO1),
1963 GPIO_FN(DU0_DB0),
1964
1965 /* Port17 */
1966 GPIO_FN(LCDD17),
1967 GPIO_FN(SF_IRQ_00),
1968 GPIO_FN(DU0_DB1),
1969
1970 /* Port18 */
1971 GPIO_FN(LCDD18),
1972 GPIO_FN(SF_IRQ_01),
1973 GPIO_FN(DU0_DB2),
1974
1975 /* Port19 */
1976 GPIO_FN(LCDD19),
1977 GPIO_FN(SCIFB3_RTS_19),
1978 GPIO_FN(DU0_DB3),
1979
1980 /* Port20 */
1981 GPIO_FN(LCDD20),
1982 GPIO_FN(SCIFB3_CTS_20),
1983 GPIO_FN(DU0_DB4),
1984
1985 /* Port21 */
1986 GPIO_FN(LCDD21),
1987 GPIO_FN(SCIFB3_TXD_21),
1988 GPIO_FN(DU0_DB5),
1989
1990 /* Port22 */
1991 GPIO_FN(LCDD22),
1992 GPIO_FN(SCIFB3_RXD_22),
1993 GPIO_FN(DU0_DB6),
1994
1995 /* Port23 */
1996 GPIO_FN(LCDD23),
1997 GPIO_FN(SCIFB3_SCK_23),
1998 GPIO_FN(DU0_DB7),
1999
2000 /* Port24 */
2001 GPIO_FN(LCDHSYN),
2002 GPIO_FN(LCDCS),
2003 GPIO_FN(SCIFB1_RTS_24),
2004 GPIO_FN(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
2005
2006 /* Port25 */
2007 GPIO_FN(LCDVSYN),
2008 GPIO_FN(SCIFB1_CTS_25),
2009 GPIO_FN(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
2010
2011 /* Port26 */
2012 GPIO_FN(LCDDCK),
2013 GPIO_FN(LCDWR),
2014 GPIO_FN(SCIFB1_TXD_26),
2015 GPIO_FN(DU0_DOTCLKIN),
2016
2017 /* Port27 */
2018 GPIO_FN(LCDDISP),
2019 GPIO_FN(LCDRS),
2020 GPIO_FN(SCIFB1_RXD_27),
2021 GPIO_FN(DU0_DOTCLKOUT),
2022
2023 /* Port28 */
2024 GPIO_FN(LCDRD_N),
2025 GPIO_FN(SCIFB1_SCK_28),
2026 GPIO_FN(DU0_DOTCLKOUTB),
2027
2028 /* Port29 */
2029 GPIO_FN(LCDLCLK),
2030 GPIO_FN(SF_IRQ_02),
2031 GPIO_FN(DU0_DISP_CSYNC_N_DE),
2032
2033 /* Port30 */
2034 GPIO_FN(LCDDON),
2035 GPIO_FN(SF_IRQ_03),
2036 GPIO_FN(DU0_ODDF_N_CLAMP),
2037
2038 /* Port32 */
2039 GPIO_FN(SCIFA0_RTS),
2040 GPIO_FN(SIM0_DET),
2041 GPIO_FN(CSCIF0_RTS),
2042
2043 /* Port33 */
2044 GPIO_FN(SCIFA0_CTS),
2045 GPIO_FN(SIM1_DET),
2046 GPIO_FN(CSCIF0_CTS),
2047
2048 /* Port34 */
2049 GPIO_FN(SCIFA0_SCK),
2050 GPIO_FN(SIM0_PWRON),
2051 GPIO_FN(CSCIF0_SCK),
2052
2053 /* Port35 */
2054 GPIO_FN(SCIFA1_RTS),
2055 GPIO_FN(CSCIF1_RTS),
2056
2057 /* Port36 */
2058 GPIO_FN(SCIFA1_CTS),
2059 GPIO_FN(CSCIF1_CTS),
2060
2061 /* Port37 */
2062 GPIO_FN(SCIFA1_SCK),
2063 GPIO_FN(CSCIF1_SCK),
2064
2065 /* Port38 */
2066 GPIO_FN(SCIFB0_RTS),
2067 GPIO_FN(TPU0TO1),
2068 GPIO_FN(SCIFB3_RTS_38),
2069 GPIO_FN(CHSCIF0_HRTS),
2070
2071 /* Port39 */
2072 GPIO_FN(SCIFB0_CTS),
2073 GPIO_FN(TPU0TO2),
2074 GPIO_FN(SCIFB3_CTS_39),
2075 GPIO_FN(CHSCIF0_HCTS),
2076
2077 /* Port40 */
2078 GPIO_FN(SCIFB0_SCK),
2079 GPIO_FN(TPU0TO3),
2080 GPIO_FN(SCIFB3_SCK_40),
2081 GPIO_FN(CHSCIF0_HSCK),
2082
2083 /* Port64 */
2084 GPIO_FN(PDM0_DATA),
2085
2086 /* Port65 */
2087 GPIO_FN(PDM1_DATA),
2088
2089 /* Port66 */
2090 GPIO_FN(HSI_RX_WAKE),
2091 GPIO_FN(SCIFB2_CTS_66),
2092 GPIO_FN(MSIOF3_SYNC),
2093 GPIO_FN(GenIO4),
2094 GPIO_FN(IRQ40),
2095
2096 /* Port67 */
2097 GPIO_FN(HSI_RX_READY),
2098 GPIO_FN(SCIFB1_TXD_67),
2099 GPIO_FN(GIO_OUT3_67),
2100 GPIO_FN(CHSCIF1_HTX),
2101
2102 /* Port68 */
2103 GPIO_FN(HSI_RX_FLAG),
2104 GPIO_FN(SCIFB2_TXD_68),
2105 GPIO_FN(MSIOF3_TXD),
2106 GPIO_FN(GIO_OUT4_68),
2107
2108 /* Port69 */
2109 GPIO_FN(HSI_RX_DATA),
2110 GPIO_FN(SCIFB2_RXD_69),
2111 GPIO_FN(MSIOF3_RXD),
2112 GPIO_FN(GIO_OUT5_69),
2113
2114 /* Port70 */
2115 GPIO_FN(HSI_TX_FLAG),
2116 GPIO_FN(SCIFB1_RTS_70),
2117 GPIO_FN(GIO_OUT1_70),
2118 GPIO_FN(HSIC_TSTCLK0),
2119 GPIO_FN(CHSCIF1_HRTS),
2120
2121 /* Port71 */
2122 GPIO_FN(HSI_TX_DATA),
2123 GPIO_FN(SCIFB1_CTS_71),
2124 GPIO_FN(GIO_OUT2_71),
2125 GPIO_FN(HSIC_TSTCLK1),
2126 GPIO_FN(CHSCIF1_HCTS),
2127
2128 /* Port72 */
2129 GPIO_FN(HSI_TX_WAKE),
2130 GPIO_FN(SCIFB1_RXD_72),
2131 GPIO_FN(GenIO8),
2132 GPIO_FN(CHSCIF1_HRX),
2133
2134 /* Port73 */
2135 GPIO_FN(HSI_TX_READY),
2136 GPIO_FN(SCIFB2_RTS_73),
2137 GPIO_FN(MSIOF3_SCK),
2138 GPIO_FN(GIO_OUT0_73),
2139
2140 /* Port74 - Port85 */
2141 GPIO_FN(IRDA_OUT),
2142 GPIO_FN(IRDA_IN),
2143 GPIO_FN(IRDA_FIRSEL),
2144 GPIO_FN(TPU0TO0),
2145 GPIO_FN(DIGRFEN),
2146 GPIO_FN(GPS_TIMESTAMP),
2147 GPIO_FN(TXP),
2148 GPIO_FN(TXP2),
2149 GPIO_FN(COEX_0),
2150 GPIO_FN(COEX_1),
2151 GPIO_FN(IRQ19),
2152 GPIO_FN(IRQ18),
2153
2154 /* Port96 - Port101 */
2155 GPIO_FN(KEYIN0),
2156 GPIO_FN(KEYIN1),
2157 GPIO_FN(KEYIN2),
2158 GPIO_FN(KEYIN3),
2159 GPIO_FN(KEYIN4),
2160 GPIO_FN(KEYIN5),
2161
2162 /* Port102 */
2163 GPIO_FN(KEYIN6),
2164 GPIO_FN(IRQ41),
2165
2166 /* Port103 */
2167 GPIO_FN(KEYIN7),
2168 GPIO_FN(IRQ42),
2169
2170 /* Port104 - Port108 */
2171 GPIO_FN(KEYOUT0),
2172 GPIO_FN(KEYOUT1),
2173 GPIO_FN(KEYOUT2),
2174 GPIO_FN(KEYOUT3),
2175 GPIO_FN(KEYOUT4),
2176
2177 /* Port109 */
2178 GPIO_FN(KEYOUT5),
2179 GPIO_FN(IRQ43),
2180
2181 /* Port110 */
2182 GPIO_FN(KEYOUT6),
2183 GPIO_FN(IRQ44),
2184
2185 /* Port111 */
2186 GPIO_FN(KEYOUT7),
2187 GPIO_FN(RFANAEN),
2188 GPIO_FN(IRQ45),
2189
2190 /* Port112 */
2191 GPIO_FN(KEYIN8),
2192 GPIO_FN(KEYOUT8),
2193 GPIO_FN(SF_IRQ_04),
2194 GPIO_FN(IRQ46),
2195
2196 /* Port113 */
2197 GPIO_FN(KEYIN9),
2198 GPIO_FN(KEYOUT9),
2199 GPIO_FN(SF_IRQ_05),
2200 GPIO_FN(IRQ47),
2201
2202 /* Port114 */
2203 GPIO_FN(KEYIN10),
2204 GPIO_FN(KEYOUT10),
2205 GPIO_FN(SF_IRQ_06),
2206 GPIO_FN(IRQ48),
2207
2208 /* Port115 */
2209 GPIO_FN(KEYIN11),
2210 GPIO_FN(KEYOUT11),
2211 GPIO_FN(SF_IRQ_07),
2212 GPIO_FN(IRQ49),
2213
2214 /* Port116 */
2215 GPIO_FN(SCIFA0_TXD),
2216 GPIO_FN(CSCIF0_TX),
2217
2218 /* Port117 */
2219 GPIO_FN(SCIFA0_RXD),
2220 GPIO_FN(CSCIF0_RX),
2221
2222 /* Port118 */
2223 GPIO_FN(SCIFA1_TXD),
2224 GPIO_FN(CSCIF1_TX),
2225
2226 /* Port119 */
2227 GPIO_FN(SCIFA1_RXD),
2228 GPIO_FN(CSCIF1_RX),
2229
2230 /* Port120 */
2231 GPIO_FN(SF_PORT_1_120),
2232 GPIO_FN(SCIFB3_RXD_120),
2233 GPIO_FN(DU0_CDE),
2234
2235 /* Port121 */
2236 GPIO_FN(SF_PORT_0_121),
2237 GPIO_FN(SCIFB3_TXD_121),
2238
2239 /* Port122 */
2240 GPIO_FN(SCIFB0_TXD),
2241 GPIO_FN(CHSCIF0_HTX),
2242
2243 /* Port123 */
2244 GPIO_FN(SCIFB0_RXD),
2245 GPIO_FN(CHSCIF0_HRX),
2246
2247 /* Port124 */
2248 GPIO_FN(ISP_STROBE_124),
2249
2250 /* Port125 */
2251 GPIO_FN(STP_ISD_0),
2252 GPIO_FN(PDM4_CLK_125),
2253 GPIO_FN(MSIOF2_TXD),
2254 GPIO_FN(SIM0_VOLTSEL0),
2255
2256 /* Port126 */
2257 GPIO_FN(TS_SDEN),
2258 GPIO_FN(MSIOF7_SYNC),
2259 GPIO_FN(STP_ISEN_1),
2260
2261 /* Port128 */
2262 GPIO_FN(STP_ISEN_0),
2263 GPIO_FN(PDM1_OUTDATA_128),
2264 GPIO_FN(MSIOF2_SYNC),
2265 GPIO_FN(SIM1_VOLTSEL1),
2266
2267 /* Port129 */
2268 GPIO_FN(TS_SPSYNC),
2269 GPIO_FN(MSIOF7_RXD),
2270 GPIO_FN(STP_ISSYNC_1),
2271
2272 /* Port130 */
2273 GPIO_FN(STP_ISSYNC_0),
2274 GPIO_FN(PDM4_DATA_130),
2275 GPIO_FN(MSIOF2_RXD),
2276 GPIO_FN(SIM0_VOLTSEL1),
2277
2278 /* Port131 */
2279 GPIO_FN(STP_OPWM_0),
2280 GPIO_FN(SIM1_PWRON),
2281
2282 /* Port132 */
2283 GPIO_FN(TS_SCK),
2284 GPIO_FN(MSIOF7_SCK),
2285 GPIO_FN(STP_ISCLK_1),
2286
2287 /* Port133 */
2288 GPIO_FN(STP_ISCLK_0),
2289 GPIO_FN(PDM1_OUTCLK_133),
2290 GPIO_FN(MSIOF2_SCK),
2291 GPIO_FN(SIM1_VOLTSEL0),
2292
2293 /* Port134 */
2294 GPIO_FN(TS_SDAT),
2295 GPIO_FN(MSIOF7_TXD),
2296 GPIO_FN(STP_ISD_1),
2297
2298 /* Port160 - Port178 */
2299 GPIO_FN(IRQ20),
2300 GPIO_FN(IRQ21),
2301 GPIO_FN(IRQ22),
2302 GPIO_FN(IRQ23),
2303 GPIO_FN(MMCD0_0),
2304 GPIO_FN(MMCD0_1),
2305 GPIO_FN(MMCD0_2),
2306 GPIO_FN(MMCD0_3),
2307 GPIO_FN(MMCD0_4),
2308 GPIO_FN(MMCD0_5),
2309 GPIO_FN(MMCD0_6),
2310 GPIO_FN(MMCD0_7),
2311 GPIO_FN(MMCCMD0),
2312 GPIO_FN(MMCCLK0),
2313 GPIO_FN(MMCRST),
2314 GPIO_FN(IRQ24),
2315 GPIO_FN(IRQ25),
2316 GPIO_FN(IRQ26),
2317 GPIO_FN(IRQ27),
2318
2319 /* Port192 - Port200 FN1 */
2320 GPIO_FN(A10),
2321 GPIO_FN(A9),
2322 GPIO_FN(A8),
2323 GPIO_FN(A7),
2324 GPIO_FN(A6),
2325 GPIO_FN(A5),
2326 GPIO_FN(A4),
2327 GPIO_FN(A3),
2328 GPIO_FN(A2),
2329
2330 /* Port192 - Port200 FN2 */
2331 GPIO_FN(MMCD1_7),
2332 GPIO_FN(MMCD1_6),
2333 GPIO_FN(MMCD1_5),
2334 GPIO_FN(MMCD1_4),
2335 GPIO_FN(MMCD1_3),
2336 GPIO_FN(MMCD1_2),
2337 GPIO_FN(MMCD1_1),
2338 GPIO_FN(MMCD1_0),
2339 GPIO_FN(MMCCMD1),
2340
2341 /* Port192 - Port200 IRQ */
2342 GPIO_FN(IRQ31),
2343 GPIO_FN(IRQ32),
2344 GPIO_FN(IRQ33),
2345 GPIO_FN(IRQ34),
2346 GPIO_FN(IRQ35),
2347 GPIO_FN(IRQ36),
2348 GPIO_FN(IRQ37),
2349 GPIO_FN(IRQ38),
2350 GPIO_FN(IRQ39),
2351
2352 /* Port201 */
2353 GPIO_FN(A1),
2354
2355 /* Port202 */
2356 GPIO_FN(A0),
2357 GPIO_FN(BS),
2358
2359 /* Port203 */
2360 GPIO_FN(CKO),
2361 GPIO_FN(MMCCLK1),
2362
2363 /* Port204 */
2364 GPIO_FN(CS0_N),
2365 GPIO_FN(SIM0_GPO1),
2366
2367 /* Port205 */
2368 GPIO_FN(CS2_N),
2369 GPIO_FN(SIM0_GPO2),
2370
2371 /* Port206 */
2372 GPIO_FN(CS4_N),
2373 GPIO_FN(VIO_VD),
2374 GPIO_FN(SIM1_GPO0),
2375
2376 /* Port207 - Port212 FN1 */
2377 GPIO_FN(D15),
2378 GPIO_FN(D14),
2379 GPIO_FN(D13),
2380 GPIO_FN(D12),
2381 GPIO_FN(D11),
2382 GPIO_FN(D10),
2383
2384 /* Port207 - Port212 FN5 */
2385 GPIO_FN(GIO_OUT15),
2386 GPIO_FN(GIO_OUT14),
2387 GPIO_FN(GIO_OUT13),
2388 GPIO_FN(GIO_OUT12),
2389 GPIO_FN(WGM_TXP2),
2390 GPIO_FN(WGM_GPS_TIMEM_ASK_RFCLK),
2391
2392 /* Port213 - Port222 FN1 */
2393 GPIO_FN(D9),
2394 GPIO_FN(D8),
2395 GPIO_FN(D7),
2396 GPIO_FN(D6),
2397 GPIO_FN(D5),
2398 GPIO_FN(D4),
2399 GPIO_FN(D3),
2400 GPIO_FN(D2),
2401 GPIO_FN(D1),
2402 GPIO_FN(D0),
2403
2404 /* Port213 - Port222 FN2 */
2405 GPIO_FN(VIO_D9),
2406 GPIO_FN(VIO_D8),
2407 GPIO_FN(VIO_D7),
2408 GPIO_FN(VIO_D6),
2409 GPIO_FN(VIO_D5),
2410 GPIO_FN(VIO_D4),
2411 GPIO_FN(VIO_D3),
2412 GPIO_FN(VIO_D2),
2413 GPIO_FN(VIO_D1),
2414 GPIO_FN(VIO_D0),
2415
2416 /* Port213 - Port222 FN5 */
2417 GPIO_FN(GIO_OUT9),
2418 GPIO_FN(GIO_OUT8),
2419 GPIO_FN(GIO_OUT7),
2420 GPIO_FN(GIO_OUT6),
2421 GPIO_FN(GIO_OUT5_217),
2422 GPIO_FN(GIO_OUT4_218),
2423 GPIO_FN(GIO_OUT3_219),
2424 GPIO_FN(GIO_OUT2_220),
2425 GPIO_FN(GIO_OUT1_221),
2426 GPIO_FN(GIO_OUT0_222),
2427
2428 /* Port224 */
2429 GPIO_FN(RDWR_224),
2430 GPIO_FN(VIO_HD),
2431 GPIO_FN(SIM1_GPO2),
2432
2433 /* Port225 */
2434 GPIO_FN(RD_N),
2435
2436 /* Port226 */
2437 GPIO_FN(WAIT_N),
2438 GPIO_FN(VIO_CLK),
2439 GPIO_FN(SIM1_GPO1),
2440
2441 /* Port227 */
2442 GPIO_FN(WE0_N),
2443 GPIO_FN(RDWR_227),
2444
2445 /* Port228 */
2446 GPIO_FN(WE1_N),
2447 GPIO_FN(SIM0_GPO0),
2448
2449 /* Port229 */
2450 GPIO_FN(PWMO),
2451 GPIO_FN(VIO_CKO1_229),
2452
2453 /* Port230 */
2454 GPIO_FN(SLIM_CLK),
2455 GPIO_FN(VIO_CKO4_230),
2456
2457 /* Port231 */
2458 GPIO_FN(SLIM_DATA),
2459 GPIO_FN(VIO_CKO5_231),
2460
2461 /* Port232 */
2462 GPIO_FN(VIO_CKO2_232),
2463 GPIO_FN(SF_PORT_0_232),
2464
2465 /* Port233 */
2466 GPIO_FN(VIO_CKO3_233),
2467 GPIO_FN(SF_PORT_1_233),
2468
2469 /* Port234 */
2470 GPIO_FN(FSIACK),
2471 GPIO_FN(PDM3_CLK_234),
2472 GPIO_FN(ISP_IRIS1_234),
2473
2474 /* Port235 */
2475 GPIO_FN(FSIAISLD),
2476 GPIO_FN(PDM3_DATA_235),
2477
2478 /* Port236 */
2479 GPIO_FN(FSIAOMC),
2480 GPIO_FN(PDM0_OUTCLK_236),
2481 GPIO_FN(ISP_IRIS0_236),
2482
2483 /* Port237 */
2484 GPIO_FN(FSIAOLR),
2485 GPIO_FN(FSIAILR),
2486
2487 /* Port238 */
2488 GPIO_FN(FSIAOBT),
2489 GPIO_FN(FSIAIBT),
2490
2491 /* Port239 */
2492 GPIO_FN(FSIAOSLD),
2493 GPIO_FN(PDM0_OUTDATA_239),
2494
2495 /* Port240 */
2496 GPIO_FN(FSIBISLD),
2497
2498 /* Port241 */
2499 GPIO_FN(FSIBOLR),
2500 GPIO_FN(FSIBILR),
2501
2502 /* Port242 */
2503 GPIO_FN(FSIBOMC),
2504 GPIO_FN(ISP_SHUTTER1_242),
2505
2506 /* Port243 */
2507 GPIO_FN(FSIBOBT),
2508 GPIO_FN(FSIBIBT),
2509
2510 /* Port244 */
2511 GPIO_FN(FSIBOSLD),
2512 GPIO_FN(FSIASPDIF),
2513
2514 /* Port245 */
2515 GPIO_FN(FSIBCK),
2516 GPIO_FN(ISP_SHUTTER0_245),
2517
2518 /* Port246 - Port250 FN1 */
2519 GPIO_FN(ISP_IRIS1_246),
2520 GPIO_FN(ISP_IRIS0_247),
2521 GPIO_FN(ISP_SHUTTER1_248),
2522 GPIO_FN(ISP_SHUTTER0_249),
2523 GPIO_FN(ISP_STROBE_250),
2524
2525 /* Port256 - Port258 */
2526 GPIO_FN(MSIOF0_SYNC),
2527 GPIO_FN(MSIOF0_RXD),
2528 GPIO_FN(MSIOF0_SCK),
2529
2530 /* Port259 */
2531 GPIO_FN(MSIOF0_SS2),
2532 GPIO_FN(VIO_CKO3_259),
2533
2534 /* Port260 */
2535 GPIO_FN(MSIOF0_TXD),
2536
2537 /* Port261 */
2538 GPIO_FN(SCIFB1_SCK_261),
2539 GPIO_FN(CHSCIF1_HSCK),
2540
2541 /* Port262 */
2542 GPIO_FN(SCIFB2_SCK_262),
2543
2544 /* Port263 - Port266 FN1 */
2545 GPIO_FN(MSIOF1_SS2),
2546 GPIO_FN(MSIOF1_TXD),
2547 GPIO_FN(MSIOF1_RXD),
2548 GPIO_FN(MSIOF1_SS1),
2549
2550 /* Port263 - Port266 FN4 */
2551 GPIO_FN(MSIOF5_SS2),
2552 GPIO_FN(MSIOF5_TXD),
2553 GPIO_FN(MSIOF5_RXD),
2554 GPIO_FN(MSIOF5_SS1),
2555
2556 /* Port267 */
2557 GPIO_FN(MSIOF0_SS1),
2558
2559 /* Port268 */
2560 GPIO_FN(MSIOF1_SCK),
2561 GPIO_FN(MSIOF5_SCK),
2562
2563 /* Port269 */
2564 GPIO_FN(MSIOF1_SYNC),
2565 GPIO_FN(MSIOF5_SYNC),
2566
2567 /* Port270 - Port273 FN1 */
2568 GPIO_FN(MSIOF2_SS1),
2569 GPIO_FN(MSIOF2_SS2),
2570 GPIO_FN(MSIOF3_SS2),
2571 GPIO_FN(MSIOF3_SS1),
2572
2573 /* Port270 - Port273 FN3 */
2574 GPIO_FN(VIO_CKO5_270),
2575 GPIO_FN(VIO_CKO2_271),
2576 GPIO_FN(VIO_CKO1_272),
2577 GPIO_FN(VIO_CKO4_273),
2578
2579 /* Port274 */
2580 GPIO_FN(MSIOF4_SS2),
2581 GPIO_FN(TPU1TO0),
2582
2583 /* Port275 - Port280 */
2584 GPIO_FN(IC_DP),
2585 GPIO_FN(SIM0_RST),
2586 GPIO_FN(IC_DM),
2587 GPIO_FN(SIM0_BSICOMP),
2588 GPIO_FN(SIM0_CLK),
2589 GPIO_FN(SIM0_IO),
2590
2591 /* Port281 */
2592 GPIO_FN(SIM1_IO),
2593 GPIO_FN(PDM2_DATA_281),
2594
2595 /* Port282 */
2596 GPIO_FN(SIM1_CLK),
2597 GPIO_FN(PDM2_CLK_282),
2598
2599 /* Port283 */
2600 GPIO_FN(SIM1_RST),
2601
2602 /* Port289 */
2603 GPIO_FN(SDHID1_0),
2604 GPIO_FN(STMDATA0_2),
2605
2606 /* Port290 */
2607 GPIO_FN(SDHID1_1),
2608 GPIO_FN(STMDATA1_2),
2609 GPIO_FN(IRQ51),
2610
2611 /* Port291 - Port294 FN1 */
2612 GPIO_FN(SDHID1_2),
2613 GPIO_FN(SDHID1_3),
2614 GPIO_FN(SDHICLK1),
2615 GPIO_FN(SDHICMD1),
2616
2617 /* Port291 - Port294 FN3 */
2618 GPIO_FN(STMDATA2_2),
2619 GPIO_FN(STMDATA3_2),
2620 GPIO_FN(STMCLK_2),
2621 GPIO_FN(STMSIDI_2),
2622
2623 /* Port295 */
2624 GPIO_FN(SDHID2_0),
2625 GPIO_FN(MSIOF4_TXD),
2626 GPIO_FN(SCIFB2_TXD_295),
2627 GPIO_FN(MSIOF6_TXD),
2628
2629 /* Port296 */
2630 GPIO_FN(SDHID2_1),
2631 GPIO_FN(MSIOF6_SS2),
2632 GPIO_FN(IRQ52),
2633
2634 /* Port297 - Port300 FN1 */
2635 GPIO_FN(SDHID2_2),
2636 GPIO_FN(SDHID2_3),
2637 GPIO_FN(SDHICLK2),
2638 GPIO_FN(SDHICMD2),
2639
2640 /* Port297 - Port300 FN2 */
2641 GPIO_FN(MSIOF4_RXD),
2642 GPIO_FN(MSIOF4_SYNC),
2643 GPIO_FN(MSIOF4_SCK),
2644 GPIO_FN(MSIOF4_SS1),
2645
2646 /* Port297 - Port300 FN3 */
2647 GPIO_FN(SCIFB2_RXD_297),
2648 GPIO_FN(SCIFB2_CTS_298),
2649 GPIO_FN(SCIFB2_SCK_299),
2650 GPIO_FN(SCIFB2_RTS_300),
2651
2652 /* Port297 - Port300 FN4 */
2653 GPIO_FN(MSIOF6_RXD),
2654 GPIO_FN(MSIOF6_SYNC),
2655 GPIO_FN(MSIOF6_SCK),
2656 GPIO_FN(MSIOF6_SS1),
2657
2658 /* Port301 */
2659 GPIO_FN(SDHICD0),
2660 GPIO_FN(IRQ50),
2661
2662 /* Port302 - Port306 FN1 */
2663 GPIO_FN(SDHID0_0),
2664 GPIO_FN(SDHID0_1),
2665 GPIO_FN(SDHID0_2),
2666 GPIO_FN(SDHID0_3),
2667 GPIO_FN(SDHICMD0),
2668
2669 /* Port302 - Port306 FN3 */
2670 GPIO_FN(STMDATA0_1),
2671 GPIO_FN(STMDATA1_1),
2672 GPIO_FN(STMDATA2_1),
2673 GPIO_FN(STMDATA3_1),
2674 GPIO_FN(STMSIDI_1),
2675
2676 /* Port307 */
2677 GPIO_FN(SDHIWP0),
2678
2679 /* Port308 */
2680 GPIO_FN(SDHICLK0),
2681 GPIO_FN(STMCLK_1),
2682
2683 /* Port320 - Port329 */
2684 GPIO_FN(IRQ16),
2685 GPIO_FN(IRQ17),
2686 GPIO_FN(IRQ28),
2687 GPIO_FN(IRQ29),
2688 GPIO_FN(IRQ30),
2689 GPIO_FN(IRQ53),
2690 GPIO_FN(IRQ54),
2691 GPIO_FN(IRQ55),
2692 GPIO_FN(IRQ56),
2693 GPIO_FN(IRQ57),
2694};
2695
2696static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2697
2698 PORTCR(0, 0xe6050000),
2699 PORTCR(1, 0xe6050001),
2700 PORTCR(2, 0xe6050002),
2701 PORTCR(3, 0xe6050003),
2702 PORTCR(4, 0xe6050004),
2703 PORTCR(5, 0xe6050005),
2704 PORTCR(6, 0xe6050006),
2705 PORTCR(7, 0xe6050007),
2706 PORTCR(8, 0xe6050008),
2707 PORTCR(9, 0xe6050009),
2708 PORTCR(10, 0xe605000A),
2709 PORTCR(11, 0xe605000B),
2710 PORTCR(12, 0xe605000C),
2711 PORTCR(13, 0xe605000D),
2712 PORTCR(14, 0xe605000E),
2713 PORTCR(15, 0xe605000F),
2714 PORTCR(16, 0xe6050010),
2715 PORTCR(17, 0xe6050011),
2716 PORTCR(18, 0xe6050012),
2717 PORTCR(19, 0xe6050013),
2718 PORTCR(20, 0xe6050014),
2719 PORTCR(21, 0xe6050015),
2720 PORTCR(22, 0xe6050016),
2721 PORTCR(23, 0xe6050017),
2722 PORTCR(24, 0xe6050018),
2723 PORTCR(25, 0xe6050019),
2724 PORTCR(26, 0xe605001A),
2725 PORTCR(27, 0xe605001B),
2726 PORTCR(28, 0xe605001C),
2727 PORTCR(29, 0xe605001D),
2728 PORTCR(30, 0xe605001E),
2729 PORTCR(32, 0xe6051020),
2730 PORTCR(33, 0xe6051021),
2731 PORTCR(34, 0xe6051022),
2732 PORTCR(35, 0xe6051023),
2733 PORTCR(36, 0xe6051024),
2734 PORTCR(37, 0xe6051025),
2735 PORTCR(38, 0xe6051026),
2736 PORTCR(39, 0xe6051027),
2737 PORTCR(40, 0xe6051028),
2738 PORTCR(64, 0xe6050040),
2739 PORTCR(65, 0xe6050041),
2740 PORTCR(66, 0xe6050042),
2741 PORTCR(67, 0xe6050043),
2742 PORTCR(68, 0xe6050044),
2743 PORTCR(69, 0xe6050045),
2744 PORTCR(70, 0xe6050046),
2745 PORTCR(71, 0xe6050047),
2746 PORTCR(72, 0xe6050048),
2747 PORTCR(73, 0xe6050049),
2748 PORTCR(74, 0xe605004A),
2749 PORTCR(75, 0xe605004B),
2750 PORTCR(76, 0xe605004C),
2751 PORTCR(77, 0xe605004D),
2752 PORTCR(78, 0xe605004E),
2753 PORTCR(79, 0xe605004F),
2754 PORTCR(80, 0xe6050050),
2755 PORTCR(81, 0xe6050051),
2756 PORTCR(82, 0xe6050052),
2757 PORTCR(83, 0xe6050053),
2758 PORTCR(84, 0xe6050054),
2759 PORTCR(85, 0xe6050055),
2760 PORTCR(96, 0xe6051060),
2761 PORTCR(97, 0xe6051061),
2762 PORTCR(98, 0xe6051062),
2763 PORTCR(99, 0xe6051063),
2764 PORTCR(100, 0xe6051064),
2765 PORTCR(101, 0xe6051065),
2766 PORTCR(102, 0xe6051066),
2767 PORTCR(103, 0xe6051067),
2768 PORTCR(104, 0xe6051068),
2769 PORTCR(105, 0xe6051069),
2770 PORTCR(106, 0xe605106A),
2771 PORTCR(107, 0xe605106B),
2772 PORTCR(108, 0xe605106C),
2773 PORTCR(109, 0xe605106D),
2774 PORTCR(110, 0xe605106E),
2775 PORTCR(111, 0xe605106F),
2776 PORTCR(112, 0xe6051070),
2777 PORTCR(113, 0xe6051071),
2778 PORTCR(114, 0xe6051072),
2779 PORTCR(115, 0xe6051073),
2780 PORTCR(116, 0xe6051074),
2781 PORTCR(117, 0xe6051075),
2782 PORTCR(118, 0xe6051076),
2783 PORTCR(119, 0xe6051077),
2784 PORTCR(120, 0xe6051078),
2785 PORTCR(121, 0xe6051079),
2786 PORTCR(122, 0xe605107A),
2787 PORTCR(123, 0xe605107B),
2788 PORTCR(124, 0xe605107C),
2789 PORTCR(125, 0xe605107D),
2790 PORTCR(126, 0xe605107E),
2791 PORTCR(128, 0xe6051080),
2792 PORTCR(129, 0xe6051081),
2793 PORTCR(130, 0xe6051082),
2794 PORTCR(131, 0xe6051083),
2795 PORTCR(132, 0xe6051084),
2796 PORTCR(133, 0xe6051085),
2797 PORTCR(134, 0xe6051086),
2798 PORTCR(160, 0xe60520A0),
2799 PORTCR(161, 0xe60520A1),
2800 PORTCR(162, 0xe60520A2),
2801 PORTCR(163, 0xe60520A3),
2802 PORTCR(164, 0xe60520A4),
2803 PORTCR(165, 0xe60520A5),
2804 PORTCR(166, 0xe60520A6),
2805 PORTCR(167, 0xe60520A7),
2806 PORTCR(168, 0xe60520A8),
2807 PORTCR(169, 0xe60520A9),
2808 PORTCR(170, 0xe60520AA),
2809 PORTCR(171, 0xe60520AB),
2810 PORTCR(172, 0xe60520AC),
2811 PORTCR(173, 0xe60520AD),
2812 PORTCR(174, 0xe60520AE),
2813 PORTCR(175, 0xe60520AF),
2814 PORTCR(176, 0xe60520B0),
2815 PORTCR(177, 0xe60520B1),
2816 PORTCR(178, 0xe60520B2),
2817 PORTCR(192, 0xe60520C0),
2818 PORTCR(193, 0xe60520C1),
2819 PORTCR(194, 0xe60520C2),
2820 PORTCR(195, 0xe60520C3),
2821 PORTCR(196, 0xe60520C4),
2822 PORTCR(197, 0xe60520C5),
2823 PORTCR(198, 0xe60520C6),
2824 PORTCR(199, 0xe60520C7),
2825 PORTCR(200, 0xe60520C8),
2826 PORTCR(201, 0xe60520C9),
2827 PORTCR(202, 0xe60520CA),
2828 PORTCR(203, 0xe60520CB),
2829 PORTCR(204, 0xe60520CC),
2830 PORTCR(205, 0xe60520CD),
2831 PORTCR(206, 0xe60520CE),
2832 PORTCR(207, 0xe60520CF),
2833 PORTCR(208, 0xe60520D0),
2834 PORTCR(209, 0xe60520D1),
2835 PORTCR(210, 0xe60520D2),
2836 PORTCR(211, 0xe60520D3),
2837 PORTCR(212, 0xe60520D4),
2838 PORTCR(213, 0xe60520D5),
2839 PORTCR(214, 0xe60520D6),
2840 PORTCR(215, 0xe60520D7),
2841 PORTCR(216, 0xe60520D8),
2842 PORTCR(217, 0xe60520D9),
2843 PORTCR(218, 0xe60520DA),
2844 PORTCR(219, 0xe60520DB),
2845 PORTCR(220, 0xe60520DC),
2846 PORTCR(221, 0xe60520DD),
2847 PORTCR(222, 0xe60520DE),
2848 PORTCR(224, 0xe60520E0),
2849 PORTCR(225, 0xe60520E1),
2850 PORTCR(226, 0xe60520E2),
2851 PORTCR(227, 0xe60520E3),
2852 PORTCR(228, 0xe60520E4),
2853 PORTCR(229, 0xe60520E5),
2854 PORTCR(230, 0xe60520e6),
2855 PORTCR(231, 0xe60520E7),
2856 PORTCR(232, 0xe60520E8),
2857 PORTCR(233, 0xe60520E9),
2858 PORTCR(234, 0xe60520EA),
2859 PORTCR(235, 0xe60520EB),
2860 PORTCR(236, 0xe60520EC),
2861 PORTCR(237, 0xe60520ED),
2862 PORTCR(238, 0xe60520EE),
2863 PORTCR(239, 0xe60520EF),
2864 PORTCR(240, 0xe60520F0),
2865 PORTCR(241, 0xe60520F1),
2866 PORTCR(242, 0xe60520F2),
2867 PORTCR(243, 0xe60520F3),
2868 PORTCR(244, 0xe60520F4),
2869 PORTCR(245, 0xe60520F5),
2870 PORTCR(246, 0xe60520F6),
2871 PORTCR(247, 0xe60520F7),
2872 PORTCR(248, 0xe60520F8),
2873 PORTCR(249, 0xe60520F9),
2874 PORTCR(250, 0xe60520FA),
2875 PORTCR(256, 0xe6052100),
2876 PORTCR(257, 0xe6052101),
2877 PORTCR(258, 0xe6052102),
2878 PORTCR(259, 0xe6052103),
2879 PORTCR(260, 0xe6052104),
2880 PORTCR(261, 0xe6052105),
2881 PORTCR(262, 0xe6052106),
2882 PORTCR(263, 0xe6052107),
2883 PORTCR(264, 0xe6052108),
2884 PORTCR(265, 0xe6052109),
2885 PORTCR(266, 0xe605210A),
2886 PORTCR(267, 0xe605210B),
2887 PORTCR(268, 0xe605210C),
2888 PORTCR(269, 0xe605210D),
2889 PORTCR(270, 0xe605210E),
2890 PORTCR(271, 0xe605210F),
2891 PORTCR(272, 0xe6052110),
2892 PORTCR(273, 0xe6052111),
2893 PORTCR(274, 0xe6052112),
2894 PORTCR(275, 0xe6052113),
2895 PORTCR(276, 0xe6052114),
2896 PORTCR(277, 0xe6052115),
2897 PORTCR(278, 0xe6052116),
2898 PORTCR(279, 0xe6052117),
2899 PORTCR(280, 0xe6052118),
2900 PORTCR(281, 0xe6052119),
2901 PORTCR(282, 0xe605211A),
2902 PORTCR(283, 0xe605211B),
2903 PORTCR(288, 0xe6053120),
2904 PORTCR(289, 0xe6053121),
2905 PORTCR(290, 0xe6053122),
2906 PORTCR(291, 0xe6053123),
2907 PORTCR(292, 0xe6053124),
2908 PORTCR(293, 0xe6053125),
2909 PORTCR(294, 0xe6053126),
2910 PORTCR(295, 0xe6053127),
2911 PORTCR(296, 0xe6053128),
2912 PORTCR(297, 0xe6053129),
2913 PORTCR(298, 0xe605312A),
2914 PORTCR(299, 0xe605312B),
2915 PORTCR(300, 0xe605312C),
2916 PORTCR(301, 0xe605312D),
2917 PORTCR(302, 0xe605312E),
2918 PORTCR(303, 0xe605312F),
2919 PORTCR(304, 0xe6053130),
2920 PORTCR(305, 0xe6053131),
2921 PORTCR(306, 0xe6053132),
2922 PORTCR(307, 0xe6053133),
2923 PORTCR(308, 0xe6053134),
2924 PORTCR(320, 0xe6053140),
2925 PORTCR(321, 0xe6053141),
2926 PORTCR(322, 0xe6053142),
2927 PORTCR(323, 0xe6053143),
2928 PORTCR(324, 0xe6053144),
2929 PORTCR(325, 0xe6053145),
2930 PORTCR(326, 0xe6053146),
2931 PORTCR(327, 0xe6053147),
2932 PORTCR(328, 0xe6053148),
2933 PORTCR(329, 0xe6053149),
2934
2935 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
2936 MSEL1CR_31_0, MSEL1CR_31_1,
2937 0, 0,
2938 0, 0,
2939 0, 0,
2940 MSEL1CR_27_0, MSEL1CR_27_1,
2941 0, 0,
2942 MSEL1CR_25_0, MSEL1CR_25_1,
2943 MSEL1CR_24_0, MSEL1CR_24_1,
2944 0, 0,
2945 MSEL1CR_22_0, MSEL1CR_22_1,
2946 MSEL1CR_21_0, MSEL1CR_21_1,
2947 MSEL1CR_20_0, MSEL1CR_20_1,
2948 MSEL1CR_19_0, MSEL1CR_19_1,
2949 MSEL1CR_18_0, MSEL1CR_18_1,
2950 MSEL1CR_17_0, MSEL1CR_17_1,
2951 MSEL1CR_16_0, MSEL1CR_16_1,
2952 MSEL1CR_15_0, MSEL1CR_15_1,
2953 MSEL1CR_14_0, MSEL1CR_14_1,
2954 MSEL1CR_13_0, MSEL1CR_13_1,
2955 MSEL1CR_12_0, MSEL1CR_12_1,
2956 MSEL1CR_11_0, MSEL1CR_11_1,
2957 MSEL1CR_10_0, MSEL1CR_10_1,
2958 MSEL1CR_09_0, MSEL1CR_09_1,
2959 MSEL1CR_08_0, MSEL1CR_08_1,
2960 MSEL1CR_07_0, MSEL1CR_07_1,
2961 MSEL1CR_06_0, MSEL1CR_06_1,
2962 MSEL1CR_05_0, MSEL1CR_05_1,
2963 MSEL1CR_04_0, MSEL1CR_04_1,
2964 MSEL1CR_03_0, MSEL1CR_03_1,
2965 MSEL1CR_02_0, MSEL1CR_02_1,
2966 MSEL1CR_01_0, MSEL1CR_01_1,
2967 MSEL1CR_00_0, MSEL1CR_00_1,
2968 }
2969 },
2970 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
2971 MSEL3CR_31_0, MSEL3CR_31_1,
2972 0, 0,
2973 0, 0,
2974 MSEL3CR_28_0, MSEL3CR_28_1,
2975 MSEL3CR_27_0, MSEL3CR_27_1,
2976 MSEL3CR_26_0, MSEL3CR_26_1,
2977 0, 0,
2978 0, 0,
2979 MSEL3CR_23_0, MSEL3CR_23_1,
2980 MSEL3CR_22_0, MSEL3CR_22_1,
2981 MSEL3CR_21_0, MSEL3CR_21_1,
2982 MSEL3CR_20_0, MSEL3CR_20_1,
2983 MSEL3CR_19_0, MSEL3CR_19_1,
2984 MSEL3CR_18_0, MSEL3CR_18_1,
2985 MSEL3CR_17_0, MSEL3CR_17_1,
2986 MSEL3CR_16_0, MSEL3CR_16_1,
2987 MSEL3CR_15_0, MSEL3CR_15_1,
2988 0, 0,
2989 0, 0,
2990 MSEL3CR_12_0, MSEL3CR_12_1,
2991 MSEL3CR_11_0, MSEL3CR_11_1,
2992 MSEL3CR_10_0, MSEL3CR_10_1,
2993 MSEL3CR_09_0, MSEL3CR_09_1,
2994 0, 0,
2995 0, 0,
2996 MSEL3CR_06_0, MSEL3CR_06_1,
2997 0, 0,
2998 0, 0,
2999 MSEL3CR_03_0, MSEL3CR_03_1,
3000 0, 0,
3001 MSEL3CR_01_0, MSEL3CR_01_1,
3002 MSEL3CR_00_0, MSEL3CR_00_1,
3003 }
3004 },
3005 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
3006 0, 0,
3007 MSEL4CR_30_0, MSEL4CR_30_1,
3008 MSEL4CR_29_0, MSEL4CR_29_1,
3009 MSEL4CR_28_0, MSEL4CR_28_1,
3010 MSEL4CR_27_0, MSEL4CR_27_1,
3011 MSEL4CR_26_0, MSEL4CR_26_1,
3012 MSEL4CR_25_0, MSEL4CR_25_1,
3013 MSEL4CR_24_0, MSEL4CR_24_1,
3014 MSEL4CR_23_0, MSEL4CR_23_1,
3015 MSEL4CR_22_0, MSEL4CR_22_1,
3016 MSEL4CR_21_0, MSEL4CR_21_1,
3017 MSEL4CR_20_0, MSEL4CR_20_1,
3018 MSEL4CR_19_0, MSEL4CR_19_1,
3019 MSEL4CR_18_0, MSEL4CR_18_1,
3020 MSEL4CR_17_0, MSEL4CR_17_1,
3021 MSEL4CR_16_0, MSEL4CR_16_1,
3022 MSEL4CR_15_0, MSEL4CR_15_1,
3023 MSEL4CR_14_0, MSEL4CR_14_1,
3024 MSEL4CR_13_0, MSEL4CR_13_1,
3025 MSEL4CR_12_0, MSEL4CR_12_1,
3026 MSEL4CR_11_0, MSEL4CR_11_1,
3027 MSEL4CR_10_0, MSEL4CR_10_1,
3028 MSEL4CR_09_0, MSEL4CR_09_1,
3029 0, 0,
3030 MSEL4CR_07_0, MSEL4CR_07_1,
3031 0, 0,
3032 0, 0,
3033 MSEL4CR_04_0, MSEL4CR_04_1,
3034 0, 0,
3035 0, 0,
3036 MSEL4CR_01_0, MSEL4CR_01_1,
3037 0, 0,
3038 }
3039 },
3040 { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) {
3041 MSEL5CR_31_0, MSEL5CR_31_1,
3042 MSEL5CR_30_0, MSEL5CR_30_1,
3043 MSEL5CR_29_0, MSEL5CR_29_1,
3044 MSEL5CR_28_0, MSEL5CR_28_1,
3045 MSEL5CR_27_0, MSEL5CR_27_1,
3046 MSEL5CR_26_0, MSEL5CR_26_1,
3047 MSEL5CR_25_0, MSEL5CR_25_1,
3048 MSEL5CR_24_0, MSEL5CR_24_1,
3049 MSEL5CR_23_0, MSEL5CR_23_1,
3050 MSEL5CR_22_0, MSEL5CR_22_1,
3051 MSEL5CR_21_0, MSEL5CR_21_1,
3052 MSEL5CR_20_0, MSEL5CR_20_1,
3053 MSEL5CR_19_0, MSEL5CR_19_1,
3054 MSEL5CR_18_0, MSEL5CR_18_1,
3055 MSEL5CR_17_0, MSEL5CR_17_1,
3056 MSEL5CR_16_0, MSEL5CR_16_1,
3057 MSEL5CR_15_0, MSEL5CR_15_1,
3058 MSEL5CR_14_0, MSEL5CR_14_1,
3059 MSEL5CR_13_0, MSEL5CR_13_1,
3060 MSEL5CR_12_0, MSEL5CR_12_1,
3061 MSEL5CR_11_0, MSEL5CR_11_1,
3062 MSEL5CR_10_0, MSEL5CR_10_1,
3063 MSEL5CR_09_0, MSEL5CR_09_1,
3064 MSEL5CR_08_0, MSEL5CR_08_1,
3065 MSEL5CR_07_0, MSEL5CR_07_1,
3066 MSEL5CR_06_0, MSEL5CR_06_1,
3067 0, 0,
3068 0, 0,
3069 0, 0,
3070 0, 0,
3071 0, 0,
3072 0, 0,
3073 }
3074 },
3075 { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) {
3076 0, 0,
3077 0, 0,
3078 0, 0,
3079 0, 0,
3080 0, 0,
3081 0, 0,
3082 0, 0,
3083 0, 0,
3084 0, 0,
3085 0, 0,
3086 0, 0,
3087 0, 0,
3088 0, 0,
3089 0, 0,
3090 0, 0,
3091 MSEL8CR_16_0, MSEL8CR_16_1,
3092 0, 0,
3093 0, 0,
3094 0, 0,
3095 0, 0,
3096 0, 0,
3097 0, 0,
3098 0, 0,
3099 0, 0,
3100 0, 0,
3101 0, 0,
3102 0, 0,
3103 0, 0,
3104 0, 0,
3105 0, 0,
3106 MSEL8CR_01_0, MSEL8CR_01_1,
3107 MSEL8CR_00_0, MSEL8CR_00_1,
3108 }
3109 },
3110 { },
3111};
3112
3113static const struct pinmux_data_reg pinmux_data_regs[] = {
3114
3115 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
3116 0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
3117 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
3118 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
3119 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
3120 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
3121 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
3122 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
3123 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
3124 }
3125 },
3126 { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
3127 0, 0, 0, 0,
3128 0, 0, 0, 0,
3129 0, 0, 0, 0,
3130 0, 0, 0, 0,
3131 0, 0, 0, 0,
3132 0, 0, 0, PORT40_DATA,
3133 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
3134 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
3135 }
3136 },
3137 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) {
3138 0, 0, 0, 0,
3139 0, 0, 0, 0,
3140 0, 0, PORT85_DATA, PORT84_DATA,
3141 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
3142 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
3143 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
3144 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
3145 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
3146 }
3147 },
3148 { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
3149 0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
3150 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
3151 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
3152 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
3153 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
3154 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
3155 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
3156 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
3157 }
3158 },
3159 { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
3160 0, 0, 0, 0,
3161 0, 0, 0, 0,
3162 0, 0, 0, 0,
3163 0, 0, 0, 0,
3164 0, 0, 0, 0,
3165 0, 0, 0, 0,
3166 0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
3167 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
3168 }
3169 },
3170 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
3171 0, 0, 0, 0,
3172 0, 0, 0, 0,
3173 0, 0, 0, 0,
3174 0, PORT178_DATA, PORT177_DATA, PORT176_DATA,
3175 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
3176 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
3177 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
3178 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
3179 }
3180 },
3181 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
3182 0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
3183 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
3184 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
3185 PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
3186 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
3187 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
3188 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
3189 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
3190 }
3191 },
3192 { PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) {
3193 0, 0, 0, 0,
3194 0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
3195 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
3196 PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
3197 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
3198 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
3199 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
3200 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
3201 }
3202 },
3203 { PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) {
3204 0, 0, 0, 0,
3205 PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
3206 PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
3207 PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
3208 PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
3209 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
3210 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
3211 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
3212 }
3213 },
3214 { PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) {
3215 0, 0, 0, 0,
3216 0, 0, 0, 0,
3217 0, 0, 0, PORT308_DATA,
3218 PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
3219 PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
3220 PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
3221 PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
3222 PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
3223 }
3224 },
3225 { PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) {
3226 0, 0, 0, 0,
3227 0, 0, 0, 0,
3228 0, 0, 0, 0,
3229 0, 0, 0, 0,
3230 0, 0, 0, 0,
3231 0, 0, PORT329_DATA, PORT328_DATA,
3232 PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
3233 PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
3234 }
3235 },
3236 { },
3237};
3238
Magnus Dammc96931c2013-03-26 22:50:09 +0900[diff] [blame]3239static const struct pinmux_irq pinmux_irqs[] = {
3240 PINMUX_IRQ(irq_pin(0), 0),
3241 PINMUX_IRQ(irq_pin(1), 1),
3242 PINMUX_IRQ(irq_pin(2), 2),
3243 PINMUX_IRQ(irq_pin(3), 3),
3244 PINMUX_IRQ(irq_pin(4), 4),
3245 PINMUX_IRQ(irq_pin(5), 5),
3246 PINMUX_IRQ(irq_pin(6), 6),
3247 PINMUX_IRQ(irq_pin(7), 7),
3248 PINMUX_IRQ(irq_pin(8), 8),
3249 PINMUX_IRQ(irq_pin(9), 9),
3250 PINMUX_IRQ(irq_pin(10), 10),
3251 PINMUX_IRQ(irq_pin(11), 11),
3252 PINMUX_IRQ(irq_pin(12), 12),
3253 PINMUX_IRQ(irq_pin(13), 13),
3254 PINMUX_IRQ(irq_pin(14), 14),
3255 PINMUX_IRQ(irq_pin(15), 15),
3256 PINMUX_IRQ(irq_pin(16), 320),
3257 PINMUX_IRQ(irq_pin(17), 321),
3258 PINMUX_IRQ(irq_pin(18), 85),
3259 PINMUX_IRQ(irq_pin(19), 84),
3260 PINMUX_IRQ(irq_pin(20), 160),
3261 PINMUX_IRQ(irq_pin(21), 161),
3262 PINMUX_IRQ(irq_pin(22), 162),
3263 PINMUX_IRQ(irq_pin(23), 163),
3264 PINMUX_IRQ(irq_pin(24), 175),
3265 PINMUX_IRQ(irq_pin(25), 176),
3266 PINMUX_IRQ(irq_pin(26), 177),
3267 PINMUX_IRQ(irq_pin(27), 178),
3268 PINMUX_IRQ(irq_pin(28), 322),
3269 PINMUX_IRQ(irq_pin(29), 323),
3270 PINMUX_IRQ(irq_pin(30), 324),
3271 PINMUX_IRQ(irq_pin(31), 192),
3272 PINMUX_IRQ(irq_pin(32), 193),
3273 PINMUX_IRQ(irq_pin(33), 194),
3274 PINMUX_IRQ(irq_pin(34), 195),
3275 PINMUX_IRQ(irq_pin(35), 196),
3276 PINMUX_IRQ(irq_pin(36), 197),
3277 PINMUX_IRQ(irq_pin(37), 198),
3278 PINMUX_IRQ(irq_pin(38), 199),
3279 PINMUX_IRQ(irq_pin(39), 200),
3280 PINMUX_IRQ(irq_pin(40), 66),
3281 PINMUX_IRQ(irq_pin(41), 102),
3282 PINMUX_IRQ(irq_pin(42), 103),
3283 PINMUX_IRQ(irq_pin(43), 109),
3284 PINMUX_IRQ(irq_pin(44), 110),
3285 PINMUX_IRQ(irq_pin(45), 111),
3286 PINMUX_IRQ(irq_pin(46), 112),
3287 PINMUX_IRQ(irq_pin(47), 113),
3288 PINMUX_IRQ(irq_pin(48), 114),
3289 PINMUX_IRQ(irq_pin(49), 115),
3290 PINMUX_IRQ(irq_pin(50), 301),
3291 PINMUX_IRQ(irq_pin(51), 290),
3292 PINMUX_IRQ(irq_pin(52), 296),
3293 PINMUX_IRQ(irq_pin(53), 325),
3294 PINMUX_IRQ(irq_pin(54), 326),
3295 PINMUX_IRQ(irq_pin(55), 327),
3296 PINMUX_IRQ(irq_pin(56), 328),
3297 PINMUX_IRQ(irq_pin(57), 329),
3298};
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]3299
3300#define PORTCR_PULMD_OFF (0 << 6)
3301#define PORTCR_PULMD_DOWN (2 << 6)
3302#define PORTCR_PULMD_UP (3 << 6)
3303#define PORTCR_PULMD_MASK (3 << 6)
3304
3305static const unsigned int r8a73a4_portcr_offsets[] = {
3306 0x00000000, 0x00001000, 0x00000000, 0x00001000,
3307 0x00001000, 0x00002000, 0x00002000, 0x00002000,
3308 0x00002000, 0x00003000, 0x00003000,
3309};
3310
3311static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
3312 unsigned int pin)
3313{
3314 void __iomem *addr;
3315
3316 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
3317
3318 switch (ioread8(addr) & PORTCR_PULMD_MASK) {
3319 case PORTCR_PULMD_UP:
3320 return PIN_CONFIG_BIAS_PULL_UP;
3321 case PORTCR_PULMD_DOWN:
3322 return PIN_CONFIG_BIAS_PULL_DOWN;
3323 case PORTCR_PULMD_OFF:
3324 default:
3325 return PIN_CONFIG_BIAS_DISABLE;
3326 }
3327}
3328
3329static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3330 unsigned int bias)
3331{
3332 void __iomem *addr;
3333 u32 value;
3334
3335 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
3336 value = ioread8(addr) & ~PORTCR_PULMD_MASK;
3337
3338 switch (bias) {
3339 case PIN_CONFIG_BIAS_PULL_UP:
3340 value |= PORTCR_PULMD_UP;
3341 break;
3342 case PIN_CONFIG_BIAS_PULL_DOWN:
3343 value |= PORTCR_PULMD_DOWN;
3344 break;
3345 }
3346
3347 iowrite8(value, addr);
3348}
3349
3350static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = {
3351 .get_bias = r8a73a4_pinmux_get_bias,
3352 .set_bias = r8a73a4_pinmux_set_bias,
3353};
3354
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]3355const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
3356 .name = "r8a73a4_pfc",
Magnus Damm57ef73b2013-03-26 22:50:27 +0900[diff] [blame]3357 .ops = &r8a73a4_pinmux_ops,
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]3358
3359 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
3360 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
3361 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
3362 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
3363 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3364
3365 .pins = pinmux_pins,
3366 .nr_pins = ARRAY_SIZE(pinmux_pins),
Magnus Damm172fd612013-03-26 22:50:36 +0900[diff] [blame^]3367
Magnus Dammf365bfc2013-03-26 22:49:59 +0900[diff] [blame]3368 .ranges = pinmux_ranges,
3369 .nr_ranges = ARRAY_SIZE(pinmux_ranges),
Magnus Damm172fd612013-03-26 22:50:36 +0900[diff] [blame^]3370
3371 .groups = pinmux_groups,
3372 .nr_groups = ARRAY_SIZE(pinmux_groups),
3373 .functions = pinmux_functions,
3374 .nr_functions = ARRAY_SIZE(pinmux_functions),
3375
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]3376 .func_gpios = pinmux_func_gpios,
3377 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
3378
3379 .cfg_regs = pinmux_config_regs,
3380 .data_regs = pinmux_data_regs,
3381
3382 .gpio_data = pinmux_data,
3383 .gpio_data_size = ARRAY_SIZE(pinmux_data),
Magnus Dammc96931c2013-03-26 22:50:09 +0900[diff] [blame]3384
3385 .gpio_irq = pinmux_irqs,
3386 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
Magnus Dammc98f6c22013-03-26 22:49:49 +0900[diff] [blame]3387};