blob: cef9616f330aa06fc75769a79fbcf62211b3fea7 [file] [log] [blame]
Jason Cooper3d468b62012-02-27 16:07:13 +00001/include/ "skeleton.dtsi"
2
3/ {
Andrew Lunn77843502012-07-18 19:22:54 +02004 compatible = "marvell,kirkwood";
Andrew Lunn278b45b2012-06-27 13:40:04 +02005 interrupt-parent = <&intc>;
6
7 intc: interrupt-controller {
8 compatible = "marvell,orion-intc", "marvell,intc";
9 interrupt-controller;
10 #interrupt-cells = <1>;
11 reg = <0xf1020204 0x04>,
12 <0xf1020214 0x04>;
13 };
Jason Cooper3d468b62012-02-27 16:07:13 +000014
Jason Cooper163f2ce2012-03-15 01:00:27 +000015 ocp@f1000000 {
16 compatible = "simple-bus";
Jamie Lentin858156b2012-04-18 11:06:42 +010017 ranges = <0 0xf1000000 0x4000000>;
Jason Cooper163f2ce2012-03-15 01:00:27 +000018 #address-cells = <1>;
19 #size-cells = <1>;
20
Andrew Lunn278b45b2012-06-27 13:40:04 +020021 gpio0: gpio@10100 {
22 compatible = "marvell,orion-gpio";
23 #gpio-cells = <2>;
24 gpio-controller;
25 reg = <0x10100 0x40>;
26 ngpio = <32>;
27 interrupts = <35>, <36>, <37>, <38>;
28 };
29
30 gpio1: gpio@10140 {
31 compatible = "marvell,orion-gpio";
32 #gpio-cells = <2>;
33 gpio-controller;
34 reg = <0x10140 0x40>;
35 ngpio = <18>;
36 interrupts = <39>, <40>, <41>;
37 };
38
Jason Cooper163f2ce2012-03-15 01:00:27 +000039 serial@12000 {
40 compatible = "ns16550a";
41 reg = <0x12000 0x100>;
42 reg-shift = <2>;
43 interrupts = <33>;
44 /* set clock-frequency in board dts */
45 status = "disabled";
46 };
47
48 serial@12100 {
49 compatible = "ns16550a";
50 reg = <0x12100 0x100>;
51 reg-shift = <2>;
52 interrupts = <34>;
53 /* set clock-frequency in board dts */
54 status = "disabled";
55 };
Jason Coopere871b872012-03-06 23:55:04 +000056
57 rtc@10300 {
Andrew Lunn77843502012-07-18 19:22:54 +020058 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
Jason Coopere871b872012-03-06 23:55:04 +000059 reg = <0x10300 0x20>;
60 interrupts = <53>;
61 };
Jamie Lentin858156b2012-04-18 11:06:42 +010062
Michael Walle76372122012-06-06 20:30:57 +020063 spi@10600 {
64 compatible = "marvell,orion-spi";
65 #address-cells = <1>;
66 #size-cells = <0>;
67 cell-index = <0>;
68 interrupts = <23>;
69 reg = <0x10600 0x28>;
70 status = "disabled";
71 };
72
Andrew Lunn1e7bad02012-06-10 15:20:06 +020073 wdt@20300 {
74 compatible = "marvell,orion-wdt";
75 reg = <0x20300 0x28>;
76 status = "okay";
77 };
78
Andrew Lunn97b414e2012-06-10 16:45:37 +020079 sata@80000 {
80 compatible = "marvell,orion-sata";
81 reg = <0x80000 0x5000>;
82 interrupts = <21>;
83 status = "disabled";
84 };
85
Jamie Lentin858156b2012-04-18 11:06:42 +010086 nand@3000000 {
87 #address-cells = <1>;
88 #size-cells = <1>;
89 cle = <0>;
90 ale = <1>;
91 bank-width = <1>;
Andrew Lunn77843502012-07-18 19:22:54 +020092 compatible = "marvell,orion-nand";
Jamie Lentin858156b2012-04-18 11:06:42 +010093 reg = <0x3000000 0x400>;
94 chip-delay = <25>;
95 /* set partition map and/or chip-delay in board dts */
96 status = "disabled";
97 };
Andrew Lunne91cac02012-07-20 13:51:55 +020098
99 i2c@11000 {
100 compatible = "marvell,mv64xxx-i2c";
101 reg = <0x11000 0x20>;
102 #address-cells = <1>;
103 #size-cells = <0>;
104 interrupts = <29>;
105 clock-frequency = <100000>;
106 status = "disabled";
107 };
Jason Cooper163f2ce2012-03-15 01:00:27 +0000108 };
109};