| Ken Cox | dbe91a2 | 2012-07-18 23:19:10 -0400 | [diff] [blame] | 1 | |
| 2 | / { |
| 3 | #address-cells = <1>; |
| 4 | #size-cells = <1>; |
| 5 | |
| 6 | cpus { |
| 7 | #address-cells = <1>; |
| 8 | #size-cells = <0>; |
| 9 | |
| 10 | cpu@0 { |
| 11 | device_type = "cpu"; |
| 12 | reg = <0>; |
| 13 | model = "ti,c66x"; |
| 14 | }; |
| 15 | cpu@1 { |
| 16 | device_type = "cpu"; |
| 17 | reg = <1>; |
| 18 | model = "ti,c66x"; |
| 19 | }; |
| 20 | cpu@2 { |
| 21 | device_type = "cpu"; |
| 22 | reg = <2>; |
| 23 | model = "ti,c66x"; |
| 24 | }; |
| 25 | cpu@3 { |
| 26 | device_type = "cpu"; |
| 27 | reg = <3>; |
| 28 | model = "ti,c66x"; |
| 29 | }; |
| 30 | cpu@4 { |
| 31 | device_type = "cpu"; |
| 32 | reg = <4>; |
| 33 | model = "ti,c66x"; |
| 34 | }; |
| 35 | cpu@5 { |
| 36 | device_type = "cpu"; |
| 37 | reg = <5>; |
| 38 | model = "ti,c66x"; |
| 39 | }; |
| 40 | cpu@6 { |
| 41 | device_type = "cpu"; |
| 42 | reg = <6>; |
| 43 | model = "ti,c66x"; |
| 44 | }; |
| 45 | cpu@7 { |
| 46 | device_type = "cpu"; |
| 47 | reg = <7>; |
| 48 | model = "ti,c66x"; |
| 49 | }; |
| 50 | }; |
| 51 | |
| 52 | soc { |
| 53 | compatible = "simple-bus"; |
| 54 | model = "tms320c6678"; |
| 55 | #address-cells = <1>; |
| 56 | #size-cells = <1>; |
| 57 | ranges; |
| 58 | |
| 59 | core_pic: interrupt-controller { |
| 60 | compatible = "ti,c64x+core-pic"; |
| 61 | interrupt-controller; |
| 62 | #interrupt-cells = <1>; |
| 63 | }; |
| 64 | |
| 65 | megamod_pic: interrupt-controller@1800000 { |
| 66 | compatible = "ti,c64x+megamod-pic"; |
| 67 | interrupt-controller; |
| 68 | #interrupt-cells = <1>; |
| 69 | reg = <0x1800000 0x1000>; |
| 70 | interrupt-parent = <&core_pic>; |
| 71 | }; |
| 72 | |
| 73 | cache-controller@1840000 { |
| 74 | compatible = "ti,c64x+cache"; |
| 75 | reg = <0x01840000 0x8400>; |
| 76 | }; |
| 77 | |
| 78 | timer8: timer@2280000 { |
| 79 | compatible = "ti,c64x+timer64"; |
| 80 | ti,core-mask = < 0x01 >; |
| 81 | reg = <0x2280000 0x40>; |
| 82 | }; |
| 83 | |
| 84 | timer9: timer@2290000 { |
| 85 | compatible = "ti,c64x+timer64"; |
| 86 | ti,core-mask = < 0x02 >; |
| 87 | reg = <0x2290000 0x40>; |
| 88 | }; |
| 89 | |
| 90 | timer10: timer@22A0000 { |
| 91 | compatible = "ti,c64x+timer64"; |
| 92 | ti,core-mask = < 0x04 >; |
| 93 | reg = <0x22A0000 0x40>; |
| 94 | }; |
| 95 | |
| 96 | timer11: timer@22B0000 { |
| 97 | compatible = "ti,c64x+timer64"; |
| 98 | ti,core-mask = < 0x08 >; |
| 99 | reg = <0x22B0000 0x40>; |
| 100 | }; |
| 101 | |
| 102 | timer12: timer@22C0000 { |
| 103 | compatible = "ti,c64x+timer64"; |
| 104 | ti,core-mask = < 0x10 >; |
| 105 | reg = <0x22C0000 0x40>; |
| 106 | }; |
| 107 | |
| 108 | timer13: timer@22D0000 { |
| 109 | compatible = "ti,c64x+timer64"; |
| 110 | ti,core-mask = < 0x20 >; |
| 111 | reg = <0x22D0000 0x40>; |
| 112 | }; |
| 113 | |
| 114 | timer14: timer@22E0000 { |
| 115 | compatible = "ti,c64x+timer64"; |
| 116 | ti,core-mask = < 0x40 >; |
| 117 | reg = <0x22E0000 0x40>; |
| 118 | }; |
| 119 | |
| 120 | timer15: timer@22F0000 { |
| 121 | compatible = "ti,c64x+timer64"; |
| 122 | ti,core-mask = < 0x80 >; |
| 123 | reg = <0x22F0000 0x40>; |
| 124 | }; |
| 125 | |
| 126 | clock-controller@2310000 { |
| 127 | compatible = "ti,c6678-pll", "ti,c64x+pll"; |
| 128 | reg = <0x02310000 0x200>; |
| 129 | ti,c64x+pll-bypass-delay = <200>; |
| 130 | ti,c64x+pll-reset-delay = <12000>; |
| 131 | ti,c64x+pll-lock-delay = <80000>; |
| 132 | }; |
| 133 | |
| 134 | device-state-controller@2620000 { |
| 135 | compatible = "ti,c64x+dscr"; |
| 136 | reg = <0x02620000 0x1000>; |
| 137 | |
| 138 | ti,dscr-devstat = <0x20>; |
| 139 | ti,dscr-silicon-rev = <0x18 28 0xf>; |
| 140 | |
| 141 | ti,dscr-mac-fuse-regs = <0x110 1 2 3 4 |
| 142 | 0x114 5 6 0 0>; |
| 143 | |
| 144 | }; |
| 145 | }; |
| 146 | }; |