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review.evervolv.com / android_kernel_oneplus_msm8996 / 173f77e9c5cbddb02eebe17dd9c48d39e5eb86b9 / . / arch / s390 / kernel / head64.S
blob: c108af28bbe890b95ec606300b1129e893071b87 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
Heiko Carstensa53c8fa2012-07-20 11:15:04 +0200[diff] [blame]2 * Copyright IBM Corp. 1999, 2010
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3 *
Heiko Carstens0ad775d2005-11-07 00:59:12 -0800[diff] [blame]4 * Author(s): Hartmut Penner <hp@de.ibm.com>
5 * Martin Schwidefsky <schwidefsky@de.ibm.com>
6 * Rob van der Heij <rvdhei@iae.nl>
7 * Heiko Carstens <heiko.carstens@de.ibm.com>
8 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]9 */
10
Martin Schwidefsky1844c9b2010-02-26 22:37:53 +0100[diff] [blame]11#include <linux/init.h>
Jan Glauber144d6342011-07-24 10:48:19 +0200[diff] [blame]12#include <linux/linkage.h>
Martin Schwidefsky1844c9b2010-02-26 22:37:53 +0100[diff] [blame]13#include <asm/asm-offsets.h>
14#include <asm/thread_info.h>
15#include <asm/page.h>
Heiko Carstensb1b70302006-06-29 14:58:17 +0200[diff] [blame]16
Martin Schwidefsky1844c9b2010-02-26 22:37:53 +0100[diff] [blame]17__HEAD
Jan Glauber144d6342011-07-24 10:48:19 +0200[diff] [blame]18ENTRY(startup_continue)
Martin Schwidefsky1844c9b2010-02-26 22:37:53 +0100[diff] [blame]19 larl %r1,sched_clock_base_cc
20 mvc 0(8,%r1),__LC_LAST_UPDATE_CLOCK
21 larl %r13,.LPG1 # get base
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]22 lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers
23 lg %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area
24 # move IPL device to lowcore
Martin Schwidefskyc742b312008-12-31 15:11:42 +0100[diff] [blame]25 lghi %r0,__LC_PASTE
26 stg %r0,__LC_VDSO_PER_CPU
Heiko Carstense87bfe52006-09-20 15:59:15 +0200[diff] [blame]27#
28# Setup stack
29#
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]30 larl %r15,init_thread_union
Heiko Carstens0c88ee52009-09-11 10:28:58 +0200[diff] [blame]31 stg %r15,__LC_THREAD_INFO # cache thread info in lowcore
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]32 lg %r14,__TI_task(%r15) # cache current in lowcore
33 stg %r14,__LC_CURRENT
34 aghi %r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union + THREAD_SIZE
35 stg %r15,__LC_KERNEL_STACK # set end of kernel stack
36 aghi %r15,-160
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]37#
Hongjie Yangfe355b72007-02-05 21:18:24 +0100[diff] [blame]38# Save ipl parameters, clear bss memory, initialize storage key for kernel pages,
39# and create a kernel NSS if the SAVESYS= parm is defined
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]40#
Hongjie Yangfe355b72007-02-05 21:18:24 +0100[diff] [blame]41 brasl %r14,startup_init
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]42 lpswe .Lentry-.LPG1(13) # jump to _stext in primary-space,
43 # virtual and never return ...
44 .align 16
Martin Schwidefsky1844c9b2010-02-26 22:37:53 +0100[diff] [blame]45.LPG1:
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]46.Lentry:.quad 0x0000000180000000,_stext
Martin Schwidefskyc76e70d2011-07-24 10:48:29 +0200[diff] [blame]47.Lctl: .quad 0x04040000 # cr0: AFP registers & secondary space
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]48 .quad 0 # cr1: primary space segment table
49 .quad .Lduct # cr2: dispatchable unit control table
50 .quad 0 # cr3: instruction authorization
51 .quad 0 # cr4: instruction authorization
Gerald Schaefer482b05d2007-03-05 23:35:54 +0100[diff] [blame]52 .quad .Lduct # cr5: primary-aste origin
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]53 .quad 0 # cr6: I/O interrupts
54 .quad 0 # cr7: secondary space segment table
55 .quad 0 # cr8: access registers translation
56 .quad 0 # cr9: tracing off
57 .quad 0 # cr10: tracing off
58 .quad 0 # cr11: tracing off
59 .quad 0 # cr12: tracing off
60 .quad 0 # cr13: home space segment table
61 .quad 0xc0000000 # cr14: machine check handling off
62 .quad 0 # cr15: linkage stack operations
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]63.Lpcmsk:.quad 0x0000000180000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]64.L4malign:.quad 0xffffffffffc00000
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]65.Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8
66.Lnop: .long 0x07000700
Heiko Carstensb1b70302006-06-29 14:58:17 +0200[diff] [blame]67.Lparmaddr:
68 .quad PARMAREA
Gerald Schaefer482b05d2007-03-05 23:35:54 +0100[diff] [blame]69 .align 64
70.Lduct: .long 0,0,0,0,.Lduald,0,0,0
71 .long 0,0,0,0,0,0,0,0
72 .align 128
73.Lduald:.rept 8
74 .long 0x80000000,0,0,0 # invalid access-list entries
75 .endr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]76
Jan Glauber144d6342011-07-24 10:48:19 +0200[diff] [blame]77ENTRY(_ehead)
Martin Schwidefsky1844c9b2010-02-26 22:37:53 +0100[diff] [blame]78
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]79#ifdef CONFIG_SHARED_KERNEL
Martin Schwidefsky57d84902010-05-12 09:32:13 +0200[diff] [blame]80 .org 0x100000 - 0x11000 # head.o ends at 0x11000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]81#endif
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]82
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]83#
Heiko Carstensb1b70302006-06-29 14:58:17 +0200[diff] [blame]84# startup-code, running in absolute addressing mode
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]85#
Jan Glauber144d6342011-07-24 10:48:19 +0200[diff] [blame]86ENTRY(_stext)
87 basr %r13,0 # get base
Heiko Carstens1e8e3382005-10-30 15:00:11 -0800[diff] [blame]88.LPG3:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]89# check control registers
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]90 stctg %c0,%c15,0(%r15)
Martin Schwidefskyd98e19c2011-10-30 15:16:58 +0100[diff] [blame]91 oi 6(%r15),0x60 # enable sigp emergency & external call
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]92 oi 4(%r15),0x10 # switch on low address proctection
93 lctlg %c0,%c15,0(%r15)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]94
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]95 lam 0,15,.Laregs-.LPG3(%r13) # load acrs needed by uaccess
96 brasl %r14,start_kernel # go to C code
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]97#
98# We returned from start_kernel ?!? PANIK
99#
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]100 basr %r13,0
101 lpswe .Ldw-.(%r13) # load disabled wait psw
Heiko Carstense87bfe52006-09-20 15:59:15 +0200[diff] [blame]102
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]103 .align 8
104.Ldw: .quad 0x0002000180000000,0x0000000000000000
105.Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0