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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * arch/ia64/kernel/ivt.S
3 *
David Mosberger-Tang060561f2005-04-27 21:17:03 -07004 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger <davidm@hpl.hp.com>
7 * Copyright (C) 2000, 2002-2003 Intel Co
8 * Asit Mallick <asit.k.mallick@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Kenneth Chen <kenneth.w.chen@intel.com>
11 * Fenghua Yu <fenghua.yu@intel.com>
12 *
13 * 00/08/23 Asit Mallick <asit.k.mallick@intel.com> TLB handling for SMP
14 * 00/12/20 David Mosberger-Tang <davidm@hpl.hp.com> DTLB/ITLB handler now uses virtual PT.
15 */
16/*
17 * This file defines the interruption vector table used by the CPU.
18 * It does not include one entry per possible cause of interruption.
19 *
20 * The first 20 entries of the table contain 64 bundles each while the
21 * remaining 48 entries contain only 16 bundles each.
22 *
23 * The 64 bundles are used to allow inlining the whole handler for critical
24 * interruptions like TLB misses.
25 *
26 * For each entry, the comment is as follows:
27 *
28 * // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
29 * entry offset ----/ / / / /
30 * entry number ---------/ / / /
31 * size of the entry -------------/ / /
32 * vector name -------------------------------------/ /
33 * interruptions triggering this vector ----------------------/
34 *
35 * The table is 32KB in size and must be aligned on 32KB boundary.
36 * (The CPU ignores the 15 lower bits of the address)
37 *
38 * Table is based upon EAS2.6 (Oct 1999)
39 */
40
41#include <linux/config.h>
42
43#include <asm/asmmacro.h>
44#include <asm/break.h>
45#include <asm/ia32.h>
46#include <asm/kregs.h>
Sam Ravnborg39e01cb2005-09-09 22:03:13 +020047#include <asm/asm-offsets.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048#include <asm/pgtable.h>
49#include <asm/processor.h>
50#include <asm/ptrace.h>
51#include <asm/system.h>
52#include <asm/thread_info.h>
53#include <asm/unistd.h>
54#include <asm/errno.h>
55
56#if 1
57# define PSR_DEFAULT_BITS psr.ac
58#else
59# define PSR_DEFAULT_BITS 0
60#endif
61
62#if 0
63 /*
64 * This lets you track the last eight faults that occurred on the CPU. Make sure ar.k2 isn't
65 * needed for something else before enabling this...
66 */
67# define DBG_FAULT(i) mov r16=ar.k2;; shl r16=r16,8;; add r16=(i),r16;;mov ar.k2=r16
68#else
69# define DBG_FAULT(i)
70#endif
71
Linus Torvalds1da177e2005-04-16 15:20:36 -070072#include "minstate.h"
73
74#define FAULT(n) \
75 mov r31=pr; \
76 mov r19=n;; /* prepare to save predicates */ \
77 br.sptk.many dispatch_to_fault_handler
78
79 .section .text.ivt,"ax"
80
81 .align 32768 // align on 32KB boundary
82 .global ia64_ivt
83ia64_ivt:
84/////////////////////////////////////////////////////////////////////////////////////////
85// 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47)
86ENTRY(vhpt_miss)
87 DBG_FAULT(0)
88 /*
89 * The VHPT vector is invoked when the TLB entry for the virtual page table
90 * is missing. This happens only as a result of a previous
91 * (the "original") TLB miss, which may either be caused by an instruction
92 * fetch or a data access (or non-access).
93 *
Chen, Kenneth We8aabc42005-11-17 01:55:34 -080094 * What we do here is normal TLB miss handing for the _original_ miss,
95 * followed by inserting the TLB entry for the virtual page table page
96 * that the VHPT walker was attempting to access. The latter gets
97 * inserted as long as page table entry above pte level have valid
98 * mappings for the faulting address. The TLB entry for the original
99 * miss gets inserted only if the pte entry indicates that the page is
100 * present.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101 *
102 * do_page_fault gets invoked in the following cases:
103 * - the faulting virtual address uses unimplemented address bits
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800104 * - the faulting virtual address has no valid page table mapping
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105 */
106 mov r16=cr.ifa // get address that caused the TLB miss
107#ifdef CONFIG_HUGETLB_PAGE
108 movl r18=PAGE_SHIFT
109 mov r25=cr.itir
110#endif
111 ;;
112 rsm psr.dt // use physical addressing for data
113 mov r31=pr // save the predicate registers
114 mov r19=IA64_KR(PT_BASE) // get page table base address
115 shl r21=r16,3 // shift bit 60 into sign bit
116 shr.u r17=r16,61 // get the region number into r17
117 ;;
Robin Holt837cd0b2005-11-11 09:35:43 -0600118 shr.u r22=r21,3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119#ifdef CONFIG_HUGETLB_PAGE
120 extr.u r26=r25,2,6
121 ;;
122 cmp.ne p8,p0=r18,r26
123 sub r27=r26,r18
124 ;;
125(p8) dep r25=r18,r25,2,6
126(p8) shr r22=r22,r27
127#endif
128 ;;
129 cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5?
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800130 shr.u r18=r22,PGDIR_SHIFT // get bottom portion of pgd index bit
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131 ;;
132(p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
133
134 srlz.d
135 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
136
137 .pred.rel "mutex", p6, p7
138(p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
139(p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
140 ;;
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800141(p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
142(p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
Robin Holt837cd0b2005-11-11 09:35:43 -0600144#ifdef CONFIG_PGTABLE_4
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800145 shr.u r28=r22,PUD_SHIFT // shift pud index into position
Robin Holt837cd0b2005-11-11 09:35:43 -0600146#else
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800147 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
Robin Holt837cd0b2005-11-11 09:35:43 -0600148#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149 ;;
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800150 ld8 r17=[r17] // get *pgd (may be 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151 ;;
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800152(p7) cmp.eq p6,p7=r17,r0 // was pgd_present(*pgd) == NULL?
Robin Holt837cd0b2005-11-11 09:35:43 -0600153#ifdef CONFIG_PGTABLE_4
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800154 dep r28=r28,r17,3,(PAGE_SHIFT-3) // r28=pud_offset(pgd,addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700155 ;;
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800156 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
157(p7) ld8 r29=[r28] // get *pud (may be 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158 ;;
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800159(p7) cmp.eq.or.andcm p6,p7=r29,r0 // was pud_present(*pud) == NULL?
160 dep r17=r18,r29,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
Robin Holt837cd0b2005-11-11 09:35:43 -0600161#else
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800162 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pgd,addr)
Robin Holt837cd0b2005-11-11 09:35:43 -0600163#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164 ;;
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800165(p7) ld8 r20=[r17] // get *pmd (may be 0)
166 shr.u r19=r22,PAGE_SHIFT // shift pte index into position
Robin Holt837cd0b2005-11-11 09:35:43 -0600167 ;;
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800168(p7) cmp.eq.or.andcm p6,p7=r20,r0 // was pmd_present(*pmd) == NULL?
169 dep r21=r19,r20,3,(PAGE_SHIFT-3) // r21=pte_offset(pmd,addr)
Robin Holt837cd0b2005-11-11 09:35:43 -0600170 ;;
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800171(p7) ld8 r18=[r21] // read *pte
172 mov r19=cr.isr // cr.isr bit 32 tells us if this is an insn miss
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173 ;;
174(p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared?
175 mov r22=cr.iha // get the VHPT address that caused the TLB miss
176 ;; // avoid RAW on p7
177(p7) tbit.nz.unc p10,p11=r19,32 // is it an instruction TLB miss?
178 dep r23=0,r20,0,PAGE_SHIFT // clear low bits to get page address
179 ;;
180(p10) itc.i r18 // insert the instruction TLB entry
181(p11) itc.d r18 // insert the data TLB entry
182(p6) br.cond.spnt.many page_fault // handle bad address/page not present (page fault)
183 mov cr.ifa=r22
184
185#ifdef CONFIG_HUGETLB_PAGE
186(p8) mov cr.itir=r25 // change to default page-size for VHPT
187#endif
188
189 /*
190 * Now compute and insert the TLB entry for the virtual page table. We never
191 * execute in a page table page so there is no need to set the exception deferral
192 * bit.
193 */
194 adds r24=__DIRTY_BITS_NO_ED|_PAGE_PL_0|_PAGE_AR_RW,r23
195 ;;
196(p7) itc.d r24
197 ;;
198#ifdef CONFIG_SMP
199 /*
200 * Tell the assemblers dependency-violation checker that the above "itc" instructions
201 * cannot possibly affect the following loads:
202 */
203 dv_serialize_data
204
205 /*
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800206 * Re-check pagetable entry. If they changed, we may have received a ptc.g
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207 * between reading the pagetable and the "itc". If so, flush the entry we
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800208 * inserted and retry. At this point, we have:
209 *
210 * r28 = equivalent of pud_offset(pgd, ifa)
211 * r17 = equivalent of pmd_offset(pud, ifa)
212 * r21 = equivalent of pte_offset(pmd, ifa)
213 *
214 * r29 = *pud
215 * r20 = *pmd
216 * r18 = *pte
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217 */
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800218 ld8 r25=[r21] // read *pte again
219 ld8 r26=[r17] // read *pmd again
Robin Holt837cd0b2005-11-11 09:35:43 -0600220#ifdef CONFIG_PGTABLE_4
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800221 ld8 r19=[r28] // read *pud again
Robin Holt837cd0b2005-11-11 09:35:43 -0600222#endif
223 cmp.ne p6,p7=r0,r0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224 ;;
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800225 cmp.ne.or.andcm p6,p7=r26,r20 // did *pmd change
Robin Holt837cd0b2005-11-11 09:35:43 -0600226#ifdef CONFIG_PGTABLE_4
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800227 cmp.ne.or.andcm p6,p7=r19,r29 // did *pud change
Robin Holt837cd0b2005-11-11 09:35:43 -0600228#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229 mov r27=PAGE_SHIFT<<2
230 ;;
231(p6) ptc.l r22,r27 // purge PTE page translation
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800232(p7) cmp.ne.or.andcm p6,p7=r25,r18 // did *pte change
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233 ;;
234(p6) ptc.l r16,r27 // purge translation
235#endif
236
237 mov pr=r31,-1 // restore predicate registers
238 rfi
239END(vhpt_miss)
240
241 .org ia64_ivt+0x400
242/////////////////////////////////////////////////////////////////////////////////////////
243// 0x0400 Entry 1 (size 64 bundles) ITLB (21)
244ENTRY(itlb_miss)
245 DBG_FAULT(1)
246 /*
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800247 * The ITLB handler accesses the PTE via the virtually mapped linear
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248 * page table. If a nested TLB miss occurs, we switch into physical
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800249 * mode, walk the page table, and then re-execute the PTE read and
250 * go on normally after that.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251 */
252 mov r16=cr.ifa // get virtual address
253 mov r29=b0 // save b0
254 mov r31=pr // save predicates
255.itlb_fault:
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800256 mov r17=cr.iha // get virtual address of PTE
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257 movl r30=1f // load nested fault continuation point
258 ;;
Chen, Kenneth We8aabc42005-11-17 01:55:34 -08002591: ld8 r18=[r17] // read *pte
Linus Torvalds1da177e2005-04-16 15:20:36 -0700260 ;;
261 mov b0=r29
262 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
263(p6) br.cond.spnt page_fault
264 ;;
265 itc.i r18
266 ;;
267#ifdef CONFIG_SMP
268 /*
269 * Tell the assemblers dependency-violation checker that the above "itc" instructions
270 * cannot possibly affect the following loads:
271 */
272 dv_serialize_data
273
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800274 ld8 r19=[r17] // read *pte again and see if same
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275 mov r20=PAGE_SHIFT<<2 // setup page size for purge
276 ;;
277 cmp.ne p7,p0=r18,r19
278 ;;
279(p7) ptc.l r16,r20
280#endif
281 mov pr=r31,-1
282 rfi
283END(itlb_miss)
284
285 .org ia64_ivt+0x0800
286/////////////////////////////////////////////////////////////////////////////////////////
287// 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
288ENTRY(dtlb_miss)
289 DBG_FAULT(2)
290 /*
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800291 * The DTLB handler accesses the PTE via the virtually mapped linear
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292 * page table. If a nested TLB miss occurs, we switch into physical
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800293 * mode, walk the page table, and then re-execute the PTE read and
294 * go on normally after that.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700295 */
296 mov r16=cr.ifa // get virtual address
297 mov r29=b0 // save b0
298 mov r31=pr // save predicates
299dtlb_fault:
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800300 mov r17=cr.iha // get virtual address of PTE
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301 movl r30=1f // load nested fault continuation point
302 ;;
Chen, Kenneth We8aabc42005-11-17 01:55:34 -08003031: ld8 r18=[r17] // read *pte
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304 ;;
305 mov b0=r29
306 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
307(p6) br.cond.spnt page_fault
308 ;;
309 itc.d r18
310 ;;
311#ifdef CONFIG_SMP
312 /*
313 * Tell the assemblers dependency-violation checker that the above "itc" instructions
314 * cannot possibly affect the following loads:
315 */
316 dv_serialize_data
317
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800318 ld8 r19=[r17] // read *pte again and see if same
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319 mov r20=PAGE_SHIFT<<2 // setup page size for purge
320 ;;
321 cmp.ne p7,p0=r18,r19
322 ;;
323(p7) ptc.l r16,r20
324#endif
325 mov pr=r31,-1
326 rfi
327END(dtlb_miss)
328
329 .org ia64_ivt+0x0c00
330/////////////////////////////////////////////////////////////////////////////////////////
331// 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
332ENTRY(alt_itlb_miss)
333 DBG_FAULT(3)
334 mov r16=cr.ifa // get address that caused the TLB miss
335 movl r17=PAGE_KERNEL
336 mov r21=cr.ipsr
337 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
338 mov r31=pr
339 ;;
340#ifdef CONFIG_DISABLE_VHPT
341 shr.u r22=r16,61 // get the region number into r21
342 ;;
343 cmp.gt p8,p0=6,r22 // user mode
344 ;;
345(p8) thash r17=r16
346 ;;
347(p8) mov cr.iha=r17
348(p8) mov r29=b0 // save b0
349(p8) br.cond.dptk .itlb_fault
350#endif
351 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
352 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
353 shr.u r18=r16,57 // move address bit 61 to bit 4
354 ;;
355 andcm r18=0x10,r18 // bit 4=~address-bit(61)
356 cmp.ne p8,p0=r0,r23 // psr.cpl != 0?
357 or r19=r17,r19 // insert PTE control bits into r19
358 ;;
359 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
360(p8) br.cond.spnt page_fault
361 ;;
362 itc.i r19 // insert the TLB entry
363 mov pr=r31,-1
364 rfi
365END(alt_itlb_miss)
366
367 .org ia64_ivt+0x1000
368/////////////////////////////////////////////////////////////////////////////////////////
369// 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
370ENTRY(alt_dtlb_miss)
371 DBG_FAULT(4)
372 mov r16=cr.ifa // get address that caused the TLB miss
373 movl r17=PAGE_KERNEL
374 mov r20=cr.isr
375 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
376 mov r21=cr.ipsr
377 mov r31=pr
378 ;;
379#ifdef CONFIG_DISABLE_VHPT
380 shr.u r22=r16,61 // get the region number into r21
381 ;;
382 cmp.gt p8,p0=6,r22 // access to region 0-5
383 ;;
384(p8) thash r17=r16
385 ;;
386(p8) mov cr.iha=r17
387(p8) mov r29=b0 // save b0
388(p8) br.cond.dptk dtlb_fault
389#endif
390 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
391 and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field
392 tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on?
393 shr.u r18=r16,57 // move address bit 61 to bit 4
394 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
395 tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on?
396 ;;
397 andcm r18=0x10,r18 // bit 4=~address-bit(61)
398 cmp.ne p8,p0=r0,r23
399(p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field
400(p8) br.cond.spnt page_fault
401
402 dep r21=-1,r21,IA64_PSR_ED_BIT,1
403 or r19=r19,r17 // insert PTE control bits into r19
404 ;;
405 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
406(p6) mov cr.ipsr=r21
407 ;;
408(p7) itc.d r19 // insert the TLB entry
409 mov pr=r31,-1
410 rfi
411END(alt_dtlb_miss)
412
413 .org ia64_ivt+0x1400
414/////////////////////////////////////////////////////////////////////////////////////////
415// 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45)
416ENTRY(nested_dtlb_miss)
417 /*
418 * In the absence of kernel bugs, we get here when the virtually mapped linear
419 * page table is accessed non-speculatively (e.g., in the Dirty-bit, Instruction
420 * Access-bit, or Data Access-bit faults). If the DTLB entry for the virtual page
421 * table is missing, a nested TLB miss fault is triggered and control is
422 * transferred to this point. When this happens, we lookup the pte for the
423 * faulting address by walking the page table in physical mode and return to the
424 * continuation point passed in register r30 (or call page_fault if the address is
425 * not mapped).
426 *
427 * Input: r16: faulting address
428 * r29: saved b0
429 * r30: continuation address
430 * r31: saved pr
431 *
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800432 * Output: r17: physical address of PTE of faulting address
Linus Torvalds1da177e2005-04-16 15:20:36 -0700433 * r29: saved b0
434 * r30: continuation address
435 * r31: saved pr
436 *
Ken Chen0393eed2005-06-21 14:40:31 -0700437 * Clobbered: b0, r18, r19, r21, r22, psr.dt (cleared)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438 */
439 rsm psr.dt // switch to using physical data addressing
440 mov r19=IA64_KR(PT_BASE) // get the page table base address
441 shl r21=r16,3 // shift bit 60 into sign bit
Ken Chen0393eed2005-06-21 14:40:31 -0700442 mov r18=cr.itir
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443 ;;
444 shr.u r17=r16,61 // get the region number into r17
Ken Chen0393eed2005-06-21 14:40:31 -0700445 extr.u r18=r18,2,6 // get the faulting page size
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446 ;;
447 cmp.eq p6,p7=5,r17 // is faulting address in region 5?
Ken Chen0393eed2005-06-21 14:40:31 -0700448 add r22=-PAGE_SHIFT,r18 // adjustment for hugetlb address
449 add r18=PGDIR_SHIFT-PAGE_SHIFT,r18
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450 ;;
Ken Chen0393eed2005-06-21 14:40:31 -0700451 shr.u r22=r16,r22
452 shr.u r18=r16,r18
Linus Torvalds1da177e2005-04-16 15:20:36 -0700453(p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
454
455 srlz.d
456 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
457
458 .pred.rel "mutex", p6, p7
459(p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
460(p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
461 ;;
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800462(p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
463(p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
Robin Holt837cd0b2005-11-11 09:35:43 -0600465#ifdef CONFIG_PGTABLE_4
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800466 shr.u r18=r22,PUD_SHIFT // shift pud index into position
Robin Holt837cd0b2005-11-11 09:35:43 -0600467#else
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800468 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
Robin Holt837cd0b2005-11-11 09:35:43 -0600469#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700470 ;;
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800471 ld8 r17=[r17] // get *pgd (may be 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700472 ;;
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800473(p7) cmp.eq p6,p7=r17,r0 // was pgd_present(*pgd) == NULL?
474 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=p[u|m]d_offset(pgd,addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700475 ;;
Robin Holt837cd0b2005-11-11 09:35:43 -0600476#ifdef CONFIG_PGTABLE_4
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800477(p7) ld8 r17=[r17] // get *pud (may be 0)
478 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
Linus Torvalds1da177e2005-04-16 15:20:36 -0700479 ;;
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800480(p7) cmp.eq.or.andcm p6,p7=r17,r0 // was pud_present(*pud) == NULL?
481 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
Robin Holt837cd0b2005-11-11 09:35:43 -0600482 ;;
483#endif
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800484(p7) ld8 r17=[r17] // get *pmd (may be 0)
485 shr.u r19=r22,PAGE_SHIFT // shift pte index into position
Robin Holt837cd0b2005-11-11 09:35:43 -0600486 ;;
Chen, Kenneth We8aabc42005-11-17 01:55:34 -0800487(p7) cmp.eq.or.andcm p6,p7=r17,r0 // was pmd_present(*pmd) == NULL?
488 dep r17=r19,r17,3,(PAGE_SHIFT-3) // r17=pte_offset(pmd,addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489(p6) br.cond.spnt page_fault
490 mov b0=r30
491 br.sptk.many b0 // return to continuation point
492END(nested_dtlb_miss)
493
494 .org ia64_ivt+0x1800
495/////////////////////////////////////////////////////////////////////////////////////////
496// 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
497ENTRY(ikey_miss)
498 DBG_FAULT(6)
499 FAULT(6)
500END(ikey_miss)
501
502 //-----------------------------------------------------------------------------------
503 // call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address)
504ENTRY(page_fault)
505 ssm psr.dt
506 ;;
507 srlz.i
508 ;;
509 SAVE_MIN_WITH_COVER
510 alloc r15=ar.pfs,0,0,3,0
511 mov out0=cr.ifa
512 mov out1=cr.isr
513 adds r3=8,r2 // set up second base pointer
514 ;;
515 ssm psr.ic | PSR_DEFAULT_BITS
516 ;;
517 srlz.i // guarantee that interruption collectin is on
518 ;;
519(p15) ssm psr.i // restore psr.i
520 movl r14=ia64_leave_kernel
521 ;;
522 SAVE_REST
523 mov rp=r14
524 ;;
525 adds out2=16,r12 // out2 = pointer to pt_regs
526 br.call.sptk.many b6=ia64_do_page_fault // ignore return address
527END(page_fault)
528
529 .org ia64_ivt+0x1c00
530/////////////////////////////////////////////////////////////////////////////////////////
531// 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
532ENTRY(dkey_miss)
533 DBG_FAULT(7)
534 FAULT(7)
535END(dkey_miss)
536
537 .org ia64_ivt+0x2000
538/////////////////////////////////////////////////////////////////////////////////////////
539// 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
540ENTRY(dirty_bit)
541 DBG_FAULT(8)
542 /*
543 * What we do here is to simply turn on the dirty bit in the PTE. We need to
544 * update both the page-table and the TLB entry. To efficiently access the PTE,
545 * we address it through the virtual page table. Most likely, the TLB entry for
546 * the relevant virtual page table page is still present in the TLB so we can
547 * normally do this without additional TLB misses. In case the necessary virtual
548 * page table TLB entry isn't present, we take a nested TLB miss hit where we look
549 * up the physical address of the L3 PTE and then continue at label 1 below.
550 */
551 mov r16=cr.ifa // get the address that caused the fault
552 movl r30=1f // load continuation point in case of nested fault
553 ;;
554 thash r17=r16 // compute virtual address of L3 PTE
555 mov r29=b0 // save b0 in case of nested fault
556 mov r31=pr // save pr
557#ifdef CONFIG_SMP
558 mov r28=ar.ccv // save ar.ccv
559 ;;
5601: ld8 r18=[r17]
561 ;; // avoid RAW on r18
562 mov ar.ccv=r18 // set compare value for cmpxchg
563 or r25=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
Christoph Lameterd8117ce2006-03-07 19:05:32 -0800564 tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565 ;;
Christoph Lameterd8117ce2006-03-07 19:05:32 -0800566(p6) cmpxchg8.acq r26=[r17],r25,ar.ccv // Only update if page is present
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567 mov r24=PAGE_SHIFT<<2
568 ;;
Christoph Lameterd8117ce2006-03-07 19:05:32 -0800569(p6) cmp.eq p6,p7=r26,r18 // Only compare if page is present
Linus Torvalds1da177e2005-04-16 15:20:36 -0700570 ;;
571(p6) itc.d r25 // install updated PTE
572 ;;
573 /*
574 * Tell the assemblers dependency-violation checker that the above "itc" instructions
575 * cannot possibly affect the following loads:
576 */
577 dv_serialize_data
578
579 ld8 r18=[r17] // read PTE again
580 ;;
581 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
582 ;;
583(p7) ptc.l r16,r24
584 mov b0=r29 // restore b0
585 mov ar.ccv=r28
586#else
587 ;;
5881: ld8 r18=[r17]
589 ;; // avoid RAW on r18
590 or r18=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
591 mov b0=r29 // restore b0
592 ;;
593 st8 [r17]=r18 // store back updated PTE
594 itc.d r18 // install updated PTE
595#endif
596 mov pr=r31,-1 // restore pr
597 rfi
598END(dirty_bit)
599
600 .org ia64_ivt+0x2400
601/////////////////////////////////////////////////////////////////////////////////////////
602// 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
603ENTRY(iaccess_bit)
604 DBG_FAULT(9)
605 // Like Entry 8, except for instruction access
606 mov r16=cr.ifa // get the address that caused the fault
607 movl r30=1f // load continuation point in case of nested fault
608 mov r31=pr // save predicates
609#ifdef CONFIG_ITANIUM
610 /*
611 * Erratum 10 (IFA may contain incorrect address) has "NoFix" status.
612 */
613 mov r17=cr.ipsr
614 ;;
615 mov r18=cr.iip
616 tbit.z p6,p0=r17,IA64_PSR_IS_BIT // IA64 instruction set?
617 ;;
618(p6) mov r16=r18 // if so, use cr.iip instead of cr.ifa
619#endif /* CONFIG_ITANIUM */
620 ;;
621 thash r17=r16 // compute virtual address of L3 PTE
622 mov r29=b0 // save b0 in case of nested fault)
623#ifdef CONFIG_SMP
624 mov r28=ar.ccv // save ar.ccv
625 ;;
6261: ld8 r18=[r17]
627 ;;
628 mov ar.ccv=r18 // set compare value for cmpxchg
629 or r25=_PAGE_A,r18 // set the accessed bit
Christoph Lameterd8117ce2006-03-07 19:05:32 -0800630 tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit
Linus Torvalds1da177e2005-04-16 15:20:36 -0700631 ;;
Christoph Lameterd8117ce2006-03-07 19:05:32 -0800632(p6) cmpxchg8.acq r26=[r17],r25,ar.ccv // Only if page present
Linus Torvalds1da177e2005-04-16 15:20:36 -0700633 mov r24=PAGE_SHIFT<<2
634 ;;
Christoph Lameterd8117ce2006-03-07 19:05:32 -0800635(p6) cmp.eq p6,p7=r26,r18 // Only if page present
Linus Torvalds1da177e2005-04-16 15:20:36 -0700636 ;;
637(p6) itc.i r25 // install updated PTE
638 ;;
639 /*
640 * Tell the assemblers dependency-violation checker that the above "itc" instructions
641 * cannot possibly affect the following loads:
642 */
643 dv_serialize_data
644
645 ld8 r18=[r17] // read PTE again
646 ;;
647 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
648 ;;
649(p7) ptc.l r16,r24
650 mov b0=r29 // restore b0
651 mov ar.ccv=r28
652#else /* !CONFIG_SMP */
653 ;;
6541: ld8 r18=[r17]
655 ;;
656 or r18=_PAGE_A,r18 // set the accessed bit
657 mov b0=r29 // restore b0
658 ;;
659 st8 [r17]=r18 // store back updated PTE
660 itc.i r18 // install updated PTE
661#endif /* !CONFIG_SMP */
662 mov pr=r31,-1
663 rfi
664END(iaccess_bit)
665
666 .org ia64_ivt+0x2800
667/////////////////////////////////////////////////////////////////////////////////////////
668// 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
669ENTRY(daccess_bit)
670 DBG_FAULT(10)
671 // Like Entry 8, except for data access
672 mov r16=cr.ifa // get the address that caused the fault
673 movl r30=1f // load continuation point in case of nested fault
674 ;;
675 thash r17=r16 // compute virtual address of L3 PTE
676 mov r31=pr
677 mov r29=b0 // save b0 in case of nested fault)
678#ifdef CONFIG_SMP
679 mov r28=ar.ccv // save ar.ccv
680 ;;
6811: ld8 r18=[r17]
682 ;; // avoid RAW on r18
683 mov ar.ccv=r18 // set compare value for cmpxchg
684 or r25=_PAGE_A,r18 // set the dirty bit
Christoph Lameterd8117ce2006-03-07 19:05:32 -0800685 tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit
Linus Torvalds1da177e2005-04-16 15:20:36 -0700686 ;;
Christoph Lameterd8117ce2006-03-07 19:05:32 -0800687(p6) cmpxchg8.acq r26=[r17],r25,ar.ccv // Only if page is present
Linus Torvalds1da177e2005-04-16 15:20:36 -0700688 mov r24=PAGE_SHIFT<<2
689 ;;
Christoph Lameterd8117ce2006-03-07 19:05:32 -0800690(p6) cmp.eq p6,p7=r26,r18 // Only if page is present
Linus Torvalds1da177e2005-04-16 15:20:36 -0700691 ;;
692(p6) itc.d r25 // install updated PTE
693 /*
694 * Tell the assemblers dependency-violation checker that the above "itc" instructions
695 * cannot possibly affect the following loads:
696 */
697 dv_serialize_data
698 ;;
699 ld8 r18=[r17] // read PTE again
700 ;;
701 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
702 ;;
703(p7) ptc.l r16,r24
704 mov ar.ccv=r28
705#else
706 ;;
7071: ld8 r18=[r17]
708 ;; // avoid RAW on r18
709 or r18=_PAGE_A,r18 // set the accessed bit
710 ;;
711 st8 [r17]=r18 // store back updated PTE
712 itc.d r18 // install updated PTE
713#endif
714 mov b0=r29 // restore b0
715 mov pr=r31,-1
716 rfi
717END(daccess_bit)
718
719 .org ia64_ivt+0x2c00
720/////////////////////////////////////////////////////////////////////////////////////////
721// 0x2c00 Entry 11 (size 64 bundles) Break instruction (33)
722ENTRY(break_fault)
723 /*
724 * The streamlined system call entry/exit paths only save/restore the initial part
725 * of pt_regs. This implies that the callers of system-calls must adhere to the
726 * normal procedure calling conventions.
727 *
728 * Registers to be saved & restored:
729 * CR registers: cr.ipsr, cr.iip, cr.ifs
730 * AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore, ar.fpsr
731 * others: pr, b0, b6, loadrs, r1, r11, r12, r13, r15
732 * Registers to be restored only:
733 * r8-r11: output value from the system call.
734 *
735 * During system call exit, scratch registers (including r15) are modified/cleared
736 * to prevent leaking bits from kernel to user level.
737 */
738 DBG_FAULT(11)
David Mosberger-Tangf8fa5442005-04-27 21:19:04 -0700739 mov.m r16=IA64_KR(CURRENT) // M2 r16 <- current task (12 cyc)
740 mov r29=cr.ipsr // M2 (12 cyc)
741 mov r31=pr // I0 (2 cyc)
742
743 mov r17=cr.iim // M2 (2 cyc)
744 mov.m r27=ar.rsc // M2 (12 cyc)
745 mov r18=__IA64_BREAK_SYSCALL // A
746
747 mov.m ar.rsc=0 // M2
748 mov.m r21=ar.fpsr // M2 (12 cyc)
749 mov r19=b6 // I0 (2 cyc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700750 ;;
David Mosberger-Tangf8fa5442005-04-27 21:19:04 -0700751 mov.m r23=ar.bspstore // M2 (12 cyc)
752 mov.m r24=ar.rnat // M2 (5 cyc)
753 mov.i r26=ar.pfs // I0 (2 cyc)
754
755 invala // M0|1
756 nop.m 0 // M
757 mov r20=r1 // A save r1
758
759 nop.m 0
760 movl r30=sys_call_table // X
761
762 mov r28=cr.iip // M2 (2 cyc)
763 cmp.eq p0,p7=r18,r17 // I0 is this a system call?
764(p7) br.cond.spnt non_syscall // B no ->
765 //
766 // From this point on, we are definitely on the syscall-path
767 // and we can use (non-banked) scratch registers.
768 //
769///////////////////////////////////////////////////////////////////////
770 mov r1=r16 // A move task-pointer to "addl"-addressable reg
771 mov r2=r16 // A setup r2 for ia64_syscall_setup
772 add r9=TI_FLAGS+IA64_TASK_SIZE,r16 // A r9 = &current_thread_info()->flags
773
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
David Mosberger-Tangf8fa5442005-04-27 21:19:04 -0700775 adds r15=-1024,r15 // A subtract 1024 from syscall number
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776 mov r3=NR_syscalls - 1
777 ;;
David Mosberger-Tangf8fa5442005-04-27 21:19:04 -0700778 ld1.bias r17=[r16] // M0|1 r17 = current->thread.on_ustack flag
779 ld4 r9=[r9] // M0|1 r9 = current_thread_info()->flags
780 extr.u r8=r29,41,2 // I0 extract ei field from cr.ipsr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781
David Mosberger-Tangf8fa5442005-04-27 21:19:04 -0700782 shladd r30=r15,3,r30 // A r30 = sys_call_table + 8*(syscall-1024)
783 addl r22=IA64_RBS_OFFSET,r1 // A compute base of RBS
784 cmp.leu p6,p7=r15,r3 // A syscall number in range?
Linus Torvalds1da177e2005-04-16 15:20:36 -0700785 ;;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786
David Mosberger-Tangf8fa5442005-04-27 21:19:04 -0700787 lfetch.fault.excl.nt1 [r22] // M0|1 prefetch RBS
788(p6) ld8 r30=[r30] // M0|1 load address of syscall entry point
789 tnat.nz.or p7,p0=r15 // I0 is syscall nr a NaT?
790
791 mov.m ar.bspstore=r22 // M2 switch to kernel RBS
792 cmp.eq p8,p9=2,r8 // A isr.ei==2?
Linus Torvalds1da177e2005-04-16 15:20:36 -0700793 ;;
David Mosberger-Tangf8fa5442005-04-27 21:19:04 -0700794
795(p8) mov r8=0 // A clear ei to 0
796(p7) movl r30=sys_ni_syscall // X
797
798(p8) adds r28=16,r28 // A switch cr.iip to next bundle
799(p9) adds r8=1,r8 // A increment ei to next slot
800 nop.i 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801 ;;
David Mosberger-Tangf8fa5442005-04-27 21:19:04 -0700802
803 mov.m r25=ar.unat // M2 (5 cyc)
804 dep r29=r8,r29,41,2 // I0 insert new ei into cr.ipsr
805 adds r15=1024,r15 // A restore original syscall number
806 //
807 // If any of the above loads miss in L1D, we'll stall here until
808 // the data arrives.
809 //
810///////////////////////////////////////////////////////////////////////
811 st1 [r16]=r0 // M2|3 clear current->thread.on_ustack flag
812 mov b6=r30 // I0 setup syscall handler branch reg early
813 cmp.eq pKStk,pUStk=r0,r17 // A were we on kernel stacks already?
814
815 and r9=_TIF_SYSCALL_TRACEAUDIT,r9 // A mask trace or audit
816 mov r18=ar.bsp // M2 (12 cyc)
817(pKStk) br.cond.spnt .break_fixup // B we're already in kernel-mode -- fix up RBS
Linus Torvalds1da177e2005-04-16 15:20:36 -0700818 ;;
David Mosberger-Tangf8fa5442005-04-27 21:19:04 -0700819.back_from_break_fixup:
820(pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1 // A compute base of memory stack
821 cmp.eq p14,p0=r9,r0 // A are syscalls being traced/audited?
822 br.call.sptk.many b7=ia64_syscall_setup // B
8231:
824 mov ar.rsc=0x3 // M2 set eager mode, pl 0, LE, loadrs=0
825 nop 0
826 bsw.1 // B (6 cyc) regs are saved, switch to bank 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700827 ;;
David Mosberger-Tangf8fa5442005-04-27 21:19:04 -0700828
829 ssm psr.ic | PSR_DEFAULT_BITS // M2 now it's safe to re-enable intr.-collection
830 movl r3=ia64_ret_from_syscall // X
831 ;;
832
833 srlz.i // M0 ensure interruption collection is on
834 mov rp=r3 // I0 set the real return addr
835(p10) br.cond.spnt.many ia64_ret_from_syscall // B return if bad call-frame or r15 is a NaT
836
837(p15) ssm psr.i // M2 restore psr.i
838(p14) br.call.sptk.many b6=b6 // B invoke syscall-handker (ignore return addr)
839 br.cond.spnt.many ia64_trace_syscall // B do syscall-tracing thingamagic
Linus Torvalds1da177e2005-04-16 15:20:36 -0700840 // NOT REACHED
David Mosberger-Tangf8fa5442005-04-27 21:19:04 -0700841///////////////////////////////////////////////////////////////////////
842 // On entry, we optimistically assumed that we're coming from user-space.
843 // For the rare cases where a system-call is done from within the kernel,
844 // we fix things up at this point:
845.break_fixup:
846 add r1=-IA64_PT_REGS_SIZE,sp // A allocate space for pt_regs structure
847 mov ar.rnat=r24 // M2 restore kernel's AR.RNAT
848 ;;
849 mov ar.bspstore=r23 // M2 restore kernel's AR.BSPSTORE
850 br.cond.sptk .back_from_break_fixup
Linus Torvalds1da177e2005-04-16 15:20:36 -0700851END(break_fault)
852
853 .org ia64_ivt+0x3000
854/////////////////////////////////////////////////////////////////////////////////////////
855// 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
856ENTRY(interrupt)
857 DBG_FAULT(12)
858 mov r31=pr // prepare to save predicates
859 ;;
860 SAVE_MIN_WITH_COVER // uses r31; defines r2 and r3
861 ssm psr.ic | PSR_DEFAULT_BITS
862 ;;
863 adds r3=8,r2 // set up second base pointer for SAVE_REST
864 srlz.i // ensure everybody knows psr.ic is back on
865 ;;
866 SAVE_REST
867 ;;
Russ Andersond2a28ad2006-03-24 09:49:52 -0800868 MCA_RECOVER_RANGE(interrupt)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869 alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
870 mov out0=cr.ivr // pass cr.ivr as first arg
871 add out1=16,sp // pass pointer to pt_regs as second arg
872 ;;
873 srlz.d // make sure we see the effect of cr.ivr
874 movl r14=ia64_leave_kernel
875 ;;
876 mov rp=r14
877 br.call.sptk.many b6=ia64_handle_irq
878END(interrupt)
879
880 .org ia64_ivt+0x3400
881/////////////////////////////////////////////////////////////////////////////////////////
882// 0x3400 Entry 13 (size 64 bundles) Reserved
883 DBG_FAULT(13)
884 FAULT(13)
885
886 .org ia64_ivt+0x3800
887/////////////////////////////////////////////////////////////////////////////////////////
888// 0x3800 Entry 14 (size 64 bundles) Reserved
889 DBG_FAULT(14)
890 FAULT(14)
891
892 /*
893 * There is no particular reason for this code to be here, other than that
894 * there happens to be space here that would go unused otherwise. If this
895 * fault ever gets "unreserved", simply moved the following code to a more
896 * suitable spot...
897 *
898 * ia64_syscall_setup() is a separate subroutine so that it can
899 * allocate stacked registers so it can safely demine any
900 * potential NaT values from the input registers.
901 *
902 * On entry:
903 * - executing on bank 0 or bank 1 register set (doesn't matter)
904 * - r1: stack pointer
905 * - r2: current task pointer
906 * - r3: preserved
907 * - r11: original contents (saved ar.pfs to be saved)
908 * - r12: original contents (sp to be saved)
909 * - r13: original contents (tp to be saved)
910 * - r15: original contents (syscall # to be saved)
911 * - r18: saved bsp (after switching to kernel stack)
912 * - r19: saved b6
913 * - r20: saved r1 (gp)
914 * - r21: saved ar.fpsr
915 * - r22: kernel's register backing store base (krbs_base)
916 * - r23: saved ar.bspstore
917 * - r24: saved ar.rnat
918 * - r25: saved ar.unat
919 * - r26: saved ar.pfs
920 * - r27: saved ar.rsc
921 * - r28: saved cr.iip
922 * - r29: saved cr.ipsr
923 * - r31: saved pr
924 * - b0: original contents (to be saved)
925 * On exit:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700926 * - p10: TRUE if syscall is invoked with more than 8 out
927 * registers or r15's Nat is true
928 * - r1: kernel's gp
929 * - r3: preserved (same as on entry)
930 * - r8: -EINVAL if p10 is true
931 * - r12: points to kernel stack
932 * - r13: points to current task
David Mosberger-Tangf8fa5442005-04-27 21:19:04 -0700933 * - r14: preserved (same as on entry)
934 * - p13: preserved
Linus Torvalds1da177e2005-04-16 15:20:36 -0700935 * - p15: TRUE if interrupts need to be re-enabled
936 * - ar.fpsr: set to kernel settings
David Mosberger-Tangf8fa5442005-04-27 21:19:04 -0700937 * - b6: preserved (same as on entry)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700938 */
939GLOBAL_ENTRY(ia64_syscall_setup)
940#if PT(B6) != 0
941# error This code assumes that b6 is the first field in pt_regs.
942#endif
943 st8 [r1]=r19 // save b6
944 add r16=PT(CR_IPSR),r1 // initialize first base pointer
945 add r17=PT(R11),r1 // initialize second base pointer
946 ;;
947 alloc r19=ar.pfs,8,0,0,0 // ensure in0-in7 are writable
948 st8 [r16]=r29,PT(AR_PFS)-PT(CR_IPSR) // save cr.ipsr
949 tnat.nz p8,p0=in0
950
951 st8.spill [r17]=r11,PT(CR_IIP)-PT(R11) // save r11
952 tnat.nz p9,p0=in1
953(pKStk) mov r18=r0 // make sure r18 isn't NaT
954 ;;
955
956 st8 [r16]=r26,PT(CR_IFS)-PT(AR_PFS) // save ar.pfs
957 st8 [r17]=r28,PT(AR_UNAT)-PT(CR_IIP) // save cr.iip
958 mov r28=b0 // save b0 (2 cyc)
959 ;;
960
961 st8 [r17]=r25,PT(AR_RSC)-PT(AR_UNAT) // save ar.unat
962 dep r19=0,r19,38,26 // clear all bits but 0..37 [I0]
963(p8) mov in0=-1
964 ;;
965
966 st8 [r16]=r19,PT(AR_RNAT)-PT(CR_IFS) // store ar.pfs.pfm in cr.ifs
967 extr.u r11=r19,7,7 // I0 // get sol of ar.pfs
968 and r8=0x7f,r19 // A // get sof of ar.pfs
969
970 st8 [r17]=r27,PT(AR_BSPSTORE)-PT(AR_RSC)// save ar.rsc
971 tbit.nz p15,p0=r29,IA64_PSR_I_BIT // I0
972(p9) mov in1=-1
973 ;;
974
975(pUStk) sub r18=r18,r22 // r18=RSE.ndirty*8
976 tnat.nz p10,p0=in2
977 add r11=8,r11
978 ;;
979(pKStk) adds r16=PT(PR)-PT(AR_RNAT),r16 // skip over ar_rnat field
980(pKStk) adds r17=PT(B0)-PT(AR_BSPSTORE),r17 // skip over ar_bspstore field
981 tnat.nz p11,p0=in3
982 ;;
983(p10) mov in2=-1
984 tnat.nz p12,p0=in4 // [I0]
985(p11) mov in3=-1
986 ;;
987(pUStk) st8 [r16]=r24,PT(PR)-PT(AR_RNAT) // save ar.rnat
988(pUStk) st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE) // save ar.bspstore
989 shl r18=r18,16 // compute ar.rsc to be used for "loadrs"
990 ;;
991 st8 [r16]=r31,PT(LOADRS)-PT(PR) // save predicates
992 st8 [r17]=r28,PT(R1)-PT(B0) // save b0
993 tnat.nz p13,p0=in5 // [I0]
994 ;;
995 st8 [r16]=r18,PT(R12)-PT(LOADRS) // save ar.rsc value for "loadrs"
996 st8.spill [r17]=r20,PT(R13)-PT(R1) // save original r1
997(p12) mov in4=-1
998 ;;
999
1000.mem.offset 0,0; st8.spill [r16]=r12,PT(AR_FPSR)-PT(R12) // save r12
1001.mem.offset 8,0; st8.spill [r17]=r13,PT(R15)-PT(R13) // save r13
1002(p13) mov in5=-1
1003 ;;
1004 st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr
David Mosberger-Tangf8fa5442005-04-27 21:19:04 -07001005 tnat.nz p13,p0=in6
Linus Torvalds1da177e2005-04-16 15:20:36 -07001006 cmp.lt p10,p9=r11,r8 // frame size can't be more than local+8
1007 ;;
David Mosberger-Tang060561f2005-04-27 21:17:03 -07001008 mov r8=1
Linus Torvalds1da177e2005-04-16 15:20:36 -07001009(p9) tnat.nz p10,p0=r15
1010 adds r12=-16,r1 // switch to kernel memory stack (with 16 bytes of scratch)
1011
1012 st8.spill [r17]=r15 // save r15
1013 tnat.nz p8,p0=in7
1014 nop.i 0
1015
1016 mov r13=r2 // establish `current'
1017 movl r1=__gp // establish kernel global pointer
1018 ;;
David Mosberger-Tang060561f2005-04-27 21:17:03 -07001019 st8 [r16]=r8 // ensure pt_regs.r8 != 0 (see handle_syscall_error)
David Mosberger-Tangf8fa5442005-04-27 21:19:04 -07001020(p13) mov in6=-1
Linus Torvalds1da177e2005-04-16 15:20:36 -07001021(p8) mov in7=-1
Linus Torvalds1da177e2005-04-16 15:20:36 -07001022
1023 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
1024 movl r17=FPSR_DEFAULT
1025 ;;
1026 mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value
1027(p10) mov r8=-EINVAL
1028 br.ret.sptk.many b7
1029END(ia64_syscall_setup)
1030
1031 .org ia64_ivt+0x3c00
1032/////////////////////////////////////////////////////////////////////////////////////////
1033// 0x3c00 Entry 15 (size 64 bundles) Reserved
1034 DBG_FAULT(15)
1035 FAULT(15)
1036
1037 /*
1038 * Squatting in this space ...
1039 *
1040 * This special case dispatcher for illegal operation faults allows preserved
1041 * registers to be modified through a callback function (asm only) that is handed
1042 * back from the fault handler in r8. Up to three arguments can be passed to the
1043 * callback function by returning an aggregate with the callback as its first
1044 * element, followed by the arguments.
1045 */
1046ENTRY(dispatch_illegal_op_fault)
1047 .prologue
1048 .body
1049 SAVE_MIN_WITH_COVER
1050 ssm psr.ic | PSR_DEFAULT_BITS
1051 ;;
1052 srlz.i // guarantee that interruption collection is on
1053 ;;
1054(p15) ssm psr.i // restore psr.i
1055 adds r3=8,r2 // set up second base pointer for SAVE_REST
1056 ;;
1057 alloc r14=ar.pfs,0,0,1,0 // must be first in insn group
1058 mov out0=ar.ec
1059 ;;
1060 SAVE_REST
1061 PT_REGS_UNWIND_INFO(0)
1062 ;;
1063 br.call.sptk.many rp=ia64_illegal_op_fault
1064.ret0: ;;
1065 alloc r14=ar.pfs,0,0,3,0 // must be first in insn group
1066 mov out0=r9
1067 mov out1=r10
1068 mov out2=r11
1069 movl r15=ia64_leave_kernel
1070 ;;
1071 mov rp=r15
1072 mov b6=r8
1073 ;;
1074 cmp.ne p6,p0=0,r8
1075(p6) br.call.dpnt.many b6=b6 // call returns to ia64_leave_kernel
1076 br.sptk.many ia64_leave_kernel
1077END(dispatch_illegal_op_fault)
1078
1079 .org ia64_ivt+0x4000
1080/////////////////////////////////////////////////////////////////////////////////////////
1081// 0x4000 Entry 16 (size 64 bundles) Reserved
1082 DBG_FAULT(16)
1083 FAULT(16)
1084
1085 .org ia64_ivt+0x4400
1086/////////////////////////////////////////////////////////////////////////////////////////
1087// 0x4400 Entry 17 (size 64 bundles) Reserved
1088 DBG_FAULT(17)
1089 FAULT(17)
1090
1091ENTRY(non_syscall)
David Mosberger-Tangf8fa5442005-04-27 21:19:04 -07001092 mov ar.rsc=r27 // restore ar.rsc before SAVE_MIN_WITH_COVER
1093 ;;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001094 SAVE_MIN_WITH_COVER
1095
1096 // There is no particular reason for this code to be here, other than that
1097 // there happens to be space here that would go unused otherwise. If this
1098 // fault ever gets "unreserved", simply moved the following code to a more
1099 // suitable spot...
1100
1101 alloc r14=ar.pfs,0,0,2,0
1102 mov out0=cr.iim
1103 add out1=16,sp
1104 adds r3=8,r2 // set up second base pointer for SAVE_REST
1105
1106 ssm psr.ic | PSR_DEFAULT_BITS
1107 ;;
1108 srlz.i // guarantee that interruption collection is on
1109 ;;
1110(p15) ssm psr.i // restore psr.i
1111 movl r15=ia64_leave_kernel
1112 ;;
1113 SAVE_REST
1114 mov rp=r15
1115 ;;
1116 br.call.sptk.many b6=ia64_bad_break // avoid WAW on CFM and ignore return addr
1117END(non_syscall)
1118
1119 .org ia64_ivt+0x4800
1120/////////////////////////////////////////////////////////////////////////////////////////
1121// 0x4800 Entry 18 (size 64 bundles) Reserved
1122 DBG_FAULT(18)
1123 FAULT(18)
1124
1125 /*
1126 * There is no particular reason for this code to be here, other than that
1127 * there happens to be space here that would go unused otherwise. If this
1128 * fault ever gets "unreserved", simply moved the following code to a more
1129 * suitable spot...
1130 */
1131
1132ENTRY(dispatch_unaligned_handler)
1133 SAVE_MIN_WITH_COVER
1134 ;;
1135 alloc r14=ar.pfs,0,0,2,0 // now it's safe (must be first in insn group!)
1136 mov out0=cr.ifa
1137 adds out1=16,sp
1138
1139 ssm psr.ic | PSR_DEFAULT_BITS
1140 ;;
1141 srlz.i // guarantee that interruption collection is on
1142 ;;
1143(p15) ssm psr.i // restore psr.i
1144 adds r3=8,r2 // set up second base pointer
1145 ;;
1146 SAVE_REST
1147 movl r14=ia64_leave_kernel
1148 ;;
1149 mov rp=r14
1150 br.sptk.many ia64_prepare_handle_unaligned
1151END(dispatch_unaligned_handler)
1152
1153 .org ia64_ivt+0x4c00
1154/////////////////////////////////////////////////////////////////////////////////////////
1155// 0x4c00 Entry 19 (size 64 bundles) Reserved
1156 DBG_FAULT(19)
1157 FAULT(19)
1158
1159 /*
1160 * There is no particular reason for this code to be here, other than that
1161 * there happens to be space here that would go unused otherwise. If this
1162 * fault ever gets "unreserved", simply moved the following code to a more
1163 * suitable spot...
1164 */
1165
1166ENTRY(dispatch_to_fault_handler)
1167 /*
1168 * Input:
1169 * psr.ic: off
1170 * r19: fault vector number (e.g., 24 for General Exception)
1171 * r31: contains saved predicates (pr)
1172 */
1173 SAVE_MIN_WITH_COVER_R19
1174 alloc r14=ar.pfs,0,0,5,0
1175 mov out0=r15
1176 mov out1=cr.isr
1177 mov out2=cr.ifa
1178 mov out3=cr.iim
1179 mov out4=cr.itir
1180 ;;
1181 ssm psr.ic | PSR_DEFAULT_BITS
1182 ;;
1183 srlz.i // guarantee that interruption collection is on
1184 ;;
1185(p15) ssm psr.i // restore psr.i
1186 adds r3=8,r2 // set up second base pointer for SAVE_REST
1187 ;;
1188 SAVE_REST
1189 movl r14=ia64_leave_kernel
1190 ;;
1191 mov rp=r14
1192 br.call.sptk.many b6=ia64_fault
1193END(dispatch_to_fault_handler)
1194
1195//
1196// --- End of long entries, Beginning of short entries
1197//
1198
1199 .org ia64_ivt+0x5000
1200/////////////////////////////////////////////////////////////////////////////////////////
1201// 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49)
1202ENTRY(page_not_present)
1203 DBG_FAULT(20)
1204 mov r16=cr.ifa
1205 rsm psr.dt
1206 /*
1207 * The Linux page fault handler doesn't expect non-present pages to be in
1208 * the TLB. Flush the existing entry now, so we meet that expectation.
1209 */
1210 mov r17=PAGE_SHIFT<<2
1211 ;;
1212 ptc.l r16,r17
1213 ;;
1214 mov r31=pr
1215 srlz.d
1216 br.sptk.many page_fault
1217END(page_not_present)
1218
1219 .org ia64_ivt+0x5100
1220/////////////////////////////////////////////////////////////////////////////////////////
1221// 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52)
1222ENTRY(key_permission)
1223 DBG_FAULT(21)
1224 mov r16=cr.ifa
1225 rsm psr.dt
1226 mov r31=pr
1227 ;;
1228 srlz.d
1229 br.sptk.many page_fault
1230END(key_permission)
1231
1232 .org ia64_ivt+0x5200
1233/////////////////////////////////////////////////////////////////////////////////////////
1234// 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
1235ENTRY(iaccess_rights)
1236 DBG_FAULT(22)
1237 mov r16=cr.ifa
1238 rsm psr.dt
1239 mov r31=pr
1240 ;;
1241 srlz.d
1242 br.sptk.many page_fault
1243END(iaccess_rights)
1244
1245 .org ia64_ivt+0x5300
1246/////////////////////////////////////////////////////////////////////////////////////////
1247// 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
1248ENTRY(daccess_rights)
1249 DBG_FAULT(23)
1250 mov r16=cr.ifa
1251 rsm psr.dt
1252 mov r31=pr
1253 ;;
1254 srlz.d
1255 br.sptk.many page_fault
1256END(daccess_rights)
1257
1258 .org ia64_ivt+0x5400
1259/////////////////////////////////////////////////////////////////////////////////////////
1260// 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39)
1261ENTRY(general_exception)
1262 DBG_FAULT(24)
1263 mov r16=cr.isr
1264 mov r31=pr
1265 ;;
1266 cmp4.eq p6,p0=0,r16
1267(p6) br.sptk.many dispatch_illegal_op_fault
1268 ;;
1269 mov r19=24 // fault number
1270 br.sptk.many dispatch_to_fault_handler
1271END(general_exception)
1272
1273 .org ia64_ivt+0x5500
1274/////////////////////////////////////////////////////////////////////////////////////////
1275// 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
1276ENTRY(disabled_fp_reg)
1277 DBG_FAULT(25)
1278 rsm psr.dfh // ensure we can access fph
1279 ;;
1280 srlz.d
1281 mov r31=pr
1282 mov r19=25
1283 br.sptk.many dispatch_to_fault_handler
1284END(disabled_fp_reg)
1285
1286 .org ia64_ivt+0x5600
1287/////////////////////////////////////////////////////////////////////////////////////////
1288// 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
1289ENTRY(nat_consumption)
1290 DBG_FAULT(26)
David Mosberger-Tang458f9352005-05-04 13:25:00 -07001291
1292 mov r16=cr.ipsr
1293 mov r17=cr.isr
1294 mov r31=pr // save PR
1295 ;;
1296 and r18=0xf,r17 // r18 = cr.ipsr.code{3:0}
1297 tbit.z p6,p0=r17,IA64_ISR_NA_BIT
1298 ;;
1299 cmp.ne.or p6,p0=IA64_ISR_CODE_LFETCH,r18
1300 dep r16=-1,r16,IA64_PSR_ED_BIT,1
1301(p6) br.cond.spnt 1f // branch if (cr.ispr.na == 0 || cr.ipsr.code{3:0} != LFETCH)
1302 ;;
1303 mov cr.ipsr=r16 // set cr.ipsr.na
1304 mov pr=r31,-1
1305 ;;
1306 rfi
1307
13081: mov pr=r31,-1
1309 ;;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001310 FAULT(26)
1311END(nat_consumption)
1312
1313 .org ia64_ivt+0x5700
1314/////////////////////////////////////////////////////////////////////////////////////////
1315// 0x5700 Entry 27 (size 16 bundles) Speculation (40)
1316ENTRY(speculation_vector)
1317 DBG_FAULT(27)
1318 /*
1319 * A [f]chk.[as] instruction needs to take the branch to the recovery code but
1320 * this part of the architecture is not implemented in hardware on some CPUs, such
1321 * as Itanium. Thus, in general we need to emulate the behavior. IIM contains
1322 * the relative target (not yet sign extended). So after sign extending it we
1323 * simply add it to IIP. We also need to reset the EI field of the IPSR to zero,
1324 * i.e., the slot to restart into.
1325 *
1326 * cr.imm contains zero_ext(imm21)
1327 */
1328 mov r18=cr.iim
1329 ;;
1330 mov r17=cr.iip
1331 shl r18=r18,43 // put sign bit in position (43=64-21)
1332 ;;
1333
1334 mov r16=cr.ipsr
1335 shr r18=r18,39 // sign extend (39=43-4)
1336 ;;
1337
1338 add r17=r17,r18 // now add the offset
1339 ;;
1340 mov cr.iip=r17
1341 dep r16=0,r16,41,2 // clear EI
1342 ;;
1343
1344 mov cr.ipsr=r16
1345 ;;
1346
1347 rfi // and go back
1348END(speculation_vector)
1349
1350 .org ia64_ivt+0x5800
1351/////////////////////////////////////////////////////////////////////////////////////////
1352// 0x5800 Entry 28 (size 16 bundles) Reserved
1353 DBG_FAULT(28)
1354 FAULT(28)
1355
1356 .org ia64_ivt+0x5900
1357/////////////////////////////////////////////////////////////////////////////////////////
1358// 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
1359ENTRY(debug_vector)
1360 DBG_FAULT(29)
1361 FAULT(29)
1362END(debug_vector)
1363
1364 .org ia64_ivt+0x5a00
1365/////////////////////////////////////////////////////////////////////////////////////////
1366// 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
1367ENTRY(unaligned_access)
1368 DBG_FAULT(30)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001369 mov r31=pr // prepare to save predicates
1370 ;;
1371 br.sptk.many dispatch_unaligned_handler
1372END(unaligned_access)
1373
1374 .org ia64_ivt+0x5b00
1375/////////////////////////////////////////////////////////////////////////////////////////
1376// 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
1377ENTRY(unsupported_data_reference)
1378 DBG_FAULT(31)
1379 FAULT(31)
1380END(unsupported_data_reference)
1381
1382 .org ia64_ivt+0x5c00
1383/////////////////////////////////////////////////////////////////////////////////////////
1384// 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64)
1385ENTRY(floating_point_fault)
1386 DBG_FAULT(32)
1387 FAULT(32)
1388END(floating_point_fault)
1389
1390 .org ia64_ivt+0x5d00
1391/////////////////////////////////////////////////////////////////////////////////////////
1392// 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
1393ENTRY(floating_point_trap)
1394 DBG_FAULT(33)
1395 FAULT(33)
1396END(floating_point_trap)
1397
1398 .org ia64_ivt+0x5e00
1399/////////////////////////////////////////////////////////////////////////////////////////
1400// 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
1401ENTRY(lower_privilege_trap)
1402 DBG_FAULT(34)
1403 FAULT(34)
1404END(lower_privilege_trap)
1405
1406 .org ia64_ivt+0x5f00
1407/////////////////////////////////////////////////////////////////////////////////////////
1408// 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
1409ENTRY(taken_branch_trap)
1410 DBG_FAULT(35)
1411 FAULT(35)
1412END(taken_branch_trap)
1413
1414 .org ia64_ivt+0x6000
1415/////////////////////////////////////////////////////////////////////////////////////////
1416// 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
1417ENTRY(single_step_trap)
1418 DBG_FAULT(36)
1419 FAULT(36)
1420END(single_step_trap)
1421
1422 .org ia64_ivt+0x6100
1423/////////////////////////////////////////////////////////////////////////////////////////
1424// 0x6100 Entry 37 (size 16 bundles) Reserved
1425 DBG_FAULT(37)
1426 FAULT(37)
1427
1428 .org ia64_ivt+0x6200
1429/////////////////////////////////////////////////////////////////////////////////////////
1430// 0x6200 Entry 38 (size 16 bundles) Reserved
1431 DBG_FAULT(38)
1432 FAULT(38)
1433
1434 .org ia64_ivt+0x6300
1435/////////////////////////////////////////////////////////////////////////////////////////
1436// 0x6300 Entry 39 (size 16 bundles) Reserved
1437 DBG_FAULT(39)
1438 FAULT(39)
1439
1440 .org ia64_ivt+0x6400
1441/////////////////////////////////////////////////////////////////////////////////////////
1442// 0x6400 Entry 40 (size 16 bundles) Reserved
1443 DBG_FAULT(40)
1444 FAULT(40)
1445
1446 .org ia64_ivt+0x6500
1447/////////////////////////////////////////////////////////////////////////////////////////
1448// 0x6500 Entry 41 (size 16 bundles) Reserved
1449 DBG_FAULT(41)
1450 FAULT(41)
1451
1452 .org ia64_ivt+0x6600
1453/////////////////////////////////////////////////////////////////////////////////////////
1454// 0x6600 Entry 42 (size 16 bundles) Reserved
1455 DBG_FAULT(42)
1456 FAULT(42)
1457
1458 .org ia64_ivt+0x6700
1459/////////////////////////////////////////////////////////////////////////////////////////
1460// 0x6700 Entry 43 (size 16 bundles) Reserved
1461 DBG_FAULT(43)
1462 FAULT(43)
1463
1464 .org ia64_ivt+0x6800
1465/////////////////////////////////////////////////////////////////////////////////////////
1466// 0x6800 Entry 44 (size 16 bundles) Reserved
1467 DBG_FAULT(44)
1468 FAULT(44)
1469
1470 .org ia64_ivt+0x6900
1471/////////////////////////////////////////////////////////////////////////////////////////
1472// 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77)
1473ENTRY(ia32_exception)
1474 DBG_FAULT(45)
1475 FAULT(45)
1476END(ia32_exception)
1477
1478 .org ia64_ivt+0x6a00
1479/////////////////////////////////////////////////////////////////////////////////////////
1480// 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71)
1481ENTRY(ia32_intercept)
1482 DBG_FAULT(46)
1483#ifdef CONFIG_IA32_SUPPORT
1484 mov r31=pr
1485 mov r16=cr.isr
1486 ;;
1487 extr.u r17=r16,16,8 // get ISR.code
1488 mov r18=ar.eflag
1489 mov r19=cr.iim // old eflag value
1490 ;;
1491 cmp.ne p6,p0=2,r17
1492(p6) br.cond.spnt 1f // not a system flag fault
1493 xor r16=r18,r19
1494 ;;
1495 extr.u r17=r16,18,1 // get the eflags.ac bit
1496 ;;
1497 cmp.eq p6,p0=0,r17
1498(p6) br.cond.spnt 1f // eflags.ac bit didn't change
1499 ;;
1500 mov pr=r31,-1 // restore predicate registers
1501 rfi
1502
15031:
1504#endif // CONFIG_IA32_SUPPORT
1505 FAULT(46)
1506END(ia32_intercept)
1507
1508 .org ia64_ivt+0x6b00
1509/////////////////////////////////////////////////////////////////////////////////////////
1510// 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74)
1511ENTRY(ia32_interrupt)
1512 DBG_FAULT(47)
1513#ifdef CONFIG_IA32_SUPPORT
1514 mov r31=pr
1515 br.sptk.many dispatch_to_ia32_handler
1516#else
1517 FAULT(47)
1518#endif
1519END(ia32_interrupt)
1520
1521 .org ia64_ivt+0x6c00
1522/////////////////////////////////////////////////////////////////////////////////////////
1523// 0x6c00 Entry 48 (size 16 bundles) Reserved
1524 DBG_FAULT(48)
1525 FAULT(48)
1526
1527 .org ia64_ivt+0x6d00
1528/////////////////////////////////////////////////////////////////////////////////////////
1529// 0x6d00 Entry 49 (size 16 bundles) Reserved
1530 DBG_FAULT(49)
1531 FAULT(49)
1532
1533 .org ia64_ivt+0x6e00
1534/////////////////////////////////////////////////////////////////////////////////////////
1535// 0x6e00 Entry 50 (size 16 bundles) Reserved
1536 DBG_FAULT(50)
1537 FAULT(50)
1538
1539 .org ia64_ivt+0x6f00
1540/////////////////////////////////////////////////////////////////////////////////////////
1541// 0x6f00 Entry 51 (size 16 bundles) Reserved
1542 DBG_FAULT(51)
1543 FAULT(51)
1544
1545 .org ia64_ivt+0x7000
1546/////////////////////////////////////////////////////////////////////////////////////////
1547// 0x7000 Entry 52 (size 16 bundles) Reserved
1548 DBG_FAULT(52)
1549 FAULT(52)
1550
1551 .org ia64_ivt+0x7100
1552/////////////////////////////////////////////////////////////////////////////////////////
1553// 0x7100 Entry 53 (size 16 bundles) Reserved
1554 DBG_FAULT(53)
1555 FAULT(53)
1556
1557 .org ia64_ivt+0x7200
1558/////////////////////////////////////////////////////////////////////////////////////////
1559// 0x7200 Entry 54 (size 16 bundles) Reserved
1560 DBG_FAULT(54)
1561 FAULT(54)
1562
1563 .org ia64_ivt+0x7300
1564/////////////////////////////////////////////////////////////////////////////////////////
1565// 0x7300 Entry 55 (size 16 bundles) Reserved
1566 DBG_FAULT(55)
1567 FAULT(55)
1568
1569 .org ia64_ivt+0x7400
1570/////////////////////////////////////////////////////////////////////////////////////////
1571// 0x7400 Entry 56 (size 16 bundles) Reserved
1572 DBG_FAULT(56)
1573 FAULT(56)
1574
1575 .org ia64_ivt+0x7500
1576/////////////////////////////////////////////////////////////////////////////////////////
1577// 0x7500 Entry 57 (size 16 bundles) Reserved
1578 DBG_FAULT(57)
1579 FAULT(57)
1580
1581 .org ia64_ivt+0x7600
1582/////////////////////////////////////////////////////////////////////////////////////////
1583// 0x7600 Entry 58 (size 16 bundles) Reserved
1584 DBG_FAULT(58)
1585 FAULT(58)
1586
1587 .org ia64_ivt+0x7700
1588/////////////////////////////////////////////////////////////////////////////////////////
1589// 0x7700 Entry 59 (size 16 bundles) Reserved
1590 DBG_FAULT(59)
1591 FAULT(59)
1592
1593 .org ia64_ivt+0x7800
1594/////////////////////////////////////////////////////////////////////////////////////////
1595// 0x7800 Entry 60 (size 16 bundles) Reserved
1596 DBG_FAULT(60)
1597 FAULT(60)
1598
1599 .org ia64_ivt+0x7900
1600/////////////////////////////////////////////////////////////////////////////////////////
1601// 0x7900 Entry 61 (size 16 bundles) Reserved
1602 DBG_FAULT(61)
1603 FAULT(61)
1604
1605 .org ia64_ivt+0x7a00
1606/////////////////////////////////////////////////////////////////////////////////////////
1607// 0x7a00 Entry 62 (size 16 bundles) Reserved
1608 DBG_FAULT(62)
1609 FAULT(62)
1610
1611 .org ia64_ivt+0x7b00
1612/////////////////////////////////////////////////////////////////////////////////////////
1613// 0x7b00 Entry 63 (size 16 bundles) Reserved
1614 DBG_FAULT(63)
1615 FAULT(63)
1616
1617 .org ia64_ivt+0x7c00
1618/////////////////////////////////////////////////////////////////////////////////////////
1619// 0x7c00 Entry 64 (size 16 bundles) Reserved
1620 DBG_FAULT(64)
1621 FAULT(64)
1622
1623 .org ia64_ivt+0x7d00
1624/////////////////////////////////////////////////////////////////////////////////////////
1625// 0x7d00 Entry 65 (size 16 bundles) Reserved
1626 DBG_FAULT(65)
1627 FAULT(65)
1628
1629 .org ia64_ivt+0x7e00
1630/////////////////////////////////////////////////////////////////////////////////////////
1631// 0x7e00 Entry 66 (size 16 bundles) Reserved
1632 DBG_FAULT(66)
1633 FAULT(66)
1634
1635 .org ia64_ivt+0x7f00
1636/////////////////////////////////////////////////////////////////////////////////////////
1637// 0x7f00 Entry 67 (size 16 bundles) Reserved
1638 DBG_FAULT(67)
1639 FAULT(67)
1640
1641#ifdef CONFIG_IA32_SUPPORT
1642
1643 /*
1644 * There is no particular reason for this code to be here, other than that
1645 * there happens to be space here that would go unused otherwise. If this
1646 * fault ever gets "unreserved", simply moved the following code to a more
1647 * suitable spot...
1648 */
1649
1650 // IA32 interrupt entry point
1651
1652ENTRY(dispatch_to_ia32_handler)
1653 SAVE_MIN
1654 ;;
1655 mov r14=cr.isr
1656 ssm psr.ic | PSR_DEFAULT_BITS
1657 ;;
1658 srlz.i // guarantee that interruption collection is on
1659 ;;
1660(p15) ssm psr.i
1661 adds r3=8,r2 // Base pointer for SAVE_REST
1662 ;;
1663 SAVE_REST
1664 ;;
1665 mov r15=0x80
1666 shr r14=r14,16 // Get interrupt number
1667 ;;
1668 cmp.ne p6,p0=r14,r15
1669(p6) br.call.dpnt.many b6=non_ia32_syscall
1670
1671 adds r14=IA64_PT_REGS_R8_OFFSET + 16,sp // 16 byte hole per SW conventions
1672 adds r15=IA64_PT_REGS_R1_OFFSET + 16,sp
1673 ;;
1674 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
1675 ld8 r8=[r14] // get r8
1676 ;;
1677 st8 [r15]=r8 // save original EAX in r1 (IA32 procs don't use the GP)
1678 ;;
1679 alloc r15=ar.pfs,0,0,6,0 // must first in an insn group
1680 ;;
1681 ld4 r8=[r14],8 // r8 == eax (syscall number)
1682 mov r15=IA32_NR_syscalls
1683 ;;
1684 cmp.ltu.unc p6,p7=r8,r15
1685 ld4 out1=[r14],8 // r9 == ecx
1686 ;;
1687 ld4 out2=[r14],8 // r10 == edx
1688 ;;
1689 ld4 out0=[r14] // r11 == ebx
1690 adds r14=(IA64_PT_REGS_R13_OFFSET) + 16,sp
1691 ;;
1692 ld4 out5=[r14],PT(R14)-PT(R13) // r13 == ebp
1693 ;;
1694 ld4 out3=[r14],PT(R15)-PT(R14) // r14 == esi
1695 adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
1696 ;;
1697 ld4 out4=[r14] // r15 == edi
1698 movl r16=ia32_syscall_table
1699 ;;
1700(p6) shladd r16=r8,3,r16 // force ni_syscall if not valid syscall number
1701 ld4 r2=[r2] // r2 = current_thread_info()->flags
1702 ;;
1703 ld8 r16=[r16]
1704 and r2=_TIF_SYSCALL_TRACEAUDIT,r2 // mask trace or audit
1705 ;;
1706 mov b6=r16
1707 movl r15=ia32_ret_from_syscall
1708 cmp.eq p8,p0=r2,r0
1709 ;;
1710 mov rp=r15
1711(p8) br.call.sptk.many b6=b6
1712 br.cond.sptk ia32_trace_syscall
1713
1714non_ia32_syscall:
1715 alloc r15=ar.pfs,0,0,2,0
1716 mov out0=r14 // interrupt #
1717 add out1=16,sp // pointer to pt_regs
1718 ;; // avoid WAW on CFM
1719 br.call.sptk.many rp=ia32_bad_interrupt
1720.ret1: movl r15=ia64_leave_kernel
1721 ;;
1722 mov rp=r15
1723 br.ret.sptk.many rp
1724END(dispatch_to_ia32_handler)
1725
1726#endif /* CONFIG_IA32_SUPPORT */