| Ian Molton | 4a48998 | 2008-07-15 16:02:21 +0100 | [diff] [blame] | 1 | /* Definitons for use with the tmio_mmc.c | 
 | 2 |  * | 
 | 3 |  * (c) 2004 Ian Molton <spyro@f2s.com> | 
 | 4 |  * (c) 2007 Ian Molton <spyro@f2s.com> | 
 | 5 |  * | 
 | 6 |  * This program is free software; you can redistribute it and/or modify | 
 | 7 |  * it under the terms of the GNU General Public License version 2 as | 
 | 8 |  * published by the Free Software Foundation. | 
 | 9 |  * | 
 | 10 |  */ | 
 | 11 | #define CNF_CMD     0x04 | 
 | 12 | #define CNF_CTL_BASE   0x10 | 
 | 13 | #define CNF_INT_PIN  0x3d | 
 | 14 | #define CNF_STOP_CLK_CTL 0x40 | 
 | 15 | #define CNF_GCLK_CTL 0x41 | 
 | 16 | #define CNF_SD_CLK_MODE 0x42 | 
 | 17 | #define CNF_PIN_STATUS 0x44 | 
 | 18 | #define CNF_PWR_CTL_1 0x48 | 
 | 19 | #define CNF_PWR_CTL_2 0x49 | 
 | 20 | #define CNF_PWR_CTL_3 0x4a | 
 | 21 | #define CNF_CARD_DETECT_MODE 0x4c | 
 | 22 | #define CNF_SD_SLOT 0x50 | 
 | 23 | #define CNF_EXT_GCLK_CTL_1 0xf0 | 
 | 24 | #define CNF_EXT_GCLK_CTL_2 0xf1 | 
 | 25 | #define CNF_EXT_GCLK_CTL_3 0xf9 | 
 | 26 | #define CNF_SD_LED_EN_1 0xfa | 
 | 27 | #define CNF_SD_LED_EN_2 0xfe | 
 | 28 |  | 
 | 29 | #define   SDCREN 0x2   /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/ | 
 | 30 |  | 
 | 31 | #define CTL_SD_CMD 0x00 | 
 | 32 | #define CTL_ARG_REG 0x04 | 
 | 33 | #define CTL_STOP_INTERNAL_ACTION 0x08 | 
 | 34 | #define CTL_XFER_BLK_COUNT 0xa | 
 | 35 | #define CTL_RESPONSE 0x0c | 
 | 36 | #define CTL_STATUS 0x1c | 
 | 37 | #define CTL_IRQ_MASK 0x20 | 
 | 38 | #define CTL_SD_CARD_CLK_CTL 0x24 | 
 | 39 | #define CTL_SD_XFER_LEN 0x26 | 
 | 40 | #define CTL_SD_MEM_CARD_OPT 0x28 | 
 | 41 | #define CTL_SD_ERROR_DETAIL_STATUS 0x2c | 
 | 42 | #define CTL_SD_DATA_PORT 0x30 | 
 | 43 | #define CTL_TRANSACTION_CTL 0x34 | 
 | 44 | #define CTL_RESET_SD 0xe0 | 
 | 45 | #define CTL_SDIO_REGS 0x100 | 
 | 46 | #define CTL_CLK_AND_WAIT_CTL 0x138 | 
 | 47 | #define CTL_RESET_SDIO 0x1e0 | 
 | 48 |  | 
 | 49 | /* Definitions for values the CTRL_STATUS register can take. */ | 
 | 50 | #define TMIO_STAT_CMDRESPEND    0x00000001 | 
 | 51 | #define TMIO_STAT_DATAEND       0x00000004 | 
 | 52 | #define TMIO_STAT_CARD_REMOVE   0x00000008 | 
 | 53 | #define TMIO_STAT_CARD_INSERT   0x00000010 | 
 | 54 | #define TMIO_STAT_SIGSTATE      0x00000020 | 
 | 55 | #define TMIO_STAT_WRPROTECT     0x00000080 | 
 | 56 | #define TMIO_STAT_CARD_REMOVE_A 0x00000100 | 
 | 57 | #define TMIO_STAT_CARD_INSERT_A 0x00000200 | 
 | 58 | #define TMIO_STAT_SIGSTATE_A    0x00000400 | 
 | 59 | #define TMIO_STAT_CMD_IDX_ERR   0x00010000 | 
 | 60 | #define TMIO_STAT_CRCFAIL       0x00020000 | 
 | 61 | #define TMIO_STAT_STOPBIT_ERR   0x00040000 | 
 | 62 | #define TMIO_STAT_DATATIMEOUT   0x00080000 | 
 | 63 | #define TMIO_STAT_RXOVERFLOW    0x00100000 | 
 | 64 | #define TMIO_STAT_TXUNDERRUN    0x00200000 | 
 | 65 | #define TMIO_STAT_CMDTIMEOUT    0x00400000 | 
 | 66 | #define TMIO_STAT_RXRDY         0x01000000 | 
 | 67 | #define TMIO_STAT_TXRQ          0x02000000 | 
 | 68 | #define TMIO_STAT_ILL_FUNC      0x20000000 | 
 | 69 | #define TMIO_STAT_CMD_BUSY      0x40000000 | 
 | 70 | #define TMIO_STAT_ILL_ACCESS    0x80000000 | 
 | 71 |  | 
 | 72 | /* Define some IRQ masks */ | 
 | 73 | /* This is the mask used at reset by the chip */ | 
 | 74 | #define TMIO_MASK_ALL           0x837f031d | 
 | 75 | #define TMIO_MASK_READOP  (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND | \ | 
 | 76 | 		TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT) | 
 | 77 | #define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND | \ | 
 | 78 | 		TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT) | 
 | 79 | #define TMIO_MASK_CMD     (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \ | 
 | 80 | 		TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT) | 
 | 81 | #define TMIO_MASK_IRQ     (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD) | 
 | 82 |  | 
 | 83 | #define enable_mmc_irqs(ctl, i) \ | 
 | 84 | 	do { \ | 
 | 85 | 		u32 mask;\ | 
 | 86 | 		mask  = tmio_ioread32((ctl) + CTL_IRQ_MASK); \ | 
 | 87 | 		mask &= ~((i) & TMIO_MASK_IRQ); \ | 
 | 88 | 		tmio_iowrite32(mask, (ctl) + CTL_IRQ_MASK); \ | 
 | 89 | 	} while (0) | 
 | 90 |  | 
 | 91 | #define disable_mmc_irqs(ctl, i) \ | 
 | 92 | 	do { \ | 
 | 93 | 		u32 mask;\ | 
 | 94 | 		mask  = tmio_ioread32((ctl) + CTL_IRQ_MASK); \ | 
 | 95 | 		mask |= ((i) & TMIO_MASK_IRQ); \ | 
 | 96 | 		tmio_iowrite32(mask, (ctl) + CTL_IRQ_MASK); \ | 
 | 97 | 	} while (0) | 
 | 98 |  | 
 | 99 | #define ack_mmc_irqs(ctl, i) \ | 
 | 100 | 	do { \ | 
 | 101 | 		u32 mask;\ | 
 | 102 | 		mask  = tmio_ioread32((ctl) + CTL_STATUS); \ | 
 | 103 | 		mask &= ~((i) & TMIO_MASK_IRQ); \ | 
 | 104 | 		tmio_iowrite32(mask, (ctl) + CTL_STATUS); \ | 
 | 105 | 	} while (0) | 
 | 106 |  | 
 | 107 |  | 
 | 108 | struct tmio_mmc_host { | 
 | 109 | 	void __iomem *cnf; | 
 | 110 | 	void __iomem *ctl; | 
 | 111 | 	struct mmc_command      *cmd; | 
 | 112 | 	struct mmc_request      *mrq; | 
 | 113 | 	struct mmc_data         *data; | 
 | 114 | 	struct mmc_host         *mmc; | 
 | 115 | 	int                     irq; | 
 | 116 |  | 
 | 117 | 	/* pio related stuff */ | 
 | 118 | 	struct scatterlist      *sg_ptr; | 
 | 119 | 	unsigned int            sg_len; | 
 | 120 | 	unsigned int            sg_off; | 
 | 121 | }; | 
 | 122 |  | 
 | 123 | #include <linux/scatterlist.h> | 
 | 124 | #include <linux/blkdev.h> | 
 | 125 |  | 
 | 126 | static inline void tmio_mmc_init_sg(struct tmio_mmc_host *host, | 
 | 127 | 	struct mmc_data *data) | 
 | 128 | { | 
 | 129 | 	host->sg_len = data->sg_len; | 
 | 130 | 	host->sg_ptr = data->sg; | 
 | 131 | 	host->sg_off = 0; | 
 | 132 | } | 
 | 133 |  | 
 | 134 | static inline int tmio_mmc_next_sg(struct tmio_mmc_host *host) | 
 | 135 | { | 
 | 136 | 	host->sg_ptr = sg_next(host->sg_ptr); | 
 | 137 | 	host->sg_off = 0; | 
 | 138 | 	return --host->sg_len; | 
 | 139 | } | 
 | 140 |  | 
 | 141 | static inline char *tmio_mmc_kmap_atomic(struct tmio_mmc_host *host, | 
 | 142 | 	unsigned long *flags) | 
 | 143 | { | 
 | 144 | 	struct scatterlist *sg = host->sg_ptr; | 
 | 145 |  | 
 | 146 | 	local_irq_save(*flags); | 
 | 147 | 	return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; | 
 | 148 | } | 
 | 149 |  | 
 | 150 | static inline void tmio_mmc_kunmap_atomic(struct tmio_mmc_host *host, | 
 | 151 | 	unsigned long *flags) | 
 | 152 | { | 
 | 153 | 	kunmap_atomic(sg_page(host->sg_ptr), KM_BIO_SRC_IRQ); | 
 | 154 | 	local_irq_restore(*flags); | 
 | 155 | } | 
 | 156 |  | 
 | 157 | #ifdef CONFIG_MMC_DEBUG | 
 | 158 |  | 
 | 159 | #define STATUS_TO_TEXT(a) \ | 
 | 160 | 	do { \ | 
 | 161 | 		if (status & TMIO_STAT_##a) \ | 
| Dmitry Baryshkov | fe246eb | 2008-09-03 19:33:30 +0400 | [diff] [blame] | 162 | 			printk(#a); \ | 
| Ian Molton | 4a48998 | 2008-07-15 16:02:21 +0100 | [diff] [blame] | 163 | 	} while (0) | 
 | 164 |  | 
| Dmitry Baryshkov | fe246eb | 2008-09-03 19:33:30 +0400 | [diff] [blame] | 165 | void pr_debug_status(u32 status) | 
| Ian Molton | 4a48998 | 2008-07-15 16:02:21 +0100 | [diff] [blame] | 166 | { | 
 | 167 | 	printk(KERN_DEBUG "status: %08x = ", status); | 
 | 168 | 	STATUS_TO_TEXT(CARD_REMOVE); | 
 | 169 | 	STATUS_TO_TEXT(CARD_INSERT); | 
 | 170 | 	STATUS_TO_TEXT(SIGSTATE); | 
 | 171 | 	STATUS_TO_TEXT(WRPROTECT); | 
 | 172 | 	STATUS_TO_TEXT(CARD_REMOVE_A); | 
 | 173 | 	STATUS_TO_TEXT(CARD_INSERT_A); | 
 | 174 | 	STATUS_TO_TEXT(SIGSTATE_A); | 
 | 175 | 	STATUS_TO_TEXT(CMD_IDX_ERR); | 
 | 176 | 	STATUS_TO_TEXT(STOPBIT_ERR); | 
 | 177 | 	STATUS_TO_TEXT(ILL_FUNC); | 
 | 178 | 	STATUS_TO_TEXT(CMD_BUSY); | 
 | 179 | 	STATUS_TO_TEXT(CMDRESPEND); | 
 | 180 | 	STATUS_TO_TEXT(DATAEND); | 
 | 181 | 	STATUS_TO_TEXT(CRCFAIL); | 
 | 182 | 	STATUS_TO_TEXT(DATATIMEOUT); | 
 | 183 | 	STATUS_TO_TEXT(CMDTIMEOUT); | 
 | 184 | 	STATUS_TO_TEXT(RXOVERFLOW); | 
 | 185 | 	STATUS_TO_TEXT(TXUNDERRUN); | 
 | 186 | 	STATUS_TO_TEXT(RXRDY); | 
 | 187 | 	STATUS_TO_TEXT(TXRQ); | 
 | 188 | 	STATUS_TO_TEXT(ILL_ACCESS); | 
 | 189 | 	printk("\n"); | 
 | 190 | } | 
 | 191 |  | 
 | 192 | #else | 
 | 193 | #define pr_debug_status(s)  do { } while (0) | 
 | 194 | #endif |