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review.evervolv.com / android_kernel_oneplus_msm8996 / 2039238b79b51a50f8477f53f33750e1c3fc146a / . / include / asm-x86 / calling.h
blob: f13e62e2cb3e75160297459ef182921b170d0850 [file] [log] [blame]
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]1/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2 * Some macros to handle stack frames in assembly.
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]3 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]5#define R15 0
6#define R14 8
7#define R13 16
8#define R12 24
9#define RBP 32
10#define RBX 40
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]11
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]12/* arguments: interrupts/non tracing syscalls only save upto here*/
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]13#define R11 48
14#define R10 56
15#define R9 64
16#define R8 72
17#define RAX 80
18#define RCX 88
19#define RDX 96
20#define RSI 104
21#define RDI 112
22#define ORIG_RAX 120 /* + error_code */
23/* end of arguments */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]24
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]25/* cpu exception frame or undefined in case of fast syscall. */
26#define RIP 128
27#define CS 136
28#define EFLAGS 144
29#define RSP 152
30#define SS 160
31
32#define ARGOFFSET R11
33#define SWFRAME ORIG_RAX
34
35 .macro SAVE_ARGS addskip=0, norcx=0, nor891011=0
36 subq $9*8+\addskip, %rsp
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]37 CFI_ADJUST_CFA_OFFSET 9*8+\addskip
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]38 movq %rdi, 8*8(%rsp)
39 CFI_REL_OFFSET rdi, 8*8
40 movq %rsi, 7*8(%rsp)
41 CFI_REL_OFFSET rsi, 7*8
42 movq %rdx, 6*8(%rsp)
43 CFI_REL_OFFSET rdx, 6*8
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]44 .if \norcx
45 .else
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]46 movq %rcx, 5*8(%rsp)
47 CFI_REL_OFFSET rcx, 5*8
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]48 .endif
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]49 movq %rax, 4*8(%rsp)
50 CFI_REL_OFFSET rax, 4*8
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]51 .if \nor891011
52 .else
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]53 movq %r8, 3*8(%rsp)
54 CFI_REL_OFFSET r8, 3*8
55 movq %r9, 2*8(%rsp)
56 CFI_REL_OFFSET r9, 2*8
57 movq %r10, 1*8(%rsp)
58 CFI_REL_OFFSET r10, 1*8
59 movq %r11, (%rsp)
60 CFI_REL_OFFSET r11, 0*8
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]61 .endif
62 .endm
63
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]64#define ARG_SKIP 9*8
65
66 .macro RESTORE_ARGS skiprax=0, addskip=0, skiprcx=0, skipr11=0, \
67 skipr8910=0, skiprdx=0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]68 .if \skipr11
69 .else
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]70 movq (%rsp), %r11
Jan Beulich7effaa82005-09-12 18:49:24 +0200[diff] [blame]71 CFI_RESTORE r11
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]72 .endif
73 .if \skipr8910
74 .else
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]75 movq 1*8(%rsp), %r10
Jan Beulich7effaa82005-09-12 18:49:24 +0200[diff] [blame]76 CFI_RESTORE r10
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]77 movq 2*8(%rsp), %r9
Jan Beulich7effaa82005-09-12 18:49:24 +0200[diff] [blame]78 CFI_RESTORE r9
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]79 movq 3*8(%rsp), %r8
Jan Beulich7effaa82005-09-12 18:49:24 +0200[diff] [blame]80 CFI_RESTORE r8
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]81 .endif
82 .if \skiprax
83 .else
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]84 movq 4*8(%rsp), %rax
Jan Beulich7effaa82005-09-12 18:49:24 +0200[diff] [blame]85 CFI_RESTORE rax
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]86 .endif
87 .if \skiprcx
88 .else
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]89 movq 5*8(%rsp), %rcx
Jan Beulich7effaa82005-09-12 18:49:24 +0200[diff] [blame]90 CFI_RESTORE rcx
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]91 .endif
92 .if \skiprdx
93 .else
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]94 movq 6*8(%rsp), %rdx
Jan Beulich7effaa82005-09-12 18:49:24 +0200[diff] [blame]95 CFI_RESTORE rdx
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]96 .endif
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]97 movq 7*8(%rsp), %rsi
Jan Beulich7effaa82005-09-12 18:49:24 +0200[diff] [blame]98 CFI_RESTORE rsi
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]99 movq 8*8(%rsp), %rdi
Jan Beulich7effaa82005-09-12 18:49:24 +0200[diff] [blame]100 CFI_RESTORE rdi
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]101 .if ARG_SKIP+\addskip > 0
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]102 addq $ARG_SKIP+\addskip, %rsp
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]103 CFI_ADJUST_CFA_OFFSET -(ARG_SKIP+\addskip)
104 .endif
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]105 .endm
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]106
107 .macro LOAD_ARGS offset
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]108 movq \offset(%rsp), %r11
109 movq \offset+8(%rsp), %r10
110 movq \offset+16(%rsp), %r9
111 movq \offset+24(%rsp), %r8
112 movq \offset+40(%rsp), %rcx
113 movq \offset+48(%rsp), %rdx
114 movq \offset+56(%rsp), %rsi
115 movq \offset+64(%rsp), %rdi
116 movq \offset+72(%rsp), %rax
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]117 .endm
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]118
119#define REST_SKIP 6*8
120
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]121 .macro SAVE_REST
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]122 subq $REST_SKIP, %rsp
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]123 CFI_ADJUST_CFA_OFFSET REST_SKIP
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]124 movq %rbx, 5*8(%rsp)
125 CFI_REL_OFFSET rbx, 5*8
126 movq %rbp, 4*8(%rsp)
127 CFI_REL_OFFSET rbp, 4*8
128 movq %r12, 3*8(%rsp)
129 CFI_REL_OFFSET r12, 3*8
130 movq %r13, 2*8(%rsp)
131 CFI_REL_OFFSET r13, 2*8
132 movq %r14, 1*8(%rsp)
133 CFI_REL_OFFSET r14, 1*8
134 movq %r15, (%rsp)
135 CFI_REL_OFFSET r15, 0*8
136 .endm
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]137
138 .macro RESTORE_REST
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]139 movq (%rsp), %r15
Jan Beulich7effaa82005-09-12 18:49:24 +0200[diff] [blame]140 CFI_RESTORE r15
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]141 movq 1*8(%rsp), %r14
Jan Beulich7effaa82005-09-12 18:49:24 +0200[diff] [blame]142 CFI_RESTORE r14
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]143 movq 2*8(%rsp), %r13
Jan Beulich7effaa82005-09-12 18:49:24 +0200[diff] [blame]144 CFI_RESTORE r13
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]145 movq 3*8(%rsp), %r12
Jan Beulich7effaa82005-09-12 18:49:24 +0200[diff] [blame]146 CFI_RESTORE r12
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]147 movq 4*8(%rsp), %rbp
Jan Beulich7effaa82005-09-12 18:49:24 +0200[diff] [blame]148 CFI_RESTORE rbp
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]149 movq 5*8(%rsp), %rbx
Jan Beulich7effaa82005-09-12 18:49:24 +0200[diff] [blame]150 CFI_RESTORE rbx
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]151 addq $REST_SKIP, %rsp
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]152 CFI_ADJUST_CFA_OFFSET -(REST_SKIP)
153 .endm
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]154
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]155 .macro SAVE_ALL
156 SAVE_ARGS
157 SAVE_REST
158 .endm
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]159
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]160 .macro RESTORE_ALL addskip=0
161 RESTORE_REST
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]162 RESTORE_ARGS 0, \addskip
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]163 .endm
164
165 .macro icebp
166 .byte 0xf1
167 .endm
Ingo Molnar0c2bd5a2008-01-30 13:32:49 +0100[diff] [blame]168