blob: 3992e48b4c71b8d628912459fe116f01bba09848 [file] [log] [blame]
Thomas Bogendoerfereea63e02008-02-06 01:37:27 -08001/*
2 * SC268xx.c: Serial driver for Philiphs SC2681/SC2692 devices.
3 *
4 * Copyright (C) 2006,2007 Thomas Bogendörfer (tsbogend@alpha.franken.de)
5 */
6
7#include <linux/module.h>
8#include <linux/kernel.h>
9#include <linux/errno.h>
10#include <linux/tty.h>
11#include <linux/tty_flip.h>
12#include <linux/major.h>
13#include <linux/circ_buf.h>
14#include <linux/serial.h>
15#include <linux/sysrq.h>
16#include <linux/console.h>
17#include <linux/spinlock.h>
18#include <linux/slab.h>
19#include <linux/delay.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/irq.h>
Alexander Shiyan221ca772012-08-01 12:00:20 +040023#include <linux/io.h>
Thomas Bogendoerfereea63e02008-02-06 01:37:27 -080024
25#if defined(CONFIG_MAGIC_SYSRQ)
26#define SUPPORT_SYSRQ
27#endif
28
29#include <linux/serial_core.h>
30
31#define SC26XX_MAJOR 204
32#define SC26XX_MINOR_START 205
33#define SC26XX_NR 2
34
35struct uart_sc26xx_port {
36 struct uart_port port[2];
37 u8 dsr_mask[2];
38 u8 cts_mask[2];
39 u8 dcd_mask[2];
40 u8 ri_mask[2];
41 u8 dtr_mask[2];
42 u8 rts_mask[2];
43 u8 imr;
44};
45
46/* register common to both ports */
47#define RD_ISR 0x14
48#define RD_IPR 0x34
49
50#define WR_ACR 0x10
51#define WR_IMR 0x14
52#define WR_OPCR 0x34
53#define WR_OPR_SET 0x38
54#define WR_OPR_CLR 0x3C
55
56/* access common register */
57#define READ_SC(p, r) readb((p)->membase + RD_##r)
58#define WRITE_SC(p, r, v) writeb((v), (p)->membase + WR_##r)
59
60/* register per port */
61#define RD_PORT_MRx 0x00
62#define RD_PORT_SR 0x04
63#define RD_PORT_RHR 0x0c
64
65#define WR_PORT_MRx 0x00
66#define WR_PORT_CSR 0x04
67#define WR_PORT_CR 0x08
68#define WR_PORT_THR 0x0c
69
70/* SR bits */
71#define SR_BREAK (1 << 7)
72#define SR_FRAME (1 << 6)
73#define SR_PARITY (1 << 5)
74#define SR_OVERRUN (1 << 4)
75#define SR_TXRDY (1 << 2)
76#define SR_RXRDY (1 << 0)
77
78#define CR_RES_MR (1 << 4)
79#define CR_RES_RX (2 << 4)
80#define CR_RES_TX (3 << 4)
81#define CR_STRT_BRK (6 << 4)
82#define CR_STOP_BRK (7 << 4)
83#define CR_DIS_TX (1 << 3)
84#define CR_ENA_TX (1 << 2)
85#define CR_DIS_RX (1 << 1)
86#define CR_ENA_RX (1 << 0)
87
88/* ISR bits */
89#define ISR_RXRDYB (1 << 5)
90#define ISR_TXRDYB (1 << 4)
91#define ISR_RXRDYA (1 << 1)
92#define ISR_TXRDYA (1 << 0)
93
94/* IMR bits */
95#define IMR_RXRDY (1 << 1)
96#define IMR_TXRDY (1 << 0)
97
98/* access port register */
99static inline u8 read_sc_port(struct uart_port *p, u8 reg)
100{
101 return readb(p->membase + p->line * 0x20 + reg);
102}
103
104static inline void write_sc_port(struct uart_port *p, u8 reg, u8 val)
105{
106 writeb(val, p->membase + p->line * 0x20 + reg);
107}
108
109#define READ_SC_PORT(p, r) read_sc_port(p, RD_PORT_##r)
110#define WRITE_SC_PORT(p, r, v) write_sc_port(p, WR_PORT_##r, v)
111
112static void sc26xx_enable_irq(struct uart_port *port, int mask)
113{
114 struct uart_sc26xx_port *up;
115 int line = port->line;
116
117 port -= line;
118 up = container_of(port, struct uart_sc26xx_port, port[0]);
119
120 up->imr |= mask << (line * 4);
121 WRITE_SC(port, IMR, up->imr);
122}
123
124static void sc26xx_disable_irq(struct uart_port *port, int mask)
125{
126 struct uart_sc26xx_port *up;
127 int line = port->line;
128
129 port -= line;
130 up = container_of(port, struct uart_sc26xx_port, port[0]);
131
132 up->imr &= ~(mask << (line * 4));
133 WRITE_SC(port, IMR, up->imr);
134}
135
136static struct tty_struct *receive_chars(struct uart_port *port)
137{
138 struct tty_struct *tty = NULL;
139 int limit = 10000;
140 unsigned char ch;
141 char flag;
142 u8 status;
143
Alan Coxebd2c8f2009-09-19 13:13:28 -0700144 if (port->state != NULL) /* Unopened serial console */
145 tty = port->state->port.tty;
Thomas Bogendoerfereea63e02008-02-06 01:37:27 -0800146
147 while (limit-- > 0) {
148 status = READ_SC_PORT(port, SR);
149 if (!(status & SR_RXRDY))
150 break;
151 ch = READ_SC_PORT(port, RHR);
152
153 flag = TTY_NORMAL;
154 port->icount.rx++;
155
156 if (unlikely(status & (SR_BREAK | SR_FRAME |
157 SR_PARITY | SR_OVERRUN))) {
158 if (status & SR_BREAK) {
159 status &= ~(SR_PARITY | SR_FRAME);
160 port->icount.brk++;
161 if (uart_handle_break(port))
162 continue;
163 } else if (status & SR_PARITY)
164 port->icount.parity++;
165 else if (status & SR_FRAME)
166 port->icount.frame++;
167 if (status & SR_OVERRUN)
168 port->icount.overrun++;
169
170 status &= port->read_status_mask;
171 if (status & SR_BREAK)
172 flag = TTY_BREAK;
173 else if (status & SR_PARITY)
174 flag = TTY_PARITY;
175 else if (status & SR_FRAME)
176 flag = TTY_FRAME;
177 }
178
179 if (uart_handle_sysrq_char(port, ch))
180 continue;
181
182 if (status & port->ignore_status_mask)
183 continue;
184
185 tty_insert_flip_char(tty, ch, flag);
186 }
187 return tty;
188}
189
190static void transmit_chars(struct uart_port *port)
191{
192 struct circ_buf *xmit;
193
Alan Coxebd2c8f2009-09-19 13:13:28 -0700194 if (!port->state)
Thomas Bogendoerfereea63e02008-02-06 01:37:27 -0800195 return;
196
Alan Coxebd2c8f2009-09-19 13:13:28 -0700197 xmit = &port->state->xmit;
Thomas Bogendoerfereea63e02008-02-06 01:37:27 -0800198 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
199 sc26xx_disable_irq(port, IMR_TXRDY);
200 return;
201 }
202 while (!uart_circ_empty(xmit)) {
203 if (!(READ_SC_PORT(port, SR) & SR_TXRDY))
204 break;
205
206 WRITE_SC_PORT(port, THR, xmit->buf[xmit->tail]);
207 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
208 port->icount.tx++;
209 }
210 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
211 uart_write_wakeup(port);
212}
213
214static irqreturn_t sc26xx_interrupt(int irq, void *dev_id)
215{
216 struct uart_sc26xx_port *up = dev_id;
217 struct tty_struct *tty;
218 unsigned long flags;
219 u8 isr;
220
221 spin_lock_irqsave(&up->port[0].lock, flags);
222
223 tty = NULL;
224 isr = READ_SC(&up->port[0], ISR);
225 if (isr & ISR_TXRDYA)
226 transmit_chars(&up->port[0]);
227 if (isr & ISR_RXRDYA)
228 tty = receive_chars(&up->port[0]);
229
230 spin_unlock(&up->port[0].lock);
231
232 if (tty)
233 tty_flip_buffer_push(tty);
234
235 spin_lock(&up->port[1].lock);
236
237 tty = NULL;
238 if (isr & ISR_TXRDYB)
239 transmit_chars(&up->port[1]);
240 if (isr & ISR_RXRDYB)
241 tty = receive_chars(&up->port[1]);
242
243 spin_unlock_irqrestore(&up->port[1].lock, flags);
244
245 if (tty)
246 tty_flip_buffer_push(tty);
247
248 return IRQ_HANDLED;
249}
250
251/* port->lock is not held. */
252static unsigned int sc26xx_tx_empty(struct uart_port *port)
253{
254 return (READ_SC_PORT(port, SR) & SR_TXRDY) ? TIOCSER_TEMT : 0;
255}
256
257/* port->lock held by caller. */
258static void sc26xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
259{
260 struct uart_sc26xx_port *up;
261 int line = port->line;
262
263 port -= line;
264 up = container_of(port, struct uart_sc26xx_port, port[0]);
265
266 if (up->dtr_mask[line]) {
267 if (mctrl & TIOCM_DTR)
268 WRITE_SC(port, OPR_SET, up->dtr_mask[line]);
269 else
270 WRITE_SC(port, OPR_CLR, up->dtr_mask[line]);
271 }
272 if (up->rts_mask[line]) {
273 if (mctrl & TIOCM_RTS)
274 WRITE_SC(port, OPR_SET, up->rts_mask[line]);
275 else
276 WRITE_SC(port, OPR_CLR, up->rts_mask[line]);
277 }
278}
279
280/* port->lock is held by caller and interrupts are disabled. */
281static unsigned int sc26xx_get_mctrl(struct uart_port *port)
282{
283 struct uart_sc26xx_port *up;
284 int line = port->line;
285 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
286 u8 ipr;
287
288 port -= line;
289 up = container_of(port, struct uart_sc26xx_port, port[0]);
290 ipr = READ_SC(port, IPR) ^ 0xff;
291
292 if (up->dsr_mask[line]) {
293 mctrl &= ~TIOCM_DSR;
294 mctrl |= ipr & up->dsr_mask[line] ? TIOCM_DSR : 0;
295 }
296 if (up->cts_mask[line]) {
297 mctrl &= ~TIOCM_CTS;
298 mctrl |= ipr & up->cts_mask[line] ? TIOCM_CTS : 0;
299 }
300 if (up->dcd_mask[line]) {
301 mctrl &= ~TIOCM_CAR;
302 mctrl |= ipr & up->dcd_mask[line] ? TIOCM_CAR : 0;
303 }
304 if (up->ri_mask[line]) {
305 mctrl &= ~TIOCM_RNG;
306 mctrl |= ipr & up->ri_mask[line] ? TIOCM_RNG : 0;
307 }
308 return mctrl;
309}
310
311/* port->lock held by caller. */
312static void sc26xx_stop_tx(struct uart_port *port)
313{
314 return;
315}
316
317/* port->lock held by caller. */
318static void sc26xx_start_tx(struct uart_port *port)
319{
Alan Coxebd2c8f2009-09-19 13:13:28 -0700320 struct circ_buf *xmit = &port->state->xmit;
Thomas Bogendoerfereea63e02008-02-06 01:37:27 -0800321
322 while (!uart_circ_empty(xmit)) {
323 if (!(READ_SC_PORT(port, SR) & SR_TXRDY)) {
324 sc26xx_enable_irq(port, IMR_TXRDY);
325 break;
326 }
327 WRITE_SC_PORT(port, THR, xmit->buf[xmit->tail]);
328 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
329 port->icount.tx++;
330 }
331}
332
333/* port->lock held by caller. */
334static void sc26xx_stop_rx(struct uart_port *port)
335{
336}
337
338/* port->lock held by caller. */
339static void sc26xx_enable_ms(struct uart_port *port)
340{
341}
342
343/* port->lock is not held. */
344static void sc26xx_break_ctl(struct uart_port *port, int break_state)
345{
346 if (break_state == -1)
347 WRITE_SC_PORT(port, CR, CR_STRT_BRK);
348 else
349 WRITE_SC_PORT(port, CR, CR_STOP_BRK);
350}
351
352/* port->lock is not held. */
353static int sc26xx_startup(struct uart_port *port)
354{
355 sc26xx_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
356 WRITE_SC(port, OPCR, 0);
357
358 /* reset tx and rx */
359 WRITE_SC_PORT(port, CR, CR_RES_RX);
360 WRITE_SC_PORT(port, CR, CR_RES_TX);
361
362 /* start rx/tx */
363 WRITE_SC_PORT(port, CR, CR_ENA_TX | CR_ENA_RX);
364
365 /* enable irqs */
366 sc26xx_enable_irq(port, IMR_RXRDY);
367 return 0;
368}
369
370/* port->lock is not held. */
371static void sc26xx_shutdown(struct uart_port *port)
372{
373 /* disable interrupst */
374 sc26xx_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
375
376 /* stop tx/rx */
377 WRITE_SC_PORT(port, CR, CR_DIS_TX | CR_DIS_RX);
378}
379
380/* port->lock is not held. */
381static void sc26xx_set_termios(struct uart_port *port, struct ktermios *termios,
382 struct ktermios *old)
383{
384 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
385 unsigned int quot = uart_get_divisor(port, baud);
386 unsigned int iflag, cflag;
387 unsigned long flags;
388 u8 mr1, mr2, csr;
389
390 spin_lock_irqsave(&port->lock, flags);
391
392 while ((READ_SC_PORT(port, SR) & ((1 << 3) | (1 << 2))) != 0xc)
393 udelay(2);
394
395 WRITE_SC_PORT(port, CR, CR_DIS_TX | CR_DIS_RX);
396
397 iflag = termios->c_iflag;
398 cflag = termios->c_cflag;
399
400 port->read_status_mask = SR_OVERRUN;
401 if (iflag & INPCK)
402 port->read_status_mask |= SR_PARITY | SR_FRAME;
403 if (iflag & (BRKINT | PARMRK))
404 port->read_status_mask |= SR_BREAK;
405
406 port->ignore_status_mask = 0;
407 if (iflag & IGNBRK)
408 port->ignore_status_mask |= SR_BREAK;
409 if ((cflag & CREAD) == 0)
410 port->ignore_status_mask |= SR_BREAK | SR_FRAME |
411 SR_PARITY | SR_OVERRUN;
412
413 switch (cflag & CSIZE) {
414 case CS5:
415 mr1 = 0x00;
416 break;
417 case CS6:
418 mr1 = 0x01;
419 break;
420 case CS7:
421 mr1 = 0x02;
422 break;
423 default:
424 case CS8:
425 mr1 = 0x03;
426 break;
427 }
428 mr2 = 0x07;
429 if (cflag & CSTOPB)
430 mr2 = 0x0f;
431 if (cflag & PARENB) {
432 if (cflag & PARODD)
433 mr1 |= (1 << 2);
434 } else
435 mr1 |= (2 << 3);
436
437 switch (baud) {
438 case 50:
439 csr = 0x00;
440 break;
441 case 110:
442 csr = 0x11;
443 break;
444 case 134:
445 csr = 0x22;
446 break;
447 case 200:
448 csr = 0x33;
449 break;
450 case 300:
451 csr = 0x44;
452 break;
453 case 600:
454 csr = 0x55;
455 break;
456 case 1200:
457 csr = 0x66;
458 break;
459 case 2400:
460 csr = 0x88;
461 break;
462 case 4800:
463 csr = 0x99;
464 break;
465 default:
466 case 9600:
467 csr = 0xbb;
468 break;
469 case 19200:
470 csr = 0xcc;
471 break;
472 }
473
474 WRITE_SC_PORT(port, CR, CR_RES_MR);
475 WRITE_SC_PORT(port, MRx, mr1);
476 WRITE_SC_PORT(port, MRx, mr2);
477
478 WRITE_SC(port, ACR, 0x80);
479 WRITE_SC_PORT(port, CSR, csr);
480
481 /* reset tx and rx */
482 WRITE_SC_PORT(port, CR, CR_RES_RX);
483 WRITE_SC_PORT(port, CR, CR_RES_TX);
484
485 WRITE_SC_PORT(port, CR, CR_ENA_TX | CR_ENA_RX);
486 while ((READ_SC_PORT(port, SR) & ((1 << 3) | (1 << 2))) != 0xc)
487 udelay(2);
488
489 /* XXX */
490 uart_update_timeout(port, cflag,
491 (port->uartclk / (16 * quot)));
492
493 spin_unlock_irqrestore(&port->lock, flags);
494}
495
496static const char *sc26xx_type(struct uart_port *port)
497{
498 return "SC26XX";
499}
500
501static void sc26xx_release_port(struct uart_port *port)
502{
503}
504
505static int sc26xx_request_port(struct uart_port *port)
506{
507 return 0;
508}
509
510static void sc26xx_config_port(struct uart_port *port, int flags)
511{
512}
513
514static int sc26xx_verify_port(struct uart_port *port, struct serial_struct *ser)
515{
516 return -EINVAL;
517}
518
519static struct uart_ops sc26xx_ops = {
520 .tx_empty = sc26xx_tx_empty,
521 .set_mctrl = sc26xx_set_mctrl,
522 .get_mctrl = sc26xx_get_mctrl,
523 .stop_tx = sc26xx_stop_tx,
524 .start_tx = sc26xx_start_tx,
525 .stop_rx = sc26xx_stop_rx,
526 .enable_ms = sc26xx_enable_ms,
527 .break_ctl = sc26xx_break_ctl,
528 .startup = sc26xx_startup,
529 .shutdown = sc26xx_shutdown,
530 .set_termios = sc26xx_set_termios,
531 .type = sc26xx_type,
532 .release_port = sc26xx_release_port,
533 .request_port = sc26xx_request_port,
534 .config_port = sc26xx_config_port,
535 .verify_port = sc26xx_verify_port,
536};
537
538static struct uart_port *sc26xx_port;
539
540#ifdef CONFIG_SERIAL_SC26XX_CONSOLE
541static void sc26xx_console_putchar(struct uart_port *port, char c)
542{
543 unsigned long flags;
544 int limit = 1000000;
545
546 spin_lock_irqsave(&port->lock, flags);
547
548 while (limit-- > 0) {
549 if (READ_SC_PORT(port, SR) & SR_TXRDY) {
550 WRITE_SC_PORT(port, THR, c);
551 break;
552 }
553 udelay(2);
554 }
555
556 spin_unlock_irqrestore(&port->lock, flags);
557}
558
559static void sc26xx_console_write(struct console *con, const char *s, unsigned n)
560{
561 struct uart_port *port = sc26xx_port;
562 int i;
563
564 for (i = 0; i < n; i++) {
565 if (*s == '\n')
566 sc26xx_console_putchar(port, '\r');
567 sc26xx_console_putchar(port, *s++);
568 }
569}
570
571static int __init sc26xx_console_setup(struct console *con, char *options)
572{
573 struct uart_port *port = sc26xx_port;
574 int baud = 9600;
575 int bits = 8;
576 int parity = 'n';
577 int flow = 'n';
578
579 if (port->type != PORT_SC26XX)
580 return -1;
581
582 printk(KERN_INFO "Console: ttySC%d (SC26XX)\n", con->index);
583 if (options)
584 uart_parse_options(options, &baud, &parity, &bits, &flow);
585
586 return uart_set_options(port, con, baud, parity, bits, flow);
587}
588
589static struct uart_driver sc26xx_reg;
590static struct console sc26xx_console = {
591 .name = "ttySC",
592 .write = sc26xx_console_write,
593 .device = uart_console_device,
594 .setup = sc26xx_console_setup,
595 .flags = CON_PRINTBUFFER,
596 .index = -1,
597 .data = &sc26xx_reg,
598};
599#define SC26XX_CONSOLE &sc26xx_console
600#else
601#define SC26XX_CONSOLE NULL
602#endif
603
604static struct uart_driver sc26xx_reg = {
605 .owner = THIS_MODULE,
606 .driver_name = "SC26xx",
607 .dev_name = "ttySC",
608 .major = SC26XX_MAJOR,
609 .minor = SC26XX_MINOR_START,
610 .nr = SC26XX_NR,
611 .cons = SC26XX_CONSOLE,
612};
613
614static u8 sc26xx_flags2mask(unsigned int flags, unsigned int bitpos)
615{
616 unsigned int bit = (flags >> bitpos) & 15;
617
618 return bit ? (1 << (bit - 1)) : 0;
619}
620
621static void __devinit sc26xx_init_masks(struct uart_sc26xx_port *up,
622 int line, unsigned int data)
623{
624 up->dtr_mask[line] = sc26xx_flags2mask(data, 0);
625 up->rts_mask[line] = sc26xx_flags2mask(data, 4);
626 up->dsr_mask[line] = sc26xx_flags2mask(data, 8);
627 up->cts_mask[line] = sc26xx_flags2mask(data, 12);
628 up->dcd_mask[line] = sc26xx_flags2mask(data, 16);
629 up->ri_mask[line] = sc26xx_flags2mask(data, 20);
630}
631
632static int __devinit sc26xx_probe(struct platform_device *dev)
633{
634 struct resource *res;
635 struct uart_sc26xx_port *up;
636 unsigned int *sc26xx_data = dev->dev.platform_data;
637 int err;
638
639 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
640 if (!res)
641 return -ENODEV;
642
643 up = kzalloc(sizeof *up, GFP_KERNEL);
644 if (unlikely(!up))
645 return -ENOMEM;
646
647 up->port[0].line = 0;
648 up->port[0].ops = &sc26xx_ops;
649 up->port[0].type = PORT_SC26XX;
650 up->port[0].uartclk = (29491200 / 16); /* arbitrary */
651
652 up->port[0].mapbase = res->start;
653 up->port[0].membase = ioremap_nocache(up->port[0].mapbase, 0x40);
654 up->port[0].iotype = UPIO_MEM;
655 up->port[0].irq = platform_get_irq(dev, 0);
656
657 up->port[0].dev = &dev->dev;
658
659 sc26xx_init_masks(up, 0, sc26xx_data[0]);
660
661 sc26xx_port = &up->port[0];
662
663 up->port[1].line = 1;
664 up->port[1].ops = &sc26xx_ops;
665 up->port[1].type = PORT_SC26XX;
666 up->port[1].uartclk = (29491200 / 16); /* arbitrary */
667
668 up->port[1].mapbase = up->port[0].mapbase;
669 up->port[1].membase = up->port[0].membase;
670 up->port[1].iotype = UPIO_MEM;
671 up->port[1].irq = up->port[0].irq;
672
673 up->port[1].dev = &dev->dev;
674
675 sc26xx_init_masks(up, 1, sc26xx_data[1]);
676
677 err = uart_register_driver(&sc26xx_reg);
678 if (err)
679 goto out_free_port;
680
681 sc26xx_reg.tty_driver->name_base = sc26xx_reg.minor;
682
683 err = uart_add_one_port(&sc26xx_reg, &up->port[0]);
684 if (err)
685 goto out_unregister_driver;
686
687 err = uart_add_one_port(&sc26xx_reg, &up->port[1]);
688 if (err)
689 goto out_remove_port0;
690
691 err = request_irq(up->port[0].irq, sc26xx_interrupt, 0, "sc26xx", up);
692 if (err)
693 goto out_remove_ports;
694
695 dev_set_drvdata(&dev->dev, up);
696 return 0;
697
698out_remove_ports:
699 uart_remove_one_port(&sc26xx_reg, &up->port[1]);
700out_remove_port0:
701 uart_remove_one_port(&sc26xx_reg, &up->port[0]);
702
703out_unregister_driver:
704 uart_unregister_driver(&sc26xx_reg);
705
706out_free_port:
707 kfree(up);
708 sc26xx_port = NULL;
709 return err;
710}
711
712
713static int __exit sc26xx_driver_remove(struct platform_device *dev)
714{
715 struct uart_sc26xx_port *up = dev_get_drvdata(&dev->dev);
716
717 free_irq(up->port[0].irq, up);
718
719 uart_remove_one_port(&sc26xx_reg, &up->port[0]);
720 uart_remove_one_port(&sc26xx_reg, &up->port[1]);
721
722 uart_unregister_driver(&sc26xx_reg);
723
724 kfree(up);
725 sc26xx_port = NULL;
726
727 dev_set_drvdata(&dev->dev, NULL);
728 return 0;
729}
730
731static struct platform_driver sc26xx_driver = {
732 .probe = sc26xx_probe,
733 .remove = __devexit_p(sc26xx_driver_remove),
734 .driver = {
735 .name = "SC26xx",
Kay Sieverse169c132008-04-15 14:34:35 -0700736 .owner = THIS_MODULE,
Thomas Bogendoerfereea63e02008-02-06 01:37:27 -0800737 },
738};
739
Axel Linc8381c152011-11-28 19:22:15 +0800740module_platform_driver(sc26xx_driver);
Thomas Bogendoerfereea63e02008-02-06 01:37:27 -0800741
742MODULE_AUTHOR("Thomas Bogendörfer");
743MODULE_DESCRIPTION("SC681/SC2692 serial driver");
744MODULE_VERSION("1.0");
745MODULE_LICENSE("GPL");
Kay Sieverse169c132008-04-15 14:34:35 -0700746MODULE_ALIAS("platform:SC26xx");