blob: c442852e65e4975e3d1760593a708570eb4568b4 [file] [log] [blame]
Jon Medhurst221bf152011-04-20 10:52:38 +01001/*
2 * arch/arm/kernel/kprobes.h
3 *
Jon Medhurst0d1a0952011-04-26 15:15:56 +01004 * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
5 *
6 * Some contents moved here from arch/arm/include/asm/kprobes.h which is
Jon Medhurst221bf152011-04-20 10:52:38 +01007 * Copyright (C) 2006, 2007 Motorola Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 */
18
19#ifndef _ARM_KERNEL_KPROBES_H
20#define _ARM_KERNEL_KPROBES_H
21
22/*
Jon Medhurstaceb4872011-04-19 17:18:35 +010023 * These undefined instructions must be unique and
Jon Medhurst221bf152011-04-20 10:52:38 +010024 * reserved solely for kprobes' use.
25 */
Jon Medhurst3b269452011-06-16 17:22:37 +010026#define KPROBE_ARM_BREAKPOINT_INSTRUCTION 0x07f001f8
Jon Medhurstaceb4872011-04-19 17:18:35 +010027#define KPROBE_THUMB16_BREAKPOINT_INSTRUCTION 0xde18
28#define KPROBE_THUMB32_BREAKPOINT_INSTRUCTION 0xf7f0a018
29
Jon Medhurst221bf152011-04-20 10:52:38 +010030
31enum kprobe_insn {
32 INSN_REJECTED,
33 INSN_GOOD,
34 INSN_GOOD_NO_SLOT
35};
36
Jon Medhurst24371702011-04-19 17:56:58 +010037typedef enum kprobe_insn (kprobe_decode_insn_t)(kprobe_opcode_t,
38 struct arch_specific_insn *);
39
40#ifdef CONFIG_THUMB2_KERNEL
41
42enum kprobe_insn thumb16_kprobe_decode_insn(kprobe_opcode_t,
43 struct arch_specific_insn *);
44enum kprobe_insn thumb32_kprobe_decode_insn(kprobe_opcode_t,
45 struct arch_specific_insn *);
46
47#else /* !CONFIG_THUMB2_KERNEL */
48
Jon Medhurst221bf152011-04-20 10:52:38 +010049enum kprobe_insn arm_kprobe_decode_insn(kprobe_opcode_t,
50 struct arch_specific_insn *);
Jon Medhurst24371702011-04-19 17:56:58 +010051#endif
Jon Medhurst221bf152011-04-20 10:52:38 +010052
53void __init arm_kprobe_decode_init(void);
54
Jon Medhurst0ab4c022011-07-06 11:25:18 +010055extern kprobe_check_cc * const kprobe_condition_checks[16];
56
Jon Medhurstaea49022011-07-07 19:58:29 +010057
58#if __LINUX_ARM_ARCH__ >= 7
59
60/* str_pc_offset is architecturally defined from ARMv7 onwards */
61#define str_pc_offset 8
62#define find_str_pc_offset()
63
64#else /* __LINUX_ARM_ARCH__ < 7 */
65
66/* We need a run-time check to determine str_pc_offset */
Jon Medhurst6c8df332011-07-07 10:21:40 +010067extern int str_pc_offset;
Jon Medhurstaea49022011-07-07 19:58:29 +010068void __init find_str_pc_offset(void);
69
70#endif
71
Jon Medhurst6c8df332011-07-07 10:21:40 +010072
Jon Medhurst1b59d872011-07-06 20:33:41 +010073/*
Jon Medhurst6aaa8b52011-06-16 14:53:56 +010074 * Update ITSTATE after normal execution of an IT block instruction.
75 *
76 * The 8 IT state bits are split into two parts in CPSR:
77 * ITSTATE<1:0> are in CPSR<26:25>
78 * ITSTATE<7:2> are in CPSR<15:10>
79 */
80static inline unsigned long it_advance(unsigned long cpsr)
81 {
82 if ((cpsr & 0x06000400) == 0) {
83 /* ITSTATE<2:0> == 0 means end of IT block, so clear IT state */
84 cpsr &= ~PSR_IT_MASK;
85 } else {
86 /* We need to shift left ITSTATE<4:0> */
87 const unsigned long mask = 0x06001c00; /* Mask ITSTATE<4:0> */
88 unsigned long it = cpsr & mask;
89 it <<= 1;
90 it |= it >> (27 - 10); /* Carry ITSTATE<2> to correct place */
91 it &= mask;
92 cpsr &= ~mask;
93 cpsr |= it;
94 }
95 return cpsr;
96}
97
Jon Medhurst059987f2011-06-09 11:01:54 +010098static inline void __kprobes bx_write_pc(long pcv, struct pt_regs *regs)
99{
100 long cpsr = regs->ARM_cpsr;
101 if (pcv & 0x1) {
102 cpsr |= PSR_T_BIT;
103 pcv &= ~0x1;
104 } else {
105 cpsr &= ~PSR_T_BIT;
106 pcv &= ~0x2; /* Avoid UNPREDICTABLE address allignment */
107 }
108 regs->ARM_cpsr = cpsr;
109 regs->ARM_pc = pcv;
110}
111
Jon Medhurst263e3682011-06-10 20:29:04 +0100112
113#if __LINUX_ARM_ARCH__ >= 6
114
115/* Kernels built for >= ARMv6 should never run on <= ARMv5 hardware, so... */
116#define load_write_pc_interworks true
117#define test_load_write_pc_interworking()
118
119#else /* __LINUX_ARM_ARCH__ < 6 */
120
121/* We need run-time testing to determine if load_write_pc() should interwork. */
122extern bool load_write_pc_interworks;
123void __init test_load_write_pc_interworking(void);
124
125#endif
126
127static inline void __kprobes load_write_pc(long pcv, struct pt_regs *regs)
128{
129 if (load_write_pc_interworks)
130 bx_write_pc(pcv, regs);
131 else
132 regs->ARM_pc = pcv;
133}
134
135
Jon Medhurst3f92dfe2011-07-02 15:36:32 +0100136void __kprobes kprobe_simulate_nop(struct kprobe *p, struct pt_regs *regs);
137void __kprobes kprobe_emulate_none(struct kprobe *p, struct pt_regs *regs);
138
Jon Medhurst235a4ce2011-07-07 08:57:22 +0100139enum kprobe_insn __kprobes
140kprobe_decode_ldmstm(kprobe_opcode_t insn, struct arch_specific_insn *asi);
141
Jon Medhurst6aaa8b52011-06-16 14:53:56 +0100142/*
Jon Medhurst1b59d872011-07-06 20:33:41 +0100143 * Test if load/store instructions writeback the address register.
144 * if P (bit 24) == 0 or W (bit 21) == 1
145 */
146#define is_writeback(insn) ((insn ^ 0x01000000) & 0x01200000)
147
Jon Medhurst0d1a0952011-04-26 15:15:56 +0100148/*
149 * The following definitions and macros are used to build instruction
150 * decoding tables for use by kprobe_decode_insn.
151 *
152 * These tables are a concatenation of entries each of which consist of one of
153 * the decode_* structs. All of the fields in every type of decode structure
154 * are of the union type decode_item, therefore the entire decode table can be
155 * viewed as an array of these and declared like:
156 *
157 * static const union decode_item table_name[] = {};
158 *
159 * In order to construct each entry in the table, macros are used to
160 * initialise a number of sequential decode_item values in a layout which
161 * matches the relevant struct. E.g. DECODE_SIMULATE initialise a struct
162 * decode_simulate by initialising four decode_item objects like this...
163 *
164 * {.bits = _type},
165 * {.bits = _mask},
166 * {.bits = _value},
167 * {.handler = _handler},
168 *
169 * Initialising a specified member of the union means that the compiler
170 * will produce a warning if the argument is of an incorrect type.
171 *
172 * Below is a list of each of the macros used to initialise entries and a
173 * description of the action performed when that entry is matched to an
174 * instruction. A match is found when (instruction & mask) == value.
175 *
176 * DECODE_TABLE(mask, value, table)
177 * Instruction decoding jumps to parsing the new sub-table 'table'.
178 *
179 * DECODE_CUSTOM(mask, value, decoder)
180 * The custom function 'decoder' is called to the complete decoding
181 * of an instruction.
182 *
183 * DECODE_SIMULATE(mask, value, handler)
184 * Set the probes instruction handler to 'handler', this will be used
185 * to simulate the instruction when the probe is hit. Decoding returns
186 * with INSN_GOOD_NO_SLOT.
187 *
188 * DECODE_EMULATE(mask, value, handler)
189 * Set the probes instruction handler to 'handler', this will be used
190 * to emulate the instruction when the probe is hit. The modified
191 * instruction (see below) is placed in the probes instruction slot so it
192 * may be called by the emulation code. Decoding returns with INSN_GOOD.
193 *
194 * DECODE_REJECT(mask, value)
195 * Instruction decoding fails with INSN_REJECTED
196 *
197 * DECODE_OR(mask, value)
198 * This allows the mask/value test of multiple table entries to be
199 * logically ORed. Once an 'or' entry is matched the decoding action to
200 * be performed is that of the next entry which isn't an 'or'. E.g.
201 *
202 * DECODE_OR (mask1, value1)
203 * DECODE_OR (mask2, value2)
204 * DECODE_SIMULATE (mask3, value3, simulation_handler)
205 *
206 * This means that if any of the three mask/value pairs match the
207 * instruction being decoded, then 'simulation_handler' will be used
208 * for it.
209 *
210 * Both the SIMULATE and EMULATE macros have a second form which take an
211 * additional 'regs' argument.
212 *
213 * DECODE_SIMULATEX(mask, value, handler, regs)
214 * DECODE_EMULATEX (mask, value, handler, regs)
215 *
216 * These are used to specify what kind of CPU register is encoded in each of the
217 * least significant 5 nibbles of the instruction being decoded. The regs value
218 * is specified using the REGS macro, this takes any of the REG_TYPE_* values
219 * from enum decode_reg_type as arguments; only the '*' part of the name is
220 * given. E.g.
221 *
222 * REGS(0, ANY, NOPC, 0, ANY)
223 *
224 * This indicates an instruction is encoded like:
225 *
226 * bits 19..16 ignore
227 * bits 15..12 any register allowed here
228 * bits 11.. 8 any register except PC allowed here
229 * bits 7.. 4 ignore
230 * bits 3.. 0 any register allowed here
231 *
232 * This register specification is checked after a decode table entry is found to
233 * match an instruction (through the mask/value test). Any invalid register then
234 * found in the instruction will cause decoding to fail with INSN_REJECTED. In
235 * the above example this would happen if bits 11..8 of the instruction were
236 * 1111, indicating R15 or PC.
237 *
238 * As well as checking for legal combinations of registers, this data is also
239 * used to modify the registers encoded in the instructions so that an
240 * emulation routines can use it. (See decode_regs() and INSN_NEW_BITS.)
241 *
242 * Here is a real example which matches ARM instructions of the form
243 * "AND <Rd>,<Rn>,<Rm>,<shift> <Rs>"
244 *
245 * DECODE_EMULATEX (0x0e000090, 0x00000010, emulate_rd12rn16rm0rs8_rwflags,
246 * REGS(ANY, ANY, NOPC, 0, ANY)),
247 * ^ ^ ^ ^
248 * Rn Rd Rs Rm
249 *
250 * Decoding the instruction "AND R4, R5, R6, ASL R15" will be rejected because
251 * Rs == R15
252 *
253 * Decoding the instruction "AND R4, R5, R6, ASL R7" will be accepted and the
254 * instruction will be modified to "AND R0, R2, R3, ASL R1" and then placed into
255 * the kprobes instruction slot. This can then be called later by the handler
256 * function emulate_rd12rn16rm0rs8_rwflags in order to simulate the instruction.
257 */
258
259enum decode_type {
260 DECODE_TYPE_END,
261 DECODE_TYPE_TABLE,
262 DECODE_TYPE_CUSTOM,
263 DECODE_TYPE_SIMULATE,
264 DECODE_TYPE_EMULATE,
265 DECODE_TYPE_OR,
266 DECODE_TYPE_REJECT,
267 NUM_DECODE_TYPES /* Must be last enum */
268};
269
270#define DECODE_TYPE_BITS 4
271#define DECODE_TYPE_MASK ((1 << DECODE_TYPE_BITS) - 1)
272
273enum decode_reg_type {
274 REG_TYPE_NONE = 0, /* Not a register, ignore */
275 REG_TYPE_ANY, /* Any register allowed */
276 REG_TYPE_SAMEAS16, /* Register should be same as that at bits 19..16 */
277 REG_TYPE_SP, /* Register must be SP */
278 REG_TYPE_PC, /* Register must be PC */
279 REG_TYPE_NOSP, /* Register must not be SP */
280 REG_TYPE_NOSPPC, /* Register must not be SP or PC */
281 REG_TYPE_NOPC, /* Register must not be PC */
282 REG_TYPE_NOPCWB, /* No PC if load/store write-back flag also set */
283
284 /* The following types are used when the encoding for PC indicates
285 * another instruction form. This distiction only matters for test
286 * case coverage checks.
287 */
288 REG_TYPE_NOPCX, /* Register must not be PC */
289 REG_TYPE_NOSPPCX, /* Register must not be SP or PC */
290
291 /* Alias to allow '0' arg to be used in REGS macro. */
292 REG_TYPE_0 = REG_TYPE_NONE
293};
294
295#define REGS(r16, r12, r8, r4, r0) \
296 ((REG_TYPE_##r16) << 16) + \
297 ((REG_TYPE_##r12) << 12) + \
298 ((REG_TYPE_##r8) << 8) + \
299 ((REG_TYPE_##r4) << 4) + \
300 (REG_TYPE_##r0)
301
302union decode_item {
303 u32 bits;
304 const union decode_item *table;
305 kprobe_insn_handler_t *handler;
306 kprobe_decode_insn_t *decoder;
307};
308
309
310#define DECODE_END \
311 {.bits = DECODE_TYPE_END}
312
313
314struct decode_header {
315 union decode_item type_regs;
316 union decode_item mask;
317 union decode_item value;
318};
319
320#define DECODE_HEADER(_type, _mask, _value, _regs) \
321 {.bits = (_type) | ((_regs) << DECODE_TYPE_BITS)}, \
322 {.bits = (_mask)}, \
323 {.bits = (_value)}
324
325
326struct decode_table {
327 struct decode_header header;
328 union decode_item table;
329};
330
331#define DECODE_TABLE(_mask, _value, _table) \
332 DECODE_HEADER(DECODE_TYPE_TABLE, _mask, _value, 0), \
333 {.table = (_table)}
334
335
336struct decode_custom {
337 struct decode_header header;
338 union decode_item decoder;
339};
340
341#define DECODE_CUSTOM(_mask, _value, _decoder) \
342 DECODE_HEADER(DECODE_TYPE_CUSTOM, _mask, _value, 0), \
343 {.decoder = (_decoder)}
344
345
346struct decode_simulate {
347 struct decode_header header;
348 union decode_item handler;
349};
350
351#define DECODE_SIMULATEX(_mask, _value, _handler, _regs) \
352 DECODE_HEADER(DECODE_TYPE_SIMULATE, _mask, _value, _regs), \
353 {.handler = (_handler)}
354
355#define DECODE_SIMULATE(_mask, _value, _handler) \
356 DECODE_SIMULATEX(_mask, _value, _handler, 0)
357
358
359struct decode_emulate {
360 struct decode_header header;
361 union decode_item handler;
362};
363
364#define DECODE_EMULATEX(_mask, _value, _handler, _regs) \
365 DECODE_HEADER(DECODE_TYPE_EMULATE, _mask, _value, _regs), \
366 {.handler = (_handler)}
367
368#define DECODE_EMULATE(_mask, _value, _handler) \
369 DECODE_EMULATEX(_mask, _value, _handler, 0)
370
371
372struct decode_or {
373 struct decode_header header;
374};
375
376#define DECODE_OR(_mask, _value) \
377 DECODE_HEADER(DECODE_TYPE_OR, _mask, _value, 0)
378
379
380struct decode_reject {
381 struct decode_header header;
382};
383
384#define DECODE_REJECT(_mask, _value) \
385 DECODE_HEADER(DECODE_TYPE_REJECT, _mask, _value, 0)
386
387
388int kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi,
389 const union decode_item *table, bool thumb16);
390
391
Jon Medhurst221bf152011-04-20 10:52:38 +0100392#endif /* _ARM_KERNEL_KPROBES_H */