Blame - drivers/gpu/drm/radeon/evergreend.h - android_kernel_oneplus_msm8996

2010-03-24 13:20:41 -0400

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/*

*

* Permission is hereby granted, free of charge, to any person obtaining a

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* copy of this software and associated documentation files (the "Software"),

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* to deal in the Software without restriction, including without limitation

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* the rights to use, copy, modify, merge, publish, distribute, sublicense,

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* and/or sell copies of the Software, and to permit persons to whom the

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* Software is furnished to do so, subject to the following conditions:

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*

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* The above copyright notice and this permission notice shall be included in

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* all copies or substantial portions of the Software.

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*

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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

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* OTHER DEALINGS IN THE SOFTWARE.

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*

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* Authors: Alex Deucher

*/

#ifndef EVERGREEND_H

#define EVERGREEND_H

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#define EVERGREEN_MAX_SH_GPRS 256

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#define EVERGREEN_MAX_TEMP_GPRS 16

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#define EVERGREEN_MAX_SH_THREADS 256

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#define EVERGREEN_MAX_SH_STACK_ENTRIES 4096

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#define EVERGREEN_MAX_FRC_EOV_CNT 16384

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#define EVERGREEN_MAX_BACKENDS 8

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#define EVERGREEN_MAX_BACKENDS_MASK 0xFF

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#define EVERGREEN_MAX_SIMDS 16

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#define EVERGREEN_MAX_SIMDS_MASK 0xFFFF

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#define EVERGREEN_MAX_PIPES 8

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#define EVERGREEN_MAX_PIPES_MASK 0xFF

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#define EVERGREEN_MAX_LDS_NUM 0xFFFF

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#define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003

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#define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003

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#define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003

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#define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002

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#define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002

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#define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002

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#define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001

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#define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001

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#define SUMO_GB_ADDR_CONFIG_GOLDEN 0x02010002

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#define SUMO2_GB_ADDR_CONFIG_GOLDEN 0x02010002

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Alex Deucher

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/* Registers */

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#define RCU_IND_INDEX 0x100

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#define RCU_IND_DATA 0x104

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Alex Deucher

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/* fusion uvd clocks */

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#define CG_DCLK_CNTL 0x610

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# define DCLK_DIVIDER_MASK 0x7f

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# define DCLK_DIR_CNTL_EN (1 << 8)

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#define CG_DCLK_STATUS 0x614

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# define DCLK_STATUS (1 << 0)

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#define CG_VCLK_CNTL 0x618

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#define CG_VCLK_STATUS 0x61c

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#define CG_SCRATCH1 0x820

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#define GRBM_GFX_INDEX 0x802C

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#define INSTANCE_INDEX(x) ((x) << 0)

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#define SE_INDEX(x) ((x) << 16)

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#define INSTANCE_BROADCAST_WRITES (1 << 30)

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#define SE_BROADCAST_WRITES (1 << 31)

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#define RLC_GFX_INDEX 0x3fC4

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#define CC_GC_SHADER_PIPE_CONFIG 0x8950

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#define WRITE_DIS (1 << 0)

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#define CC_RB_BACKEND_DISABLE 0x98F4

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#define BACKEND_DISABLE(x) ((x) << 16)

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#define GB_ADDR_CONFIG 0x98F8

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#define NUM_PIPES(x) ((x) << 0)

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#define NUM_PIPES_MASK 0x0000000f

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#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)

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#define BANK_INTERLEAVE_SIZE(x) ((x) << 8)

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#define NUM_SHADER_ENGINES(x) ((x) << 12)

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#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)

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#define NUM_GPUS(x) ((x) << 20)

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#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)

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#define ROW_SIZE(x) ((x) << 28)

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#define GB_BACKEND_MAP 0x98FC

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#define DMIF_ADDR_CONFIG 0xBD4

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#define HDP_ADDR_CONFIG 0x2F48

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#define HDP_MISC_CNTL 0x2F4C

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#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)

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#define CC_SYS_RB_BACKEND_DISABLE 0x3F88

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#define GC_USER_RB_BACKEND_DISABLE 0x9B7C

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#define CGTS_SYS_TCC_DISABLE 0x3F90

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#define CGTS_TCC_DISABLE 0x9148

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#define CGTS_USER_SYS_TCC_DISABLE 0x3F94

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#define CGTS_USER_TCC_DISABLE 0x914C

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#define CONFIG_MEMSIZE 0x5428

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#define BIF_FB_EN 0x5490

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#define FB_READ_EN (1 << 0)

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#define FB_WRITE_EN (1 << 1)

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#define CP_STRMOUT_CNTL 0x84FC

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#define CP_COHER_CNTL 0x85F0

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#define CP_COHER_SIZE 0x85F4

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#define CP_COHER_BASE 0x85F8

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#define CP_STALLED_STAT1 0x8674

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#define CP_STALLED_STAT2 0x8678

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#define CP_BUSY_STAT 0x867C

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#define CP_STAT 0x8680

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#define CP_ME_CNTL 0x86D8

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#define CP_ME_HALT (1 << 28)

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#define CP_PFP_HALT (1 << 26)

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#define CP_ME_RAM_DATA 0xC160

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#define CP_ME_RAM_RADDR 0xC158

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#define CP_ME_RAM_WADDR 0xC15C

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#define CP_MEQ_THRESHOLDS 0x8764

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#define STQ_SPLIT(x) ((x) << 0)

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#define CP_PERFMON_CNTL 0x87FC

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#define CP_PFP_UCODE_ADDR 0xC150

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#define CP_PFP_UCODE_DATA 0xC154

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#define CP_QUEUE_THRESHOLDS 0x8760

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#define ROQ_IB1_START(x) ((x) << 0)

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#define ROQ_IB2_START(x) ((x) << 8)

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#define CP_RB_BASE 0xC100

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#define CP_RB_CNTL 0xC104

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#define RB_BUFSZ(x) ((x) << 0)

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#define RB_BLKSZ(x) ((x) << 8)

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#define RB_NO_UPDATE (1 << 27)

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#define RB_RPTR_WR_ENA (1 << 31)

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#define BUF_SWAP_32BIT (2 << 16)

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#define CP_RB_RPTR 0x8700

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#define CP_RB_RPTR_ADDR 0xC10C

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#define RB_RPTR_SWAP(x) ((x) << 0)

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#define CP_RB_RPTR_ADDR_HI 0xC110

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#define CP_RB_RPTR_WR 0xC108

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#define CP_RB_WPTR 0xC114

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#define CP_RB_WPTR_ADDR 0xC118

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#define CP_RB_WPTR_ADDR_HI 0xC11C

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#define CP_RB_WPTR_DELAY 0x8704

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#define CP_SEM_WAIT_TIMER 0x85BC

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#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8

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#define CP_DEBUG 0xC1FC

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/* Audio clocks */

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#define DCCG_AUDIO_DTO_SOURCE 0x05ac

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# define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */

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# define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */

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#define DCCG_AUDIO_DTO0_PHASE 0x05b0

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#define DCCG_AUDIO_DTO0_MODULE 0x05b4

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#define DCCG_AUDIO_DTO0_LOAD 0x05b8

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#define DCCG_AUDIO_DTO0_CNTL 0x05bc

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#define DCCG_AUDIO_DTO1_PHASE 0x05c0

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#define DCCG_AUDIO_DTO1_MODULE 0x05c4

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#define DCCG_AUDIO_DTO1_LOAD 0x05c8

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#define DCCG_AUDIO_DTO1_CNTL 0x05cc

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/* DCE 4.0 AFMT */

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#define HDMI_CONTROL 0x7030

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# define HDMI_KEEPOUT_MODE (1 << 0)

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# define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */

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# define HDMI_ERROR_ACK (1 << 8)

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# define HDMI_ERROR_MASK (1 << 9)

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# define HDMI_DEEP_COLOR_ENABLE (1 << 24)

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# define HDMI_DEEP_COLOR_DEPTH (((x) & 3) << 28)

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# define HDMI_24BIT_DEEP_COLOR 0

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# define HDMI_30BIT_DEEP_COLOR 1

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# define HDMI_36BIT_DEEP_COLOR 2

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#define HDMI_STATUS 0x7034

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# define HDMI_ACTIVE_AVMUTE (1 << 0)

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# define HDMI_AUDIO_PACKET_ERROR (1 << 16)

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# define HDMI_VBI_PACKET_ERROR (1 << 20)

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#define HDMI_AUDIO_PACKET_CONTROL 0x7038

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# define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4)

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# define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16)

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#define HDMI_ACR_PACKET_CONTROL 0x703c

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# define HDMI_ACR_SEND (1 << 0)

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# define HDMI_ACR_CONT (1 << 1)

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# define HDMI_ACR_SELECT(x) (((x) & 3) << 4)

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# define HDMI_ACR_HW 0

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# define HDMI_ACR_32 1

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# define HDMI_ACR_44 2

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# define HDMI_ACR_48 3

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# define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */

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# define HDMI_ACR_AUTO_SEND (1 << 12)

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# define HDMI_ACR_N_MULTIPLE(x) (((x) & 7) << 16)

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# define HDMI_ACR_X1 1

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# define HDMI_ACR_X2 2

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# define HDMI_ACR_X4 4

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# define HDMI_ACR_AUDIO_PRIORITY (1 << 31)

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#define HDMI_VBI_PACKET_CONTROL 0x7040

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# define HDMI_NULL_SEND (1 << 0)

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# define HDMI_GC_SEND (1 << 4)

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# define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */

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#define HDMI_INFOFRAME_CONTROL0 0x7044

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# define HDMI_AVI_INFO_SEND (1 << 0)

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# define HDMI_AVI_INFO_CONT (1 << 1)

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# define HDMI_AUDIO_INFO_SEND (1 << 4)

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# define HDMI_AUDIO_INFO_CONT (1 << 5)

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# define HDMI_MPEG_INFO_SEND (1 << 8)

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# define HDMI_MPEG_INFO_CONT (1 << 9)

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#define HDMI_INFOFRAME_CONTROL1 0x7048

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# define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)

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# define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)

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# define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)

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#define HDMI_GENERIC_PACKET_CONTROL 0x704c

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# define HDMI_GENERIC0_SEND (1 << 0)

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# define HDMI_GENERIC0_CONT (1 << 1)

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# define HDMI_GENERIC1_SEND (1 << 4)

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# define HDMI_GENERIC1_CONT (1 << 5)

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# define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16)

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# define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24)

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#define HDMI_GC 0x7058

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# define HDMI_GC_AVMUTE (1 << 0)

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# define HDMI_GC_AVMUTE_CONT (1 << 2)

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#define AFMT_AUDIO_PACKET_CONTROL2 0x705c

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# define AFMT_AUDIO_LAYOUT_OVRD (1 << 0)

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# define AFMT_AUDIO_LAYOUT_SELECT (1 << 1)

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# define AFMT_60958_CS_SOURCE (1 << 4)

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# define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8)

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# define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16)

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#define AFMT_AVI_INFO0 0x7084

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# define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0)

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# define AFMT_AVI_INFO_S(x) (((x) & 3) << 8)

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# define AFMT_AVI_INFO_B(x) (((x) & 3) << 10)

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# define AFMT_AVI_INFO_A(x) (((x) & 1) << 12)

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# define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13)

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# define AFMT_AVI_INFO_Y_RGB 0

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# define AFMT_AVI_INFO_Y_YCBCR422 1

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# define AFMT_AVI_INFO_Y_YCBCR444 2

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# define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8)

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# define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16)

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# define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20)

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# define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22)

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# define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16)

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# define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24)

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# define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26)

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# define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28)

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# define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31)

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# define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24)

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#define AFMT_AVI_INFO1 0x7088

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# define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */

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# define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */

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# define AFMT_AVI_INFO_CN(x) (((x) & 0x3) << 12)

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# define AFMT_AVI_INFO_YQ(x) (((x) & 0x3) << 14)

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# define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16)

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#define AFMT_AVI_INFO2 0x708c

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# define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0)

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# define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16)

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#define AFMT_AVI_INFO3 0x7090

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# define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0)

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# define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24)

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#define AFMT_MPEG_INFO0 0x7094

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# define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0)

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# define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8)

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# define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16)

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# define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24)

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#define AFMT_MPEG_INFO1 0x7098

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# define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0)

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# define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8)

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# define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12)

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#define AFMT_GENERIC0_HDR 0x709c

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#define AFMT_GENERIC0_0 0x70a0

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#define AFMT_GENERIC0_1 0x70a4

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#define AFMT_GENERIC0_2 0x70a8

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#define AFMT_GENERIC0_3 0x70ac

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#define AFMT_GENERIC0_4 0x70b0

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#define AFMT_GENERIC0_5 0x70b4

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#define AFMT_GENERIC0_6 0x70b8

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#define AFMT_GENERIC1_HDR 0x70bc

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#define AFMT_GENERIC1_0 0x70c0

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#define AFMT_GENERIC1_1 0x70c4

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#define AFMT_GENERIC1_2 0x70c8

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#define AFMT_GENERIC1_3 0x70cc

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#define AFMT_GENERIC1_4 0x70d0

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#define AFMT_GENERIC1_5 0x70d4

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#define AFMT_GENERIC1_6 0x70d8

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#define HDMI_ACR_32_0 0x70dc

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# define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12)

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#define HDMI_ACR_32_1 0x70e0

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# define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0)

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#define HDMI_ACR_44_0 0x70e4

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# define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12)

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#define HDMI_ACR_44_1 0x70e8

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# define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0)

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#define HDMI_ACR_48_0 0x70ec

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# define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12)

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#define HDMI_ACR_48_1 0x70f0

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# define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0)

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#define HDMI_ACR_STATUS_0 0x70f4

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#define HDMI_ACR_STATUS_1 0x70f8

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#define AFMT_AUDIO_INFO0 0x70fc

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# define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0)

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# define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8)

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# define AFMT_AUDIO_INFO_CT(x) (((x) & 0xf) << 11)

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# define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16)

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# define AFMT_AUDIO_INFO_CXT(x) (((x) & 0x1f) << 24)

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#define AFMT_AUDIO_INFO1 0x7100

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# define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0)

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# define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11)

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# define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15)

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# define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)

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# define AFMT_AUDIO_INFO_LFEBPL(x) (((x) & 3) << 16)

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#define AFMT_60958_0 0x7104

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# define AFMT_60958_CS_A(x) (((x) & 1) << 0)

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# define AFMT_60958_CS_B(x) (((x) & 1) << 1)

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# define AFMT_60958_CS_C(x) (((x) & 1) << 2)

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# define AFMT_60958_CS_D(x) (((x) & 3) << 3)

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# define AFMT_60958_CS_MODE(x) (((x) & 3) << 6)

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# define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8)

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# define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16)

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# define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20)

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# define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)

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# define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28)

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#define AFMT_60958_1 0x7108

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# define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0)

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# define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4)

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# define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16)

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# define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18)

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# define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20)

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#define AFMT_AUDIO_CRC_CONTROL 0x710c

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# define AFMT_AUDIO_CRC_EN (1 << 0)

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#define AFMT_RAMP_CONTROL0 0x7110

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# define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)

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# define AFMT_RAMP_DATA_SIGN (1 << 31)

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#define AFMT_RAMP_CONTROL1 0x7114

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# define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)

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# define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24)

335

#define AFMT_RAMP_CONTROL2 0x7118

336

# define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0)

337

#define AFMT_RAMP_CONTROL3 0x711c

338

# define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0)

339

#define AFMT_60958_2 0x7120

340

# define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0)

341

# define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4)

342

# define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8)

343

# define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12)

344

# define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16)

345

# define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20)

346

#define AFMT_STATUS 0x7128

347

# define AFMT_AUDIO_ENABLE (1 << 4)

348

# define AFMT_AUDIO_HBR_ENABLE (1 << 8)

349

# define AFMT_AZ_FORMAT_WTRIG (1 << 28)

350

# define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29)

351

# define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30)

352

#define AFMT_AUDIO_PACKET_CONTROL 0x712c

353

# define AFMT_AUDIO_SAMPLE_SEND (1 << 0)

354

# define AFMT_RESET_FIFO_WHEN_AUDIO_DIS (1 << 11) /* set to 1 */

355

# define AFMT_AUDIO_TEST_EN (1 << 12)

356

# define AFMT_AUDIO_CHANNEL_SWAP (1 << 24)

357

# define AFMT_60958_CS_UPDATE (1 << 26)

358

# define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)

359

# define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28)

360

# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)

361

# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)

362

#define AFMT_VBI_PACKET_CONTROL 0x7130

363

# define AFMT_GENERIC0_UPDATE (1 << 2)

364

#define AFMT_INFOFRAME_CONTROL0 0x7134

365

# define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - afmt regs */

366

# define AFMT_AUDIO_INFO_UPDATE (1 << 7)

367

# define AFMT_MPEG_INFO_UPDATE (1 << 10)

368

#define AFMT_GENERIC0_7 0x7138

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

369

Alex Deucher

1c4c3a9

2012-12-03 11:59:21 -0500

[diff] [blame]

370

/* DCE4/5 ELD audio interface */

371

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x5f84 /* LPCM */

372

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x5f88 /* AC3 */

373

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x5f8c /* MPEG1 */

374

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x5f90 /* MP3 */

375

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x5f94 /* MPEG2 */

376

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x5f98 /* AAC */

377

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x5f9c /* DTS */

378

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x5fa0 /* ATRAC */

379

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x5fa4 /* one bit audio - leave at 0 (default) */

380

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x5fa8 /* Dolby Digital */

381

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x5fac /* DTS-HD */

382

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x5fb0 /* MAT-MLP */

383

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x5fb4 /* DTS */

384

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x5fb8 /* WMA Pro */

385

# define MAX_CHANNELS(x) (((x) & 0x7) << 0)

386

/* max channels minus one. 7 = 8 channels */

387

# define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)

388

# define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)

389

# define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */

390

/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO

* bit0 = 32 kHz

* bit1 = 44.1 kHz

* bit2 = 48 kHz

* bit3 = 88.2 kHz

* bit4 = 96 kHz

* bit5 = 176.4 kHz

* bit6 = 192 kHz

*/

#define AZ_HOT_PLUG_CONTROL 0x5e78

401

# define AZ_FORCE_CODEC_WAKE (1 << 0)

402

# define PIN0_JACK_DETECTION_ENABLE (1 << 4)

403

# define PIN1_JACK_DETECTION_ENABLE (1 << 5)

404

# define PIN2_JACK_DETECTION_ENABLE (1 << 6)

405

# define PIN3_JACK_DETECTION_ENABLE (1 << 7)

406

# define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8)

407

# define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9)

408

# define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10)

409

# define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11)

410

# define CODEC_HOT_PLUG_ENABLE (1 << 12)

411

# define PIN0_AUDIO_ENABLED (1 << 24)

412

# define PIN1_AUDIO_ENABLED (1 << 25)

413

# define PIN2_AUDIO_ENABLED (1 << 26)

414

# define PIN3_AUDIO_ENABLED (1 << 27)

415

# define AUDIO_ENABLED (1 << 31)

416

417

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

418

#define GC_USER_SHADER_PIPE_CONFIG 0x8954

419

#define INACTIVE_QD_PIPES(x) ((x) << 8)

420

#define INACTIVE_QD_PIPES_MASK 0x0000FF00

421

#define INACTIVE_SIMDS(x) ((x) << 16)

422

#define INACTIVE_SIMDS_MASK 0x00FF0000

423

424

#define GRBM_CNTL 0x8000

425

#define GRBM_READ_TIMEOUT(x) ((x) << 0)

426

#define GRBM_SOFT_RESET 0x8020

Alex Deucher

2010-03-24 13:26:36 -0400

[diff] [blame]

427

#define SOFT_RESET_CP (1 << 0)

428

#define SOFT_RESET_CB (1 << 1)

429

#define SOFT_RESET_DB (1 << 3)

430

#define SOFT_RESET_PA (1 << 5)

431

#define SOFT_RESET_SC (1 << 6)

432

#define SOFT_RESET_SPI (1 << 8)

433

#define SOFT_RESET_SH (1 << 9)

434

#define SOFT_RESET_SX (1 << 10)

435

#define SOFT_RESET_TC (1 << 11)

436

#define SOFT_RESET_TA (1 << 12)

437

#define SOFT_RESET_VC (1 << 13)

438

#define SOFT_RESET_VGT (1 << 14)

439

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

440

#define GRBM_STATUS 0x8010

441

#define CMDFIFO_AVAIL_MASK 0x0000000F

Alex Deucher

2010-03-24 13:26:36 -0400

[diff] [blame]

442

#define SRBM_RQ_PENDING (1 << 5)

443

#define CF_RQ_PENDING (1 << 7)

444

#define PF_RQ_PENDING (1 << 8)

445

#define GRBM_EE_BUSY (1 << 10)

446

#define SX_CLEAN (1 << 11)

447

#define DB_CLEAN (1 << 12)

448

#define CB_CLEAN (1 << 13)

449

#define TA_BUSY (1 << 14)

450

#define VGT_BUSY_NO_DMA (1 << 16)

451

#define VGT_BUSY (1 << 17)

452

#define SX_BUSY (1 << 20)

453

#define SH_BUSY (1 << 21)

454

#define SPI_BUSY (1 << 22)

455

#define SC_BUSY (1 << 24)

456

#define PA_BUSY (1 << 25)

457

#define DB_BUSY (1 << 26)

458

#define CP_COHERENCY_BUSY (1 << 28)

459

#define CP_BUSY (1 << 29)

460

#define CB_BUSY (1 << 30)

461

#define GUI_ACTIVE (1 << 31)

462

#define GRBM_STATUS_SE0 0x8014

463

#define GRBM_STATUS_SE1 0x8018

464

#define SE_SX_CLEAN (1 << 0)

465

#define SE_DB_CLEAN (1 << 1)

466

#define SE_CB_CLEAN (1 << 2)

467

#define SE_TA_BUSY (1 << 25)

468

#define SE_SX_BUSY (1 << 26)

469

#define SE_SPI_BUSY (1 << 27)

470

#define SE_SH_BUSY (1 << 28)

471

#define SE_SC_BUSY (1 << 29)

472

#define SE_DB_BUSY (1 << 30)

473

#define SE_CB_BUSY (1 << 31)

Alex Deucher

e33df25

2010-11-22 17:56:32 -0500

[diff] [blame]

474

/* evergreen */

Alex Deucher

67b3f82

2011-05-25 18:45:37 -0400

[diff] [blame]

475

#define CG_THERMAL_CTRL 0x72c

476

#define TOFFSET_MASK 0x00003FE0

477

#define TOFFSET_SHIFT 5

Alex Deucher

21a8122

2010-07-02 12:58:16 -0400

[diff] [blame]

478

#define CG_MULT_THERMAL_STATUS 0x740

479

#define ASIC_T(x) ((x) << 16)

Alex Deucher

67b3f82

2011-05-25 18:45:37 -0400

[diff] [blame]

480

#define ASIC_T_MASK 0x07FF0000

Alex Deucher

21a8122

2010-07-02 12:58:16 -0400

[diff] [blame]

481

#define ASIC_T_SHIFT 16

Alex Deucher

67b3f82

2011-05-25 18:45:37 -0400

[diff] [blame]

482

#define CG_TS0_STATUS 0x760

483

#define TS0_ADC_DOUT_MASK 0x000003FF

484

#define TS0_ADC_DOUT_SHIFT 0

Alex Deucher

e33df25

2010-11-22 17:56:32 -0500

[diff] [blame]

485

/* APU */

486

#define CG_THERMAL_STATUS 0x678

Alex Deucher

21a8122

2010-07-02 12:58:16 -0400

[diff] [blame]

487

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

488

#define HDP_HOST_PATH_CNTL 0x2C00

489

#define HDP_NONSURFACE_BASE 0x2C04

490

#define HDP_NONSURFACE_INFO 0x2C08

491

#define HDP_NONSURFACE_SIZE 0x2C0C

Alex Deucher

6f2f48a

2010-12-15 11:01:56 -0500

[diff] [blame]

492

#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

493

#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0

494

#define HDP_TILING_CONFIG 0x2F3C

495

496

#define MC_SHARED_CHMAP 0x2004

497

#define NOOFCHAN_SHIFT 12

498

#define NOOFCHAN_MASK 0x00003000

Alex Deucher

9535ab7

2010-11-22 17:56:18 -0500

[diff] [blame]

499

#define MC_SHARED_CHREMAP 0x2008

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

500

Alex Deucher

62444b7

2012-08-15 17:18:42 -0400

[diff] [blame]

501

#define MC_SHARED_BLACKOUT_CNTL 0x20ac

502

#define BLACKOUT_MODE_MASK 0x00000007

503

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

504

#define MC_ARB_RAMCFG 0x2760

505

#define NOOFBANK_SHIFT 0

506

#define NOOFBANK_MASK 0x00000003

507

#define NOOFRANK_SHIFT 2

508

#define NOOFRANK_MASK 0x00000004

509

#define NOOFROWS_SHIFT 3

510

#define NOOFROWS_MASK 0x00000038

511

#define NOOFCOLS_SHIFT 6

512

#define NOOFCOLS_MASK 0x000000C0

513

#define CHANSIZE_SHIFT 8

514

#define CHANSIZE_MASK 0x00000100

515

#define BURSTLENGTH_SHIFT 9

516

#define BURSTLENGTH_MASK 0x00000200

517

#define CHANSIZE_OVERRIDE (1 << 11)

Alex Deucher

d9282fc

2011-05-11 03:15:24 -0400

[diff] [blame]

518

#define FUS_MC_ARB_RAMCFG 0x2768

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

519

#define MC_VM_AGP_TOP 0x2028

520

#define MC_VM_AGP_BOT 0x202C

521

#define MC_VM_AGP_BASE 0x2030

522

#define MC_VM_FB_LOCATION 0x2024

Alex Deucher

b4183e3

2010-12-15 11:04:10 -0500

[diff] [blame]

523

#define MC_FUS_VM_FB_OFFSET 0x2898

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

524

#define MC_VM_MB_L1_TLB0_CNTL 0x2234

525

#define MC_VM_MB_L1_TLB1_CNTL 0x2238

526

#define MC_VM_MB_L1_TLB2_CNTL 0x223C

527

#define MC_VM_MB_L1_TLB3_CNTL 0x2240

528

#define ENABLE_L1_TLB (1 << 0)

529

#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)

530

#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)

531

#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)

532

#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)

533

#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)

534

#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)

535

#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)

536

#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)

537

#define MC_VM_MD_L1_TLB0_CNTL 0x2654

538

#define MC_VM_MD_L1_TLB1_CNTL 0x2658

539

#define MC_VM_MD_L1_TLB2_CNTL 0x265C

Alex Deucher

0b8c30b

2012-05-31 18:54:43 -0400

[diff] [blame]

540

#define MC_VM_MD_L1_TLB3_CNTL 0x2698

Alex Deucher

8aeb96f

2011-05-03 19:28:02 -0400

[diff] [blame]

541

542

#define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C

543

#define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660

544

#define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664

545

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

546

#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C

547

#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038

548

#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034

549

550

#define PA_CL_ENHANCE 0x8A14

551

#define CLIP_VTX_REORDER_ENA (1 << 0)

552

#define NUM_CLIP_SEQ(x) ((x) << 1)

Jerome Glisse

2012-01-05 22:11:05 -0500

[diff] [blame]

553

#define PA_SC_ENHANCE 0x8BF0

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

554

#define PA_SC_AA_CONFIG 0x28C04

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

555

#define MSAA_NUM_SAMPLES_SHIFT 0

556

#define MSAA_NUM_SAMPLES_MASK 0x3

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

557

#define PA_SC_CLIPRECT_RULE 0x2820C

558

#define PA_SC_EDGERULE 0x28230

559

#define PA_SC_FIFO_SIZE 0x8BCC

560

#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)

561

#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

562

#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

563

#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

564

#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)

565

#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

566

#define PA_SC_LINE_STIPPLE 0x28A0C

Alex Deucher

1292059

2011-02-02 12:37:40 -0500

[diff] [blame]

567

#define PA_SU_LINE_STIPPLE_VALUE 0x8A60

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

568

#define PA_SC_LINE_STIPPLE_STATE 0x8B10

569

570

#define SCRATCH_REG0 0x8500

571

#define SCRATCH_REG1 0x8504

572

#define SCRATCH_REG2 0x8508

573

#define SCRATCH_REG3 0x850C

574

#define SCRATCH_REG4 0x8510

575

#define SCRATCH_REG5 0x8514

576

#define SCRATCH_REG6 0x8518

577

#define SCRATCH_REG7 0x851C

578

#define SCRATCH_UMSK 0x8540

579

#define SCRATCH_ADDR 0x8544

580

Alex Deucher

b866d13

2012-06-14 22:06:36 +0200

[diff] [blame]

581

#define SMX_SAR_CTL0 0xA008

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

582

#define SMX_DC_CTL0 0xA020

583

#define USE_HASH_FUNCTION (1 << 0)

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

584

#define NUMBER_OF_SETS(x) ((x) << 1)

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

585

#define FLUSH_ALL_ON_EVENT (1 << 10)

586

#define STALL_ON_EVENT (1 << 11)

587

#define SMX_EVENT_CTL 0xA02C

588

#define ES_FLUSH_CTL(x) ((x) << 0)

589

#define GS_FLUSH_CTL(x) ((x) << 3)

590

#define ACK_FLUSH_CTL(x) ((x) << 6)

591

#define SYNC_FLUSH_CTL (1 << 8)

592

593

#define SPI_CONFIG_CNTL 0x9100

594

#define GPR_WRITE_PRIORITY(x) ((x) << 0)

595

#define SPI_CONFIG_CNTL_1 0x913C

596

#define VTX_DONE_DELAY(x) ((x) << 0)

597

#define INTERP_ONE_PRIM_PER_ROW (1 << 4)

598

#define SPI_INPUT_Z 0x286D8

599

#define SPI_PS_IN_CONTROL_0 0x286CC

600

#define NUM_INTERP(x) ((x)<<0)

601

#define POSITION_ENA (1<<8)

602

#define POSITION_CENTROID (1<<9)

603

#define POSITION_ADDR(x) ((x)<<10)

604

#define PARAM_GEN(x) ((x)<<15)

605

#define PARAM_GEN_ADDR(x) ((x)<<19)

606

#define BARYC_SAMPLE_CNTL(x) ((x)<<26)

607

#define PERSP_GRADIENT_ENA (1<<28)

608

#define LINEAR_GRADIENT_ENA (1<<29)

609

#define POSITION_SAMPLE (1<<30)

610

#define BARYC_AT_SAMPLE_ENA (1<<31)

611

612

#define SQ_CONFIG 0x8C00

613

#define VC_ENABLE (1 << 0)

614

#define EXPORT_SRC_C (1 << 1)

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

615

#define CS_PRIO(x) ((x) << 18)

616

#define LS_PRIO(x) ((x) << 20)

617

#define HS_PRIO(x) ((x) << 22)

618

#define PS_PRIO(x) ((x) << 24)

619

#define VS_PRIO(x) ((x) << 26)

620

#define GS_PRIO(x) ((x) << 28)

621

#define ES_PRIO(x) ((x) << 30)

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

622

#define SQ_GPR_RESOURCE_MGMT_1 0x8C04

623

#define NUM_PS_GPRS(x) ((x) << 0)

624

#define NUM_VS_GPRS(x) ((x) << 16)

625

#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)

626

#define SQ_GPR_RESOURCE_MGMT_2 0x8C08

627

#define NUM_GS_GPRS(x) ((x) << 0)

628

#define NUM_ES_GPRS(x) ((x) << 16)

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

629

#define SQ_GPR_RESOURCE_MGMT_3 0x8C0C

630

#define NUM_HS_GPRS(x) ((x) << 0)

631

#define NUM_LS_GPRS(x) ((x) << 16)

Jerome Glisse

2012-01-05 22:11:05 -0500

[diff] [blame]

632

#define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10

633

#define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

634

#define SQ_THREAD_RESOURCE_MGMT 0x8C18

635

#define NUM_PS_THREADS(x) ((x) << 0)

636

#define NUM_VS_THREADS(x) ((x) << 8)

637

#define NUM_GS_THREADS(x) ((x) << 16)

638

#define NUM_ES_THREADS(x) ((x) << 24)

639

#define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C

640

#define NUM_HS_THREADS(x) ((x) << 0)

641

#define NUM_LS_THREADS(x) ((x) << 8)

642

#define SQ_STACK_RESOURCE_MGMT_1 0x8C20

643

#define NUM_PS_STACK_ENTRIES(x) ((x) << 0)

644

#define NUM_VS_STACK_ENTRIES(x) ((x) << 16)

645

#define SQ_STACK_RESOURCE_MGMT_2 0x8C24

646

#define NUM_GS_STACK_ENTRIES(x) ((x) << 0)

647

#define NUM_ES_STACK_ENTRIES(x) ((x) << 16)

648

#define SQ_STACK_RESOURCE_MGMT_3 0x8C28

649

#define NUM_HS_STACK_ENTRIES(x) ((x) << 0)

650

#define NUM_LS_STACK_ENTRIES(x) ((x) << 16)

651

#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C

Jerome Glisse

2012-01-05 22:11:05 -0500

[diff] [blame]

652

#define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94

653

#define SQ_STATIC_THREAD_MGMT_1 0x8E20

654

#define SQ_STATIC_THREAD_MGMT_2 0x8E24

655

#define SQ_STATIC_THREAD_MGMT_3 0x8E28

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

656

#define SQ_LDS_RESOURCE_MGMT 0x8E2C

657

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

658

#define SQ_MS_FIFO_SIZES 0x8CF0

659

#define CACHE_FIFO_SIZE(x) ((x) << 0)

660

#define FETCH_FIFO_HIWATER(x) ((x) << 8)

661

#define DONE_FIFO_HIWATER(x) ((x) << 16)

662

#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)

663

664

#define SX_DEBUG_1 0x9058

665

#define ENABLE_NEW_SMX_ADDRESS (1 << 16)

666

#define SX_EXPORT_BUFFER_SIZES 0x900C

667

#define COLOR_BUFFER_SIZE(x) ((x) << 0)

668

#define POSITION_BUFFER_SIZE(x) ((x) << 8)

669

#define SMX_BUFFER_SIZE(x) ((x) << 16)

Alex Deucher

033b565

2011-06-08 15:26:45 -0400

[diff] [blame]

670

#define SX_MEMORY_EXPORT_BASE 0x9010

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

671

#define SX_MISC 0x28350

672

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

673

#define CB_PERF_CTR0_SEL_0 0x9A20

674

#define CB_PERF_CTR0_SEL_1 0x9A24

675

#define CB_PERF_CTR1_SEL_0 0x9A28

676

#define CB_PERF_CTR1_SEL_1 0x9A2C

677

#define CB_PERF_CTR2_SEL_0 0x9A30

678

#define CB_PERF_CTR2_SEL_1 0x9A34

679

#define CB_PERF_CTR3_SEL_0 0x9A38

680

#define CB_PERF_CTR3_SEL_1 0x9A3C

681

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

682

#define TA_CNTL_AUX 0x9508

683

#define DISABLE_CUBE_WRAP (1 << 0)

684

#define DISABLE_CUBE_ANISO (1 << 1)

685

#define SYNC_GRADIENT (1 << 24)

686

#define SYNC_WALKER (1 << 25)

687

#define SYNC_ALIGNER (1 << 26)

688

Alex Deucher

9535ab7

2010-11-22 17:56:18 -0500

[diff] [blame]

689

#define TCP_CHAN_STEER_LO 0x960c

690

#define TCP_CHAN_STEER_HI 0x9610

691

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

692

#define VGT_CACHE_INVALIDATION 0x88C4

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

693

#define CACHE_INVALIDATION(x) ((x) << 0)

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

#define VC_ONLY 0

#define TC_ONLY 1

#define VC_AND_TC 2

#define AUTO_INVLD_EN(x) ((x) << 6)

#define NO_AUTO 0

#define ES_AUTO 1

#define GS_AUTO 2

#define ES_AND_GS_AUTO 3

702

#define VGT_GS_VERTEX_REUSE 0x88D4

703

#define VGT_NUM_INSTANCES 0x8974

704

#define VGT_OUT_DEALLOC_CNTL 0x28C5C

705

#define DEALLOC_DIST_MASK 0x0000007F

706

#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58

707

#define VTX_REUSE_DEPTH_MASK 0x000000FF

708

709

#define VM_CONTEXT0_CNTL 0x1410

710

#define ENABLE_CONTEXT (1 << 0)

711

#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)

712

#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)

713

#define VM_CONTEXT1_CNTL 0x1414

Christian König

ae133a1

2012-09-18 15:30:44 -0400

[diff] [blame]

714

#define VM_CONTEXT1_CNTL2 0x1434

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

715

#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C

716

#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C

717

#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C

718

#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518

719

#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470

720

#define REQUEST_TYPE(x) (((x) & 0xf) << 0)

721

#define RESPONSE_TYPE_MASK 0x000000F0

722

#define RESPONSE_TYPE_SHIFT 4

723

#define VM_L2_CNTL 0x1400

724

#define ENABLE_L2_CACHE (1 << 0)

725

#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)

726

#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)

727

#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)

728

#define VM_L2_CNTL2 0x1404

729

#define INVALIDATE_ALL_L1_TLBS (1 << 0)

730

#define INVALIDATE_L2_CACHE (1 << 1)

731

#define VM_L2_CNTL3 0x1408

732

#define BANK_SELECT(x) ((x) << 0)

733

#define CACHE_UPDATE_MODE(x) ((x) << 6)

734

#define VM_L2_STATUS 0x140C

735

#define L2_BUSY (1 << 0)

Christian König

ae133a1

2012-09-18 15:30:44 -0400

[diff] [blame]

736

#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC

737

#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

738

739

#define WAIT_UNTIL 0x8040

740

741

#define SRBM_STATUS 0x0E50

Alex Deucher

a65a436

2013-01-18 18:55:54 -0500

[diff] [blame]

742

#define RLC_RQ_PENDING (1 << 3)

743

#define GRBM_RQ_PENDING (1 << 5)

744

#define VMC_BUSY (1 << 8)

745

#define MCB_BUSY (1 << 9)

746

#define MCB_NON_DISPLAY_BUSY (1 << 10)

747

#define MCC_BUSY (1 << 11)

748

#define MCD_BUSY (1 << 12)

749

#define SEM_BUSY (1 << 14)

750

#define RLC_BUSY (1 << 15)

751

#define IH_BUSY (1 << 17)

752

#define SRBM_STATUS2 0x0EC4

753

#define DMA_BUSY (1 << 5)

Alex Deucher

2010-03-24 13:26:36 -0400

[diff] [blame]

754

#define SRBM_SOFT_RESET 0x0E60

755

#define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6

756

#define SOFT_RESET_BIF (1 << 1)

757

#define SOFT_RESET_CG (1 << 2)

758

#define SOFT_RESET_DC (1 << 5)

759

#define SOFT_RESET_GRBM (1 << 8)

760

#define SOFT_RESET_HDP (1 << 9)

761

#define SOFT_RESET_IH (1 << 10)

762

#define SOFT_RESET_MC (1 << 11)

763

#define SOFT_RESET_RLC (1 << 13)

764

#define SOFT_RESET_ROM (1 << 14)

765

#define SOFT_RESET_SEM (1 << 15)

766

#define SOFT_RESET_VMC (1 << 17)

Jerome Glisse

64c56e8

2013-01-02 17:30:35 -0500

[diff] [blame]

767

#define SOFT_RESET_DMA (1 << 20)

Alex Deucher

2010-03-24 13:26:36 -0400

[diff] [blame]

768

#define SOFT_RESET_TST (1 << 21)

Jerome Glisse

64c56e8

2013-01-02 17:30:35 -0500

[diff] [blame]

769

#define SOFT_RESET_REGBB (1 << 22)

Alex Deucher

2010-03-24 13:26:36 -0400

[diff] [blame]

770

#define SOFT_RESET_ORB (1 << 23)

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

771

Alex Deucher

f9d9c36

2010-10-22 02:51:05 -0400

[diff] [blame]

772

/* display watermarks */

773

#define DC_LB_MEMORY_SPLIT 0x6b0c

774

#define PRIORITY_A_CNT 0x6b18

775

#define PRIORITY_MARK_MASK 0x7fff

776

#define PRIORITY_OFF (1 << 16)

777

#define PRIORITY_ALWAYS_ON (1 << 20)

778

#define PRIORITY_B_CNT 0x6b1c

779

#define PIPE0_ARBITRATION_CONTROL3 0x0bf0

780

# define LATENCY_WATERMARK_MASK(x) ((x) << 16)

781

#define PIPE0_LATENCY_CONTROL 0x0bf4

782

# define LATENCY_LOW_WATERMARK(x) ((x) << 0)

783

# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)

784

Alex Deucher

45f9a39

2010-03-24 13:55:51 -0400

[diff] [blame]

785

#define IH_RB_CNTL 0x3e00

786

# define IH_RB_ENABLE (1 << 0)

787

# define IH_IB_SIZE(x) ((x) << 1) /* log2 */

788

# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)

789

# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)

790

# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */

791

# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)

792

# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)

793

#define IH_RB_BASE 0x3e04

794

#define IH_RB_RPTR 0x3e08

795

#define IH_RB_WPTR 0x3e0c

796

# define RB_OVERFLOW (1 << 0)

797

# define WPTR_OFFSET_MASK 0x3fffc

798

#define IH_RB_WPTR_ADDR_HI 0x3e10

799

#define IH_RB_WPTR_ADDR_LO 0x3e14

800

#define IH_CNTL 0x3e18

801

# define ENABLE_INTR (1 << 0)

Alex Deucher

fcb857a

2011-07-06 19:52:27 +0000

[diff] [blame]

802

# define IH_MC_SWAP(x) ((x) << 1)

Alex Deucher

45f9a39

2010-03-24 13:55:51 -0400

[diff] [blame]

803

# define IH_MC_SWAP_NONE 0

804

# define IH_MC_SWAP_16BIT 1

805

# define IH_MC_SWAP_32BIT 2

806

# define IH_MC_SWAP_64BIT 3

807

# define RPTR_REARM (1 << 4)

808

# define MC_WRREQ_CREDIT(x) ((x) << 15)

809

# define MC_WR_CLEAN_CNT(x) ((x) << 20)

810

811

#define CP_INT_CNTL 0xc124

812

# define CNTX_BUSY_INT_ENABLE (1 << 19)

813

# define CNTX_EMPTY_INT_ENABLE (1 << 20)

814

# define SCRATCH_INT_ENABLE (1 << 25)

815

# define TIME_STAMP_INT_ENABLE (1 << 26)

816

# define IB2_INT_ENABLE (1 << 29)

817

# define IB1_INT_ENABLE (1 << 30)

818

# define RB_INT_ENABLE (1 << 31)

819

#define CP_INT_STATUS 0xc128

820

# define SCRATCH_INT_STAT (1 << 25)

821

# define TIME_STAMP_INT_STAT (1 << 26)

822

# define IB2_INT_STAT (1 << 29)

823

# define IB1_INT_STAT (1 << 30)

824

# define RB_INT_STAT (1 << 31)

825

826

#define GRBM_INT_CNTL 0x8060

827

# define RDERR_INT_ENABLE (1 << 0)

828

# define GUI_IDLE_INT_ENABLE (1 << 19)

829

830

/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */

831

#define CRTC_STATUS_FRAME_COUNT 0x6e98

832

833

/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */

834

#define VLINE_STATUS 0x6bb8

835

# define VLINE_OCCURRED (1 << 0)

836

# define VLINE_ACK (1 << 4)

837

# define VLINE_STAT (1 << 12)

838

# define VLINE_INTERRUPT (1 << 16)

839

# define VLINE_INTERRUPT_TYPE (1 << 17)

840

/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */

841

#define VBLANK_STATUS 0x6bbc

842

# define VBLANK_OCCURRED (1 << 0)

843

# define VBLANK_ACK (1 << 4)

844

# define VBLANK_STAT (1 << 12)

845

# define VBLANK_INTERRUPT (1 << 16)

846

# define VBLANK_INTERRUPT_TYPE (1 << 17)

847

848

/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */

849

#define INT_MASK 0x6b40

850

# define VBLANK_INT_MASK (1 << 0)

851

# define VLINE_INT_MASK (1 << 4)

852

853

#define DISP_INTERRUPT_STATUS 0x60f4

854

# define LB_D1_VLINE_INTERRUPT (1 << 2)

855

# define LB_D1_VBLANK_INTERRUPT (1 << 3)

856

# define DC_HPD1_INTERRUPT (1 << 17)

857

# define DC_HPD1_RX_INTERRUPT (1 << 18)

858

# define DACA_AUTODETECT_INTERRUPT (1 << 22)

859

# define DACB_AUTODETECT_INTERRUPT (1 << 23)

860

# define DC_I2C_SW_DONE_INTERRUPT (1 << 24)

861

# define DC_I2C_HW_DONE_INTERRUPT (1 << 25)

862

#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8

863

# define LB_D2_VLINE_INTERRUPT (1 << 2)

864

# define LB_D2_VBLANK_INTERRUPT (1 << 3)

865

# define DC_HPD2_INTERRUPT (1 << 17)

866

# define DC_HPD2_RX_INTERRUPT (1 << 18)

867

# define DISP_TIMER_INTERRUPT (1 << 24)

868

#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc

869

# define LB_D3_VLINE_INTERRUPT (1 << 2)

870

# define LB_D3_VBLANK_INTERRUPT (1 << 3)

871

# define DC_HPD3_INTERRUPT (1 << 17)

872

# define DC_HPD3_RX_INTERRUPT (1 << 18)

873

#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100

874

# define LB_D4_VLINE_INTERRUPT (1 << 2)

875

# define LB_D4_VBLANK_INTERRUPT (1 << 3)

876

# define DC_HPD4_INTERRUPT (1 << 17)

877

# define DC_HPD4_RX_INTERRUPT (1 << 18)

878

#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c

879

# define LB_D5_VLINE_INTERRUPT (1 << 2)

880

# define LB_D5_VBLANK_INTERRUPT (1 << 3)

881

# define DC_HPD5_INTERRUPT (1 << 17)

882

# define DC_HPD5_RX_INTERRUPT (1 << 18)

Alex Deucher

37cba6c

2011-07-06 19:37:47 +0000

[diff] [blame]

883

#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150

Alex Deucher

45f9a39

2010-03-24 13:55:51 -0400

[diff] [blame]

884

# define LB_D6_VLINE_INTERRUPT (1 << 2)

885

# define LB_D6_VBLANK_INTERRUPT (1 << 3)

886

# define DC_HPD6_INTERRUPT (1 << 17)

887

# define DC_HPD6_RX_INTERRUPT (1 << 18)

888

889

/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */

890

#define GRPH_INT_STATUS 0x6858

891

# define GRPH_PFLIP_INT_OCCURRED (1 << 0)

892

# define GRPH_PFLIP_INT_CLEAR (1 << 8)

893

/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */

894

#define GRPH_INT_CONTROL 0x685c

895

# define GRPH_PFLIP_INT_MASK (1 << 0)

896

# define GRPH_PFLIP_INT_TYPE (1 << 8)

897

898

#define DACA_AUTODETECT_INT_CONTROL 0x66c8

899

#define DACB_AUTODETECT_INT_CONTROL 0x67c8

900

901

#define DC_HPD1_INT_STATUS 0x601c

902

#define DC_HPD2_INT_STATUS 0x6028

903

#define DC_HPD3_INT_STATUS 0x6034

904

#define DC_HPD4_INT_STATUS 0x6040

905

#define DC_HPD5_INT_STATUS 0x604c

906

#define DC_HPD6_INT_STATUS 0x6058

907

# define DC_HPDx_INT_STATUS (1 << 0)

908

# define DC_HPDx_SENSE (1 << 1)

909

# define DC_HPDx_RX_INT_STATUS (1 << 8)

910

911

#define DC_HPD1_INT_CONTROL 0x6020

912

#define DC_HPD2_INT_CONTROL 0x602c

913

#define DC_HPD3_INT_CONTROL 0x6038

914

#define DC_HPD4_INT_CONTROL 0x6044

915

#define DC_HPD5_INT_CONTROL 0x6050

916

#define DC_HPD6_INT_CONTROL 0x605c

917

# define DC_HPDx_INT_ACK (1 << 0)

918

# define DC_HPDx_INT_POLARITY (1 << 8)

919

# define DC_HPDx_INT_EN (1 << 16)

920

# define DC_HPDx_RX_INT_ACK (1 << 20)

921

# define DC_HPDx_RX_INT_EN (1 << 24)

922

923

#define DC_HPD1_CONTROL 0x6024

924

#define DC_HPD2_CONTROL 0x6030

925

#define DC_HPD3_CONTROL 0x603c

926

#define DC_HPD4_CONTROL 0x6048

927

#define DC_HPD5_CONTROL 0x6054

928

#define DC_HPD6_CONTROL 0x6060

929

# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)

930

# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)

931

# define DC_HPDx_EN (1 << 28)

932

Alex Deucher

2012-12-04 15:25:59 -0500

[diff] [blame]

933

/* ASYNC DMA */

934

#define DMA_RB_RPTR 0xd008

935

#define DMA_RB_WPTR 0xd00c

936

937

#define DMA_CNTL 0xd02c

938

# define TRAP_ENABLE (1 << 0)

939

# define SEM_INCOMPLETE_INT_ENABLE (1 << 1)

940

# define SEM_WAIT_INT_ENABLE (1 << 2)

941

# define DATA_SWAP_ENABLE (1 << 3)

942

# define FENCE_SWAP_ENABLE (1 << 4)

943

# define CTXEMPTY_INT_ENABLE (1 << 28)

944

#define DMA_TILING_CONFIG 0xD0B8

945

Alex Deucher

f60cbd1

2012-12-04 15:27:33 -0500

[diff] [blame]

946

#define CAYMAN_DMA1_CNTL 0xd82c

947

Alex Deucher

2012-12-04 15:25:59 -0500

[diff] [blame]

948

/* async DMA packets */

Jerome Glisse

0fcb615

2013-01-14 11:32:27 -0500

[diff] [blame]

949

#define DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) | \

950

(((sub_cmd) & 0xFF) << 20) |\

951

(((n) & 0xFFFFF) << 0))

952

#define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)

953

#define GET_DMA_COUNT(h) ((h) & 0x000fffff)

954

#define GET_DMA_SUB_CMD(h) (((h) & 0x0ff00000) >> 20)

955

Alex Deucher

2012-12-04 15:25:59 -0500

[diff] [blame]

956

/* async DMA Packet types */

Jerome Glisse

0fcb615

2013-01-14 11:32:27 -0500

[diff] [blame]

957

#define DMA_PACKET_WRITE 0x2

958

#define DMA_PACKET_COPY 0x3

959

#define DMA_PACKET_INDIRECT_BUFFER 0x4

960

#define DMA_PACKET_SEMAPHORE 0x5

961

#define DMA_PACKET_FENCE 0x6

962

#define DMA_PACKET_TRAP 0x7

963

#define DMA_PACKET_SRBM_WRITE 0x9

964

#define DMA_PACKET_CONSTANT_FILL 0xd

965

#define DMA_PACKET_NOP 0xf

Alex Deucher

2012-12-04 15:25:59 -0500

[diff] [blame]

966

Alex Deucher

9e46a48

2011-01-06 18:49:35 -0500

[diff] [blame]

967

/* PCIE link stuff */

968

#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */

969

#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */

970

# define LC_LINK_WIDTH_SHIFT 0

971

# define LC_LINK_WIDTH_MASK 0x7

972

# define LC_LINK_WIDTH_X0 0

973

# define LC_LINK_WIDTH_X1 1

974

# define LC_LINK_WIDTH_X2 2

975

# define LC_LINK_WIDTH_X4 3

976

# define LC_LINK_WIDTH_X8 4

977

# define LC_LINK_WIDTH_X16 6

978

# define LC_LINK_WIDTH_RD_SHIFT 4

979

# define LC_LINK_WIDTH_RD_MASK 0x70

980

# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)

981

# define LC_RECONFIG_NOW (1 << 8)

982

# define LC_RENEGOTIATION_SUPPORT (1 << 9)

983

# define LC_RENEGOTIATE_EN (1 << 10)

984

# define LC_SHORT_RECONFIG_EN (1 << 11)

985

# define LC_UPCONFIGURE_SUPPORT (1 << 12)

986

# define LC_UPCONFIGURE_DIS (1 << 13)

987

#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */

988

# define LC_GEN2_EN_STRAP (1 << 0)

989

# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)

990

# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)

991

# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)

992

# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)

993

# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3

994

# define LC_CURRENT_DATA_RATE (1 << 11)

995

# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)

996

# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)

997

# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)

998

# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)

999

#define MM_CFGREGS_CNTL 0x544c

1000

# define MM_WR_TO_CFG_EN (1 << 3)

1001

#define LINK_CNTL2 0x88 /* F0 */

1002

# define TARGET_LINK_SPEED_MASK (0xf << 0)

1003

# define SELECTABLE_DEEMPHASIS (1 << 6)

1004

Christian König

f2ba57b

2013-04-08 12:41:29 +0200

[diff] [blame]

/*

* UVD

*/

#define UVD_RBC_RB_RPTR 0xf690

1010

#define UVD_RBC_RB_WPTR 0xf694

1011

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1012

/*

1013

* PM4

1014

*/

Ilija Hadzic

4e872ae

2013-01-02 18:27:48 -0500

[diff] [blame]

1015

#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1016

(((reg) >> 2) & 0xFFFF) | \

1017

((n) & 0x3FFF) << 16)

1018

#define CP_PACKET2 0x80000000

1019

#define PACKET2_PAD_SHIFT 0

1020

#define PACKET2_PAD_MASK (0x3fffffff << 0)

1021

1022

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

1023

Ilija Hadzic

4e872ae

2013-01-02 18:27:48 -0500

[diff] [blame]

1024

#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1025

(((op) & 0xFF) << 8) | \

1026

((n) & 0x3FFF) << 16)

1027

1028

/* Packet 3 types */

1029

#define PACKET3_NOP 0x10

1030

#define PACKET3_SET_BASE 0x11

1031

#define PACKET3_CLEAR_STATE 0x12

Alex Deucher

32171d2

2011-01-06 19:13:32 -0500

[diff] [blame]

1032

#define PACKET3_INDEX_BUFFER_SIZE 0x13

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1033

#define PACKET3_DISPATCH_DIRECT 0x15

1034

#define PACKET3_DISPATCH_INDIRECT 0x16

1035

#define PACKET3_INDIRECT_BUFFER_END 0x17

Alex Deucher

1292059

2011-02-02 12:37:40 -0500

[diff] [blame]

1036

#define PACKET3_MODE_CONTROL 0x18

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1037

#define PACKET3_SET_PREDICATION 0x20

1038

#define PACKET3_REG_RMW 0x21

1039

#define PACKET3_COND_EXEC 0x22

1040

#define PACKET3_PRED_EXEC 0x23

1041

#define PACKET3_DRAW_INDIRECT 0x24

1042

#define PACKET3_DRAW_INDEX_INDIRECT 0x25

1043

#define PACKET3_INDEX_BASE 0x26

1044

#define PACKET3_DRAW_INDEX_2 0x27

1045

#define PACKET3_CONTEXT_CONTROL 0x28

1046

#define PACKET3_DRAW_INDEX_OFFSET 0x29

1047

#define PACKET3_INDEX_TYPE 0x2A

1048

#define PACKET3_DRAW_INDEX 0x2B

1049

#define PACKET3_DRAW_INDEX_AUTO 0x2D

1050

#define PACKET3_DRAW_INDEX_IMMD 0x2E

1051

#define PACKET3_NUM_INSTANCES 0x2F

1052

#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30

1053

#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34

1054

#define PACKET3_DRAW_INDEX_OFFSET_2 0x35

1055

#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36

1056

#define PACKET3_MEM_SEMAPHORE 0x39

1057

#define PACKET3_MPEG_INDEX 0x3A

Jerome Glisse

2012-01-05 22:11:05 -0500

[diff] [blame]

1058

#define PACKET3_COPY_DW 0x3B

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1059

#define PACKET3_WAIT_REG_MEM 0x3C

1060

#define PACKET3_MEM_WRITE 0x3D

1061

#define PACKET3_INDIRECT_BUFFER 0x32

Alex Deucher

b997a8b

2012-12-03 18:07:25 -0500

[diff] [blame]

1062

#define PACKET3_CP_DMA 0x41

1063

/* 1. header

1064

* 2. SRC_ADDR_LO or DATA [31:0]

1065

* 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |

1066

* SRC_ADDR_HI [7:0]

1067

* 4. DST_ADDR_LO [31:0]

1068

* 5. DST_ADDR_HI [7:0]

1069

* 6. COMMAND [29:22] | BYTE_COUNT [20:0]

1070

*/

1071

# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)

/* 0 - SRC_ADDR

* 1 - GDS

*/

# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)

/* 0 - ME

* 1 - PFP

*/

# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)

/* 0 - SRC_ADDR

* 1 - GDS

* 2 - DATA

*/

# define PACKET3_CP_DMA_CP_SYNC (1 << 31)

1085

/* COMMAND */

1086

# define PACKET3_CP_DMA_DIS_WC (1 << 21)

1087

# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)

/* 0 - none

* 1 - 8 in 16

* 2 - 8 in 32

* 3 - 8 in 64

*/

# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)

/* 0 - none

* 1 - 8 in 16

* 2 - 8 in 32

* 3 - 8 in 64

*/

# define PACKET3_CP_DMA_CMD_SAS (1 << 26)

/* 0 - memory

* 1 - register

*/

# define PACKET3_CP_DMA_CMD_DAS (1 << 27)

/* 0 - memory

* 1 - register

*/

# define PACKET3_CP_DMA_CMD_SAIC (1 << 28)

1108

# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1109

#define PACKET3_SURFACE_SYNC 0x43

1110

# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)

1111

# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)

1112

# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)

1113

# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)

1114

# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)

1115

# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)

1116

# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)

1117

# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)

1118

# define PACKET3_DB_DEST_BASE_ENA (1 << 14)

1119

# define PACKET3_CB8_DEST_BASE_ENA (1 << 15)

1120

# define PACKET3_CB9_DEST_BASE_ENA (1 << 16)

1121

# define PACKET3_CB10_DEST_BASE_ENA (1 << 17)

Alex Deucher

32171d2

2011-01-06 19:13:32 -0500

[diff] [blame]

1122

# define PACKET3_CB11_DEST_BASE_ENA (1 << 18)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1123

# define PACKET3_FULL_CACHE_ENA (1 << 20)

1124

# define PACKET3_TC_ACTION_ENA (1 << 23)

1125

# define PACKET3_VC_ACTION_ENA (1 << 24)

1126

# define PACKET3_CB_ACTION_ENA (1 << 25)

1127

# define PACKET3_DB_ACTION_ENA (1 << 26)

1128

# define PACKET3_SH_ACTION_ENA (1 << 27)

Alex Deucher

32171d2

2011-01-06 19:13:32 -0500

[diff] [blame]

1129

# define PACKET3_SX_ACTION_ENA (1 << 28)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1130

#define PACKET3_ME_INITIALIZE 0x44

1131

#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)

1132

#define PACKET3_COND_WRITE 0x45

1133

#define PACKET3_EVENT_WRITE 0x46

1134

#define PACKET3_EVENT_WRITE_EOP 0x47

1135

#define PACKET3_EVENT_WRITE_EOS 0x48

1136

#define PACKET3_PREAMBLE_CNTL 0x4A

Alex Deucher

2281a37

2010-10-21 13:31:38 -0400

[diff] [blame]

1137

# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)

1138

# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1139

#define PACKET3_RB_OFFSET 0x4B

1140

#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C

1141

#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D

1142

#define PACKET3_ALU_PS_CONST_UPDATE 0x4E

1143

#define PACKET3_ALU_VS_CONST_UPDATE 0x4F

1144

#define PACKET3_ONE_REG_WRITE 0x57

1145

#define PACKET3_SET_CONFIG_REG 0x68

1146

#define PACKET3_SET_CONFIG_REG_START 0x00008000

1147

#define PACKET3_SET_CONFIG_REG_END 0x0000ac00

1148

#define PACKET3_SET_CONTEXT_REG 0x69

1149

#define PACKET3_SET_CONTEXT_REG_START 0x00028000

1150

#define PACKET3_SET_CONTEXT_REG_END 0x00029000

1151

#define PACKET3_SET_ALU_CONST 0x6A

1152

/* alu const buffers only; no reg file */

1153

#define PACKET3_SET_BOOL_CONST 0x6B

1154

#define PACKET3_SET_BOOL_CONST_START 0x0003a500

1155

#define PACKET3_SET_BOOL_CONST_END 0x0003a518

1156

#define PACKET3_SET_LOOP_CONST 0x6C

1157

#define PACKET3_SET_LOOP_CONST_START 0x0003a200

1158

#define PACKET3_SET_LOOP_CONST_END 0x0003a500

1159

#define PACKET3_SET_RESOURCE 0x6D

1160

#define PACKET3_SET_RESOURCE_START 0x00030000

1161

#define PACKET3_SET_RESOURCE_END 0x00038000

1162

#define PACKET3_SET_SAMPLER 0x6E

1163

#define PACKET3_SET_SAMPLER_START 0x0003c000

1164

#define PACKET3_SET_SAMPLER_END 0x0003c600

1165

#define PACKET3_SET_CTL_CONST 0x6F

1166

#define PACKET3_SET_CTL_CONST_START 0x0003cff0

1167

#define PACKET3_SET_CTL_CONST_END 0x0003ff0c

1168

#define PACKET3_SET_RESOURCE_OFFSET 0x70

1169

#define PACKET3_SET_ALU_CONST_VS 0x71

1170

#define PACKET3_SET_ALU_CONST_DI 0x72

1171

#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73

1172

#define PACKET3_SET_RESOURCE_INDIRECT 0x74

1173

#define PACKET3_SET_APPEND_CNT 0x75

1174

1175

#define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c

1176

#define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30)

1177

#define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3)

1178

#define SQ_TEX_VTX_INVALID_TEXTURE 0x0

1179

#define SQ_TEX_VTX_INVALID_BUFFER 0x1

1180

#define SQ_TEX_VTX_VALID_TEXTURE 0x2

1181

#define SQ_TEX_VTX_VALID_BUFFER 0x3

1182

Jerome Glisse

2012-01-05 22:11:05 -0500

[diff] [blame]

1183

#define VGT_VTX_VECT_EJECT_REG 0x88b0

1184

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1185

#define SQ_CONST_MEM_BASE 0x8df8

1186

Alex Deucher

2011-03-02 20:07:40 -0500

[diff] [blame]

1187

#define SQ_ESGS_RING_BASE 0x8c40

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1188

#define SQ_ESGS_RING_SIZE 0x8c44

Alex Deucher

2011-03-02 20:07:40 -0500

[diff] [blame]

1189

#define SQ_GSVS_RING_BASE 0x8c48

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1190

#define SQ_GSVS_RING_SIZE 0x8c4c

Alex Deucher

2011-03-02 20:07:40 -0500

[diff] [blame]

1191

#define SQ_ESTMP_RING_BASE 0x8c50

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1192

#define SQ_ESTMP_RING_SIZE 0x8c54

Alex Deucher

2011-03-02 20:07:40 -0500

[diff] [blame]

1193

#define SQ_GSTMP_RING_BASE 0x8c58

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1194

#define SQ_GSTMP_RING_SIZE 0x8c5c

Alex Deucher

2011-03-02 20:07:40 -0500

[diff] [blame]

1195

#define SQ_VSTMP_RING_BASE 0x8c60

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1196

#define SQ_VSTMP_RING_SIZE 0x8c64

Alex Deucher

2011-03-02 20:07:40 -0500

[diff] [blame]

1197

#define SQ_PSTMP_RING_BASE 0x8c68

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1198

#define SQ_PSTMP_RING_SIZE 0x8c6c

Alex Deucher

2011-03-02 20:07:40 -0500

[diff] [blame]

1199

#define SQ_LSTMP_RING_BASE 0x8e10

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1200

#define SQ_LSTMP_RING_SIZE 0x8e14

Alex Deucher

2011-03-02 20:07:40 -0500

[diff] [blame]

1201

#define SQ_HSTMP_RING_BASE 0x8e18

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1202

#define SQ_HSTMP_RING_SIZE 0x8e1c

1203

#define VGT_TF_RING_SIZE 0x8988

1204

1205

#define SQ_ESGS_RING_ITEMSIZE 0x28900

1206

#define SQ_GSVS_RING_ITEMSIZE 0x28904

1207

#define SQ_ESTMP_RING_ITEMSIZE 0x28908

1208

#define SQ_GSTMP_RING_ITEMSIZE 0x2890c

1209

#define SQ_VSTMP_RING_ITEMSIZE 0x28910

1210

#define SQ_PSTMP_RING_ITEMSIZE 0x28914

1211

#define SQ_LSTMP_RING_ITEMSIZE 0x28830

1212

#define SQ_HSTMP_RING_ITEMSIZE 0x28834

1213

1214

#define SQ_GS_VERT_ITEMSIZE 0x2891c

1215

#define SQ_GS_VERT_ITEMSIZE_1 0x28920

1216

#define SQ_GS_VERT_ITEMSIZE_2 0x28924

1217

#define SQ_GS_VERT_ITEMSIZE_3 0x28928

1218

#define SQ_GSVS_RING_OFFSET_1 0x2892c

1219

#define SQ_GSVS_RING_OFFSET_2 0x28930

1220

#define SQ_GSVS_RING_OFFSET_3 0x28934

1221

Alex Deucher

60a4a3e

2010-06-29 17:03:35 -0400

[diff] [blame]

1222

#define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140

1223

#define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80

1224

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1225

#define SQ_ALU_CONST_CACHE_PS_0 0x28940

1226

#define SQ_ALU_CONST_CACHE_PS_1 0x28944

1227

#define SQ_ALU_CONST_CACHE_PS_2 0x28948

1228

#define SQ_ALU_CONST_CACHE_PS_3 0x2894c

1229

#define SQ_ALU_CONST_CACHE_PS_4 0x28950

1230

#define SQ_ALU_CONST_CACHE_PS_5 0x28954

1231

#define SQ_ALU_CONST_CACHE_PS_6 0x28958

1232

#define SQ_ALU_CONST_CACHE_PS_7 0x2895c

1233

#define SQ_ALU_CONST_CACHE_PS_8 0x28960

1234

#define SQ_ALU_CONST_CACHE_PS_9 0x28964

1235

#define SQ_ALU_CONST_CACHE_PS_10 0x28968

1236

#define SQ_ALU_CONST_CACHE_PS_11 0x2896c

1237

#define SQ_ALU_CONST_CACHE_PS_12 0x28970

1238

#define SQ_ALU_CONST_CACHE_PS_13 0x28974

1239

#define SQ_ALU_CONST_CACHE_PS_14 0x28978

1240

#define SQ_ALU_CONST_CACHE_PS_15 0x2897c

1241

#define SQ_ALU_CONST_CACHE_VS_0 0x28980

1242

#define SQ_ALU_CONST_CACHE_VS_1 0x28984

1243

#define SQ_ALU_CONST_CACHE_VS_2 0x28988

1244

#define SQ_ALU_CONST_CACHE_VS_3 0x2898c

1245

#define SQ_ALU_CONST_CACHE_VS_4 0x28990

1246

#define SQ_ALU_CONST_CACHE_VS_5 0x28994

1247

#define SQ_ALU_CONST_CACHE_VS_6 0x28998

1248

#define SQ_ALU_CONST_CACHE_VS_7 0x2899c

1249

#define SQ_ALU_CONST_CACHE_VS_8 0x289a0

1250

#define SQ_ALU_CONST_CACHE_VS_9 0x289a4

1251

#define SQ_ALU_CONST_CACHE_VS_10 0x289a8

1252

#define SQ_ALU_CONST_CACHE_VS_11 0x289ac

1253

#define SQ_ALU_CONST_CACHE_VS_12 0x289b0

1254

#define SQ_ALU_CONST_CACHE_VS_13 0x289b4

1255

#define SQ_ALU_CONST_CACHE_VS_14 0x289b8

1256

#define SQ_ALU_CONST_CACHE_VS_15 0x289bc

1257

#define SQ_ALU_CONST_CACHE_GS_0 0x289c0

1258

#define SQ_ALU_CONST_CACHE_GS_1 0x289c4

1259

#define SQ_ALU_CONST_CACHE_GS_2 0x289c8

1260

#define SQ_ALU_CONST_CACHE_GS_3 0x289cc

1261

#define SQ_ALU_CONST_CACHE_GS_4 0x289d0

1262

#define SQ_ALU_CONST_CACHE_GS_5 0x289d4

1263

#define SQ_ALU_CONST_CACHE_GS_6 0x289d8

1264

#define SQ_ALU_CONST_CACHE_GS_7 0x289dc

1265

#define SQ_ALU_CONST_CACHE_GS_8 0x289e0

1266

#define SQ_ALU_CONST_CACHE_GS_9 0x289e4

1267

#define SQ_ALU_CONST_CACHE_GS_10 0x289e8

1268

#define SQ_ALU_CONST_CACHE_GS_11 0x289ec

1269

#define SQ_ALU_CONST_CACHE_GS_12 0x289f0

1270

#define SQ_ALU_CONST_CACHE_GS_13 0x289f4

1271

#define SQ_ALU_CONST_CACHE_GS_14 0x289f8

1272

#define SQ_ALU_CONST_CACHE_GS_15 0x289fc

1273

#define SQ_ALU_CONST_CACHE_HS_0 0x28f00

1274

#define SQ_ALU_CONST_CACHE_HS_1 0x28f04

1275

#define SQ_ALU_CONST_CACHE_HS_2 0x28f08

1276

#define SQ_ALU_CONST_CACHE_HS_3 0x28f0c

1277

#define SQ_ALU_CONST_CACHE_HS_4 0x28f10

1278

#define SQ_ALU_CONST_CACHE_HS_5 0x28f14

1279

#define SQ_ALU_CONST_CACHE_HS_6 0x28f18

1280

#define SQ_ALU_CONST_CACHE_HS_7 0x28f1c

1281

#define SQ_ALU_CONST_CACHE_HS_8 0x28f20

1282

#define SQ_ALU_CONST_CACHE_HS_9 0x28f24

1283

#define SQ_ALU_CONST_CACHE_HS_10 0x28f28

1284

#define SQ_ALU_CONST_CACHE_HS_11 0x28f2c

1285

#define SQ_ALU_CONST_CACHE_HS_12 0x28f30

1286

#define SQ_ALU_CONST_CACHE_HS_13 0x28f34

1287

#define SQ_ALU_CONST_CACHE_HS_14 0x28f38

1288

#define SQ_ALU_CONST_CACHE_HS_15 0x28f3c

1289

#define SQ_ALU_CONST_CACHE_LS_0 0x28f40

1290

#define SQ_ALU_CONST_CACHE_LS_1 0x28f44

1291

#define SQ_ALU_CONST_CACHE_LS_2 0x28f48

1292

#define SQ_ALU_CONST_CACHE_LS_3 0x28f4c

1293

#define SQ_ALU_CONST_CACHE_LS_4 0x28f50

1294

#define SQ_ALU_CONST_CACHE_LS_5 0x28f54

1295

#define SQ_ALU_CONST_CACHE_LS_6 0x28f58

1296

#define SQ_ALU_CONST_CACHE_LS_7 0x28f5c

1297

#define SQ_ALU_CONST_CACHE_LS_8 0x28f60

1298

#define SQ_ALU_CONST_CACHE_LS_9 0x28f64

1299

#define SQ_ALU_CONST_CACHE_LS_10 0x28f68

1300

#define SQ_ALU_CONST_CACHE_LS_11 0x28f6c

1301

#define SQ_ALU_CONST_CACHE_LS_12 0x28f70

1302

#define SQ_ALU_CONST_CACHE_LS_13 0x28f74

1303

#define SQ_ALU_CONST_CACHE_LS_14 0x28f78

1304

#define SQ_ALU_CONST_CACHE_LS_15 0x28f7c

1305

Alex Deucher

d7ccd8f

2010-09-09 11:33:36 -0400

[diff] [blame]

1306

#define PA_SC_SCREEN_SCISSOR_TL 0x28030

1307

#define PA_SC_GENERIC_SCISSOR_TL 0x28240

1308

#define PA_SC_WINDOW_SCISSOR_TL 0x28204

Alex Deucher

d7ccd8f

2010-09-09 11:33:36 -0400

[diff] [blame]

1309

Jerome Glisse

2012-01-05 22:11:05 -0500

[diff] [blame]

1310

#define VGT_PRIMITIVE_TYPE 0x8958

1311

#define VGT_INDEX_TYPE 0x895C

1312

1313

#define VGT_NUM_INDICES 0x8970

1314

1315

#define VGT_COMPUTE_DIM_X 0x8990

1316

#define VGT_COMPUTE_DIM_Y 0x8994

1317

#define VGT_COMPUTE_DIM_Z 0x8998

1318

#define VGT_COMPUTE_START_X 0x899C

1319

#define VGT_COMPUTE_START_Y 0x89A0

1320

#define VGT_COMPUTE_START_Z 0x89A4

1321

#define VGT_COMPUTE_INDEX 0x89A8

1322

#define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC

1323

#define VGT_HS_OFFCHIP_PARAM 0x89B0

1324

1325

#define DB_DEBUG 0x9830

1326

#define DB_DEBUG2 0x9834

1327

#define DB_DEBUG3 0x9838

1328

#define DB_DEBUG4 0x983C

1329

#define DB_WATERMARKS 0x9854

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1330

#define DB_DEPTH_CONTROL 0x28800

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

1331

#define R_028800_DB_DEPTH_CONTROL 0x028800

1332

#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)

1333

#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)

1334

#define C_028800_STENCIL_ENABLE 0xFFFFFFFE

1335

#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)

1336

#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)

1337

#define C_028800_Z_ENABLE 0xFFFFFFFD

1338

#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)

1339

#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)

1340

#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB

1341

#define S_028800_ZFUNC(x) (((x) & 0x7) << 4)

1342

#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7)

1343

#define C_028800_ZFUNC 0xFFFFFF8F

1344

#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)

1345

#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)

1346

#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F

1347

#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8)

1348

#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7)

1349

#define C_028800_STENCILFUNC 0xFFFFF8FF

1350

#define V_028800_STENCILFUNC_NEVER 0x00000000

1351

#define V_028800_STENCILFUNC_LESS 0x00000001

1352

#define V_028800_STENCILFUNC_EQUAL 0x00000002

1353

#define V_028800_STENCILFUNC_LEQUAL 0x00000003

1354

#define V_028800_STENCILFUNC_GREATER 0x00000004

1355

#define V_028800_STENCILFUNC_NOTEQUAL 0x00000005

1356

#define V_028800_STENCILFUNC_GEQUAL 0x00000006

1357

#define V_028800_STENCILFUNC_ALWAYS 0x00000007

1358

#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11)

1359

#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7)

1360

#define C_028800_STENCILFAIL 0xFFFFC7FF

1361

#define V_028800_STENCIL_KEEP 0x00000000

1362

#define V_028800_STENCIL_ZERO 0x00000001

1363

#define V_028800_STENCIL_REPLACE 0x00000002

1364

#define V_028800_STENCIL_INCR 0x00000003

1365

#define V_028800_STENCIL_DECR 0x00000004

1366

#define V_028800_STENCIL_INVERT 0x00000005

1367

#define V_028800_STENCIL_INCR_WRAP 0x00000006

1368

#define V_028800_STENCIL_DECR_WRAP 0x00000007

1369

#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14)

1370

#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7)

1371

#define C_028800_STENCILZPASS 0xFFFE3FFF

1372

#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17)

1373

#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7)

1374

#define C_028800_STENCILZFAIL 0xFFF1FFFF

1375

#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20)

1376

#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7)

1377

#define C_028800_STENCILFUNC_BF 0xFF8FFFFF

1378

#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23)

1379

#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7)

1380

#define C_028800_STENCILFAIL_BF 0xFC7FFFFF

1381

#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26)

1382

#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7)

1383

#define C_028800_STENCILZPASS_BF 0xE3FFFFFF

1384

#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29)

1385

#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7)

1386

#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1387

#define DB_DEPTH_VIEW 0x28008

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

1388

#define R_028008_DB_DEPTH_VIEW 0x00028008

1389

#define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0)

1390

#define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF)

1391

#define C_028008_SLICE_START 0xFFFFF800

1392

#define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13)

1393

#define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF)

1394

#define C_028008_SLICE_MAX 0xFF001FFF

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1395

#define DB_HTILE_DATA_BASE 0x28014

Jerome Glisse

88f50c8

2012-03-21 19:18:21 -0400

[diff] [blame]

1396

#define DB_HTILE_SURFACE 0x28abc

1397

#define S_028ABC_HTILE_WIDTH(x) (((x) & 0x1) << 0)

1398

#define G_028ABC_HTILE_WIDTH(x) (((x) >> 0) & 0x1)

1399

#define C_028ABC_HTILE_WIDTH 0xFFFFFFFE

1400

#define S_028ABC_HTILE_HEIGHT(x) (((x) & 0x1) << 1)

1401

#define G_028ABC_HTILE_HEIGHT(x) (((x) >> 1) & 0x1)

1402

#define C_028ABC_HTILE_HEIGHT 0xFFFFFFFD

1403

#define G_028ABC_LINEAR(x) (((x) >> 2) & 0x1)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1404

#define DB_Z_INFO 0x28040

1405

# define Z_ARRAY_MODE(x) ((x) << 4)

Alex Deucher

2011-11-28 14:49:28 -0500

[diff] [blame]

1406

# define DB_TILE_SPLIT(x) (((x) & 0x7) << 8)

1407

# define DB_NUM_BANKS(x) (((x) & 0x3) << 12)

1408

# define DB_BANK_WIDTH(x) (((x) & 0x3) << 16)

1409

# define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20)

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

1410

# define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24)

1411

#define R_028040_DB_Z_INFO 0x028040

1412

#define S_028040_FORMAT(x) (((x) & 0x3) << 0)

1413

#define G_028040_FORMAT(x) (((x) >> 0) & 0x3)

1414

#define C_028040_FORMAT 0xFFFFFFFC

1415

#define V_028040_Z_INVALID 0x00000000

1416

#define V_028040_Z_16 0x00000001

1417

#define V_028040_Z_24 0x00000002

1418

#define V_028040_Z_32_FLOAT 0x00000003

1419

#define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4)

1420

#define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF)

1421

#define C_028040_ARRAY_MODE 0xFFFFFF0F

1422

#define S_028040_READ_SIZE(x) (((x) & 0x1) << 28)

1423

#define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1)

1424

#define C_028040_READ_SIZE 0xEFFFFFFF

1425

#define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29)

1426

#define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1)

1427

#define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF

1428

#define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)

1429

#define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)

1430

#define C_028040_ZRANGE_PRECISION 0x7FFFFFFF

1431

#define S_028040_TILE_SPLIT(x) (((x) & 0x7) << 8)

1432

#define G_028040_TILE_SPLIT(x) (((x) >> 8) & 0x7)

1433

#define S_028040_NUM_BANKS(x) (((x) & 0x3) << 12)

1434

#define G_028040_NUM_BANKS(x) (((x) >> 12) & 0x3)

1435

#define S_028040_BANK_WIDTH(x) (((x) & 0x3) << 16)

1436

#define G_028040_BANK_WIDTH(x) (((x) >> 16) & 0x3)

1437

#define S_028040_BANK_HEIGHT(x) (((x) & 0x3) << 20)

1438

#define G_028040_BANK_HEIGHT(x) (((x) >> 20) & 0x3)

1439

#define S_028040_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24)

1440

#define G_028040_MACRO_TILE_ASPECT(x) (((x) >> 24) & 0x3)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1441

#define DB_STENCIL_INFO 0x28044

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

1442

#define R_028044_DB_STENCIL_INFO 0x028044

1443

#define S_028044_FORMAT(x) (((x) & 0x1) << 0)

1444

#define G_028044_FORMAT(x) (((x) >> 0) & 0x1)

1445

#define C_028044_FORMAT 0xFFFFFFFE

Marek Olšák

0f457e4

2012-07-29 16:24:57 +0200

[diff] [blame]

1446

#define V_028044_STENCIL_INVALID 0

1447

#define V_028044_STENCIL_8 1

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

1448

#define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1449

#define DB_Z_READ_BASE 0x28048

1450

#define DB_STENCIL_READ_BASE 0x2804c

1451

#define DB_Z_WRITE_BASE 0x28050

1452

#define DB_STENCIL_WRITE_BASE 0x28054

1453

#define DB_DEPTH_SIZE 0x28058

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

1454

#define R_028058_DB_DEPTH_SIZE 0x028058

1455

#define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0)

1456

#define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF)

1457

#define C_028058_PITCH_TILE_MAX 0xFFFFF800

1458

#define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11)

1459

#define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF)

1460

#define C_028058_HEIGHT_TILE_MAX 0xFFC007FF

1461

#define R_02805C_DB_DEPTH_SLICE 0x02805C

1462

#define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0)

1463

#define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF)

1464

#define C_02805C_SLICE_TILE_MAX 0xFFC00000

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1465

1466

#define SQ_PGM_START_PS 0x28840

1467

#define SQ_PGM_START_VS 0x2885c

1468

#define SQ_PGM_START_GS 0x28874

1469

#define SQ_PGM_START_ES 0x2888c

1470

#define SQ_PGM_START_FS 0x288a4

1471

#define SQ_PGM_START_HS 0x288b8

1472

#define SQ_PGM_START_LS 0x288d0

1473

Marek Olšák

dd220a0

2012-01-27 12:17:59 -0500

[diff] [blame]

1474

#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8

1475

#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8

1476

#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8

1477

#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08

1478

#define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0

1479

#define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0

1480

#define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0

1481

#define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1482

#define VGT_STRMOUT_CONFIG 0x28b94

1483

#define VGT_STRMOUT_BUFFER_CONFIG 0x28b98

1484

1485

#define CB_TARGET_MASK 0x28238

1486

#define CB_SHADER_MASK 0x2823c

1487

1488

#define GDS_ADDR_BASE 0x28720

1489

1490

#define CB_IMMED0_BASE 0x28b9c

1491

#define CB_IMMED1_BASE 0x28ba0

1492

#define CB_IMMED2_BASE 0x28ba4

1493

#define CB_IMMED3_BASE 0x28ba8

1494

#define CB_IMMED4_BASE 0x28bac

1495

#define CB_IMMED5_BASE 0x28bb0

1496

#define CB_IMMED6_BASE 0x28bb4

1497

#define CB_IMMED7_BASE 0x28bb8

1498

#define CB_IMMED8_BASE 0x28bbc

1499

#define CB_IMMED9_BASE 0x28bc0

1500

#define CB_IMMED10_BASE 0x28bc4

1501

#define CB_IMMED11_BASE 0x28bc8

1502

1503

/* all 12 CB blocks have these regs */

1504

#define CB_COLOR0_BASE 0x28c60

1505

#define CB_COLOR0_PITCH 0x28c64

1506

#define CB_COLOR0_SLICE 0x28c68

1507

#define CB_COLOR0_VIEW 0x28c6c

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

1508

#define R_028C6C_CB_COLOR0_VIEW 0x00028C6C

1509

#define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0)

1510

#define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF)

1511

#define C_028C6C_SLICE_START 0xFFFFF800

1512

#define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13)

1513

#define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF)

1514

#define C_028C6C_SLICE_MAX 0xFF001FFF

1515

#define R_028C70_CB_COLOR0_INFO 0x028C70

1516

#define S_028C70_ENDIAN(x) (((x) & 0x3) << 0)

1517

#define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3)

1518

#define C_028C70_ENDIAN 0xFFFFFFFC

1519

#define S_028C70_FORMAT(x) (((x) & 0x3F) << 2)

1520

#define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F)

1521

#define C_028C70_FORMAT 0xFFFFFF03

1522

#define V_028C70_COLOR_INVALID 0x00000000

1523

#define V_028C70_COLOR_8 0x00000001

1524

#define V_028C70_COLOR_4_4 0x00000002

1525

#define V_028C70_COLOR_3_3_2 0x00000003

1526

#define V_028C70_COLOR_16 0x00000005

1527

#define V_028C70_COLOR_16_FLOAT 0x00000006

1528

#define V_028C70_COLOR_8_8 0x00000007

1529

#define V_028C70_COLOR_5_6_5 0x00000008

1530

#define V_028C70_COLOR_6_5_5 0x00000009

1531

#define V_028C70_COLOR_1_5_5_5 0x0000000A

1532

#define V_028C70_COLOR_4_4_4_4 0x0000000B

1533

#define V_028C70_COLOR_5_5_5_1 0x0000000C

1534

#define V_028C70_COLOR_32 0x0000000D

1535

#define V_028C70_COLOR_32_FLOAT 0x0000000E

1536

#define V_028C70_COLOR_16_16 0x0000000F

1537

#define V_028C70_COLOR_16_16_FLOAT 0x00000010

1538

#define V_028C70_COLOR_8_24 0x00000011

1539

#define V_028C70_COLOR_8_24_FLOAT 0x00000012

1540

#define V_028C70_COLOR_24_8 0x00000013

1541

#define V_028C70_COLOR_24_8_FLOAT 0x00000014

1542

#define V_028C70_COLOR_10_11_11 0x00000015

1543

#define V_028C70_COLOR_10_11_11_FLOAT 0x00000016

1544

#define V_028C70_COLOR_11_11_10 0x00000017

1545

#define V_028C70_COLOR_11_11_10_FLOAT 0x00000018

1546

#define V_028C70_COLOR_2_10_10_10 0x00000019

1547

#define V_028C70_COLOR_8_8_8_8 0x0000001A

1548

#define V_028C70_COLOR_10_10_10_2 0x0000001B

1549

#define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C

1550

#define V_028C70_COLOR_32_32 0x0000001D

1551

#define V_028C70_COLOR_32_32_FLOAT 0x0000001E

1552

#define V_028C70_COLOR_16_16_16_16 0x0000001F

1553

#define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020

1554

#define V_028C70_COLOR_32_32_32_32 0x00000022

1555

#define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023

1556

#define V_028C70_COLOR_32_32_32_FLOAT 0x00000030

1557

#define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8)

1558

#define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF)

1559

#define C_028C70_ARRAY_MODE 0xFFFFF0FF

1560

#define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000

1561

#define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001

1562

#define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002

1563

#define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004

1564

#define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12)

1565

#define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7)

1566

#define C_028C70_NUMBER_TYPE 0xFFFF8FFF

1567

#define V_028C70_NUMBER_UNORM 0x00000000

1568

#define V_028C70_NUMBER_SNORM 0x00000001

1569

#define V_028C70_NUMBER_USCALED 0x00000002

1570

#define V_028C70_NUMBER_SSCALED 0x00000003

1571

#define V_028C70_NUMBER_UINT 0x00000004

1572

#define V_028C70_NUMBER_SINT 0x00000005

1573

#define V_028C70_NUMBER_SRGB 0x00000006

1574

#define V_028C70_NUMBER_FLOAT 0x00000007

1575

#define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15)

1576

#define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3)

1577

#define C_028C70_COMP_SWAP 0xFFFE7FFF

1578

#define V_028C70_SWAP_STD 0x00000000

1579

#define V_028C70_SWAP_ALT 0x00000001

1580

#define V_028C70_SWAP_STD_REV 0x00000002

1581

#define V_028C70_SWAP_ALT_REV 0x00000003

1582

#define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17)

1583

#define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1)

1584

#define C_028C70_FAST_CLEAR 0xFFFDFFFF

1585

#define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18)

1586

#define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3)

1587

#define C_028C70_COMPRESSION 0xFFF3FFFF

1588

#define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19)

1589

#define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1)

1590

#define C_028C70_BLEND_CLAMP 0xFFF7FFFF

1591

#define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20)

1592

#define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1)

1593

#define C_028C70_BLEND_BYPASS 0xFFEFFFFF

1594

#define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21)

1595

#define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1)

1596

#define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF

1597

#define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22)

1598

#define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1)

1599

#define C_028C70_ROUND_MODE 0xFFBFFFFF

1600

#define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23)

1601

#define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1)

1602

#define C_028C70_TILE_COMPACT 0xFF7FFFFF

1603

#define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24)

1604

#define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3)

1605

#define C_028C70_SOURCE_FORMAT 0xFCFFFFFF

1606

#define V_028C70_EXPORT_4C_32BPC 0x0

1607

#define V_028C70_EXPORT_4C_16BPC 0x1

1608

#define V_028C70_EXPORT_2C_32BPC 0x2 /* Do not use */

1609

#define S_028C70_RAT(x) (((x) & 0x1) << 26)

1610

#define G_028C70_RAT(x) (((x) >> 26) & 0x1)

1611

#define C_028C70_RAT 0xFBFFFFFF

1612

#define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27)

1613

#define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7)

1614

#define C_028C70_RESOURCE_TYPE 0xC7FFFFFF

1615

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1616

#define CB_COLOR0_INFO 0x28c70

Ilija Hadzic

2011-10-12 23:29:36 -0400

[diff] [blame]

1617

# define CB_FORMAT(x) ((x) << 2)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1618

# define CB_ARRAY_MODE(x) ((x) << 8)

1619

# define ARRAY_LINEAR_GENERAL 0

1620

# define ARRAY_LINEAR_ALIGNED 1

1621

# define ARRAY_1D_TILED_THIN1 2

1622

# define ARRAY_2D_TILED_THIN1 4

Ilija Hadzic

2011-10-12 23:29:36 -0400

[diff] [blame]

1623

# define CB_SOURCE_FORMAT(x) ((x) << 24)

1624

# define CB_SF_EXPORT_FULL 0

1625

# define CB_SF_EXPORT_NORM 1

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

1626

#define R_028C74_CB_COLOR0_ATTRIB 0x028C74

1627

#define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4)

1628

#define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1)

1629

#define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF

1630

#define S_028C74_TILE_SPLIT(x) (((x) & 0xf) << 5)

1631

#define G_028C74_TILE_SPLIT(x) (((x) >> 5) & 0xf)

1632

#define S_028C74_NUM_BANKS(x) (((x) & 0x3) << 10)

1633

#define G_028C74_NUM_BANKS(x) (((x) >> 10) & 0x3)

1634

#define S_028C74_BANK_WIDTH(x) (((x) & 0x3) << 13)

1635

#define G_028C74_BANK_WIDTH(x) (((x) >> 13) & 0x3)

1636

#define S_028C74_BANK_HEIGHT(x) (((x) & 0x3) << 16)

1637

#define G_028C74_BANK_HEIGHT(x) (((x) >> 16) & 0x3)

1638

#define S_028C74_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19)

1639

#define G_028C74_MACRO_TILE_ASPECT(x) (((x) >> 19) & 0x3)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1640

#define CB_COLOR0_ATTRIB 0x28c74

Alex Deucher

2011-11-28 14:49:28 -0500

[diff] [blame]

1641

# define CB_TILE_SPLIT(x) (((x) & 0x7) << 5)

1642

# define ADDR_SURF_TILE_SPLIT_64B 0

1643

# define ADDR_SURF_TILE_SPLIT_128B 1

1644

# define ADDR_SURF_TILE_SPLIT_256B 2

1645

# define ADDR_SURF_TILE_SPLIT_512B 3

1646

# define ADDR_SURF_TILE_SPLIT_1KB 4

1647

# define ADDR_SURF_TILE_SPLIT_2KB 5

1648

# define ADDR_SURF_TILE_SPLIT_4KB 6

1649

# define CB_NUM_BANKS(x) (((x) & 0x3) << 10)

1650

# define ADDR_SURF_2_BANK 0

1651

# define ADDR_SURF_4_BANK 1

1652

# define ADDR_SURF_8_BANK 2

1653

# define ADDR_SURF_16_BANK 3

1654

# define CB_BANK_WIDTH(x) (((x) & 0x3) << 13)

1655

# define ADDR_SURF_BANK_WIDTH_1 0

1656

# define ADDR_SURF_BANK_WIDTH_2 1

1657

# define ADDR_SURF_BANK_WIDTH_4 2

1658

# define ADDR_SURF_BANK_WIDTH_8 3

1659

# define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16)

1660

# define ADDR_SURF_BANK_HEIGHT_1 0

1661

# define ADDR_SURF_BANK_HEIGHT_2 1

1662

# define ADDR_SURF_BANK_HEIGHT_4 2

1663

# define ADDR_SURF_BANK_HEIGHT_8 3

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

1664

# define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1665

#define CB_COLOR0_DIM 0x28c78

1666

/* only CB0-7 blocks have these regs */

1667

#define CB_COLOR0_CMASK 0x28c7c

1668

#define CB_COLOR0_CMASK_SLICE 0x28c80

1669

#define CB_COLOR0_FMASK 0x28c84

1670

#define CB_COLOR0_FMASK_SLICE 0x28c88

1671

#define CB_COLOR0_CLEAR_WORD0 0x28c8c

1672

#define CB_COLOR0_CLEAR_WORD1 0x28c90

1673

#define CB_COLOR0_CLEAR_WORD2 0x28c94

1674

#define CB_COLOR0_CLEAR_WORD3 0x28c98

1675

1676

#define CB_COLOR1_BASE 0x28c9c

1677

#define CB_COLOR2_BASE 0x28cd8

1678

#define CB_COLOR3_BASE 0x28d14

1679

#define CB_COLOR4_BASE 0x28d50

1680

#define CB_COLOR5_BASE 0x28d8c

1681

#define CB_COLOR6_BASE 0x28dc8

1682

#define CB_COLOR7_BASE 0x28e04

1683

#define CB_COLOR8_BASE 0x28e40

1684

#define CB_COLOR9_BASE 0x28e5c

1685

#define CB_COLOR10_BASE 0x28e78

1686

#define CB_COLOR11_BASE 0x28e94

1687

1688

#define CB_COLOR1_PITCH 0x28ca0

1689

#define CB_COLOR2_PITCH 0x28cdc

1690

#define CB_COLOR3_PITCH 0x28d18

1691

#define CB_COLOR4_PITCH 0x28d54

1692

#define CB_COLOR5_PITCH 0x28d90

1693

#define CB_COLOR6_PITCH 0x28dcc

1694

#define CB_COLOR7_PITCH 0x28e08

1695

#define CB_COLOR8_PITCH 0x28e44

1696

#define CB_COLOR9_PITCH 0x28e60

1697

#define CB_COLOR10_PITCH 0x28e7c

1698

#define CB_COLOR11_PITCH 0x28e98

1699

1700

#define CB_COLOR1_SLICE 0x28ca4

1701

#define CB_COLOR2_SLICE 0x28ce0

1702

#define CB_COLOR3_SLICE 0x28d1c

1703

#define CB_COLOR4_SLICE 0x28d58

1704

#define CB_COLOR5_SLICE 0x28d94

1705

#define CB_COLOR6_SLICE 0x28dd0

1706

#define CB_COLOR7_SLICE 0x28e0c

1707

#define CB_COLOR8_SLICE 0x28e48

1708

#define CB_COLOR9_SLICE 0x28e64

1709

#define CB_COLOR10_SLICE 0x28e80

1710

#define CB_COLOR11_SLICE 0x28e9c

1711

1712

#define CB_COLOR1_VIEW 0x28ca8

1713

#define CB_COLOR2_VIEW 0x28ce4

1714

#define CB_COLOR3_VIEW 0x28d20

1715

#define CB_COLOR4_VIEW 0x28d5c

1716

#define CB_COLOR5_VIEW 0x28d98

1717

#define CB_COLOR6_VIEW 0x28dd4

1718

#define CB_COLOR7_VIEW 0x28e10

1719

#define CB_COLOR8_VIEW 0x28e4c

1720

#define CB_COLOR9_VIEW 0x28e68

1721

#define CB_COLOR10_VIEW 0x28e84

1722

#define CB_COLOR11_VIEW 0x28ea0

1723

1724

#define CB_COLOR1_INFO 0x28cac

1725

#define CB_COLOR2_INFO 0x28ce8

1726

#define CB_COLOR3_INFO 0x28d24

1727

#define CB_COLOR4_INFO 0x28d60

1728

#define CB_COLOR5_INFO 0x28d9c

1729

#define CB_COLOR6_INFO 0x28dd8

1730

#define CB_COLOR7_INFO 0x28e14

1731

#define CB_COLOR8_INFO 0x28e50

1732

#define CB_COLOR9_INFO 0x28e6c

1733

#define CB_COLOR10_INFO 0x28e88

1734

#define CB_COLOR11_INFO 0x28ea4

1735

1736

#define CB_COLOR1_ATTRIB 0x28cb0

1737

#define CB_COLOR2_ATTRIB 0x28cec

1738

#define CB_COLOR3_ATTRIB 0x28d28

1739

#define CB_COLOR4_ATTRIB 0x28d64

1740

#define CB_COLOR5_ATTRIB 0x28da0

1741

#define CB_COLOR6_ATTRIB 0x28ddc

1742

#define CB_COLOR7_ATTRIB 0x28e18

1743

#define CB_COLOR8_ATTRIB 0x28e54

1744

#define CB_COLOR9_ATTRIB 0x28e70

1745

#define CB_COLOR10_ATTRIB 0x28e8c

1746

#define CB_COLOR11_ATTRIB 0x28ea8

1747

1748

#define CB_COLOR1_DIM 0x28cb4

1749

#define CB_COLOR2_DIM 0x28cf0

1750

#define CB_COLOR3_DIM 0x28d2c

1751

#define CB_COLOR4_DIM 0x28d68

1752

#define CB_COLOR5_DIM 0x28da4

1753

#define CB_COLOR6_DIM 0x28de0

1754

#define CB_COLOR7_DIM 0x28e1c

1755

#define CB_COLOR8_DIM 0x28e58

1756

#define CB_COLOR9_DIM 0x28e74

1757

#define CB_COLOR10_DIM 0x28e90

1758

#define CB_COLOR11_DIM 0x28eac

1759

1760

#define CB_COLOR1_CMASK 0x28cb8

1761

#define CB_COLOR2_CMASK 0x28cf4

1762

#define CB_COLOR3_CMASK 0x28d30

1763

#define CB_COLOR4_CMASK 0x28d6c

1764

#define CB_COLOR5_CMASK 0x28da8

1765

#define CB_COLOR6_CMASK 0x28de4

1766

#define CB_COLOR7_CMASK 0x28e20

1767

1768

#define CB_COLOR1_CMASK_SLICE 0x28cbc

1769

#define CB_COLOR2_CMASK_SLICE 0x28cf8

1770

#define CB_COLOR3_CMASK_SLICE 0x28d34

1771

#define CB_COLOR4_CMASK_SLICE 0x28d70

1772

#define CB_COLOR5_CMASK_SLICE 0x28dac

1773

#define CB_COLOR6_CMASK_SLICE 0x28de8

1774

#define CB_COLOR7_CMASK_SLICE 0x28e24

1775

1776

#define CB_COLOR1_FMASK 0x28cc0

1777

#define CB_COLOR2_FMASK 0x28cfc

1778

#define CB_COLOR3_FMASK 0x28d38

1779

#define CB_COLOR4_FMASK 0x28d74

1780

#define CB_COLOR5_FMASK 0x28db0

1781

#define CB_COLOR6_FMASK 0x28dec

1782

#define CB_COLOR7_FMASK 0x28e28

1783

1784

#define CB_COLOR1_FMASK_SLICE 0x28cc4

1785

#define CB_COLOR2_FMASK_SLICE 0x28d00

1786

#define CB_COLOR3_FMASK_SLICE 0x28d3c

1787

#define CB_COLOR4_FMASK_SLICE 0x28d78

1788

#define CB_COLOR5_FMASK_SLICE 0x28db4

1789

#define CB_COLOR6_FMASK_SLICE 0x28df0

1790

#define CB_COLOR7_FMASK_SLICE 0x28e2c

1791

1792

#define CB_COLOR1_CLEAR_WORD0 0x28cc8

1793

#define CB_COLOR2_CLEAR_WORD0 0x28d04

1794

#define CB_COLOR3_CLEAR_WORD0 0x28d40

1795

#define CB_COLOR4_CLEAR_WORD0 0x28d7c

1796

#define CB_COLOR5_CLEAR_WORD0 0x28db8

1797

#define CB_COLOR6_CLEAR_WORD0 0x28df4

1798

#define CB_COLOR7_CLEAR_WORD0 0x28e30

1799

1800

#define CB_COLOR1_CLEAR_WORD1 0x28ccc

1801

#define CB_COLOR2_CLEAR_WORD1 0x28d08

1802

#define CB_COLOR3_CLEAR_WORD1 0x28d44

1803

#define CB_COLOR4_CLEAR_WORD1 0x28d80

1804

#define CB_COLOR5_CLEAR_WORD1 0x28dbc

1805

#define CB_COLOR6_CLEAR_WORD1 0x28df8

1806

#define CB_COLOR7_CLEAR_WORD1 0x28e34

1807

1808

#define CB_COLOR1_CLEAR_WORD2 0x28cd0

1809

#define CB_COLOR2_CLEAR_WORD2 0x28d0c

1810

#define CB_COLOR3_CLEAR_WORD2 0x28d48

1811

#define CB_COLOR4_CLEAR_WORD2 0x28d84

1812

#define CB_COLOR5_CLEAR_WORD2 0x28dc0

1813

#define CB_COLOR6_CLEAR_WORD2 0x28dfc

1814

#define CB_COLOR7_CLEAR_WORD2 0x28e38

1815

1816

#define CB_COLOR1_CLEAR_WORD3 0x28cd4

1817

#define CB_COLOR2_CLEAR_WORD3 0x28d10

1818

#define CB_COLOR3_CLEAR_WORD3 0x28d4c

1819

#define CB_COLOR4_CLEAR_WORD3 0x28d88

1820

#define CB_COLOR5_CLEAR_WORD3 0x28dc4

1821

#define CB_COLOR6_CLEAR_WORD3 0x28e00

1822

#define CB_COLOR7_CLEAR_WORD3 0x28e3c

1823

1824

#define SQ_TEX_RESOURCE_WORD0_0 0x30000

Ilija Hadzic

2011-10-12 23:29:36 -0400

[diff] [blame]

1825

# define TEX_DIM(x) ((x) << 0)

1826

# define SQ_TEX_DIM_1D 0

1827

# define SQ_TEX_DIM_2D 1

1828

# define SQ_TEX_DIM_3D 2

1829

# define SQ_TEX_DIM_CUBEMAP 3

1830

# define SQ_TEX_DIM_1D_ARRAY 4

1831

# define SQ_TEX_DIM_2D_ARRAY 5

1832

# define SQ_TEX_DIM_2D_MSAA 6

1833

# define SQ_TEX_DIM_2D_ARRAY_MSAA 7

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1834

#define SQ_TEX_RESOURCE_WORD1_0 0x30004

1835

# define TEX_ARRAY_MODE(x) ((x) << 28)

1836

#define SQ_TEX_RESOURCE_WORD2_0 0x30008

1837

#define SQ_TEX_RESOURCE_WORD3_0 0x3000C

1838

#define SQ_TEX_RESOURCE_WORD4_0 0x30010

Ilija Hadzic

2011-10-12 23:29:36 -0400

[diff] [blame]

1839

# define TEX_DST_SEL_X(x) ((x) << 16)

1840

# define TEX_DST_SEL_Y(x) ((x) << 19)

1841

# define TEX_DST_SEL_Z(x) ((x) << 22)

1842

# define TEX_DST_SEL_W(x) ((x) << 25)

# define SQ_SEL_X 0

# define SQ_SEL_Y 1

# define SQ_SEL_Z 2

# define SQ_SEL_W 3

# define SQ_SEL_0 4

# define SQ_SEL_1 5

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1849

#define SQ_TEX_RESOURCE_WORD5_0 0x30014

1850

#define SQ_TEX_RESOURCE_WORD6_0 0x30018

Alex Deucher

2011-11-28 14:49:28 -0500

[diff] [blame]

1851

# define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1852

#define SQ_TEX_RESOURCE_WORD7_0 0x3001c

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

1853

# define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6)

Alex Deucher

2011-11-28 14:49:28 -0500

[diff] [blame]

1854

# define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8)

1855

# define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10)

1856

# define TEX_NUM_BANKS(x) (((x) & 0x3) << 16)

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

1857

#define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000

1858

#define S_030000_DIM(x) (((x) & 0x7) << 0)

1859

#define G_030000_DIM(x) (((x) >> 0) & 0x7)

1860

#define C_030000_DIM 0xFFFFFFF8

1861

#define V_030000_SQ_TEX_DIM_1D 0x00000000

1862

#define V_030000_SQ_TEX_DIM_2D 0x00000001

1863

#define V_030000_SQ_TEX_DIM_3D 0x00000002

1864

#define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003

1865

#define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004

1866

#define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005

1867

#define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006

1868

#define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007

1869

#define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5)

1870

#define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1)

1871

#define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF

1872

#define S_030000_PITCH(x) (((x) & 0xFFF) << 6)

1873

#define G_030000_PITCH(x) (((x) >> 6) & 0xFFF)

1874

#define C_030000_PITCH 0xFFFC003F

1875

#define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18)

1876

#define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF)

1877

#define C_030000_TEX_WIDTH 0x0003FFFF

1878

#define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004

1879

#define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0)

1880

#define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF)

1881

#define C_030004_TEX_HEIGHT 0xFFFFC000

1882

#define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14)

1883

#define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF)

1884

#define C_030004_TEX_DEPTH 0xF8003FFF

1885

#define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28)

1886

#define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF)

1887

#define C_030004_ARRAY_MODE 0x0FFFFFFF

1888

#define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008

1889

#define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)

1890

#define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)

1891

#define C_030008_BASE_ADDRESS 0x00000000

1892

#define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C

1893

#define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)

1894

#define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)

1895

#define C_03000C_MIP_ADDRESS 0x00000000

1896

#define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010

1897

#define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)

1898

#define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)

1899

#define C_030010_FORMAT_COMP_X 0xFFFFFFFC

1900

#define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000

1901

#define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001

1902

#define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002

1903

#define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2)

1904

#define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3)

1905

#define C_030010_FORMAT_COMP_Y 0xFFFFFFF3

1906

#define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4)

1907

#define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3)

1908

#define C_030010_FORMAT_COMP_Z 0xFFFFFFCF

1909

#define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6)

1910

#define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3)

1911

#define C_030010_FORMAT_COMP_W 0xFFFFFF3F

1912

#define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8)

1913

#define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3)

1914

#define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF

1915

#define V_030010_SQ_NUM_FORMAT_NORM 0x00000000

1916

#define V_030010_SQ_NUM_FORMAT_INT 0x00000001

1917

#define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002

1918

#define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10)

1919

#define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1)

1920

#define C_030010_SRF_MODE_ALL 0xFFFFFBFF

1921

#define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000

1922

#define V_030010_SRF_MODE_NO_ZERO 0x00000001

1923

#define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11)

1924

#define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1)

1925

#define C_030010_FORCE_DEGAMMA 0xFFFFF7FF

1926

#define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12)

1927

#define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3)

1928

#define C_030010_ENDIAN_SWAP 0xFFFFCFFF

1929

#define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16)

1930

#define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7)

1931

#define C_030010_DST_SEL_X 0xFFF8FFFF

1932

#define V_030010_SQ_SEL_X 0x00000000

1933

#define V_030010_SQ_SEL_Y 0x00000001

1934

#define V_030010_SQ_SEL_Z 0x00000002

1935

#define V_030010_SQ_SEL_W 0x00000003

1936

#define V_030010_SQ_SEL_0 0x00000004

1937

#define V_030010_SQ_SEL_1 0x00000005

1938

#define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19)

1939

#define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7)

1940

#define C_030010_DST_SEL_Y 0xFFC7FFFF

1941

#define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22)

1942

#define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7)

1943

#define C_030010_DST_SEL_Z 0xFE3FFFFF

1944

#define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25)

1945

#define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7)

1946

#define C_030010_DST_SEL_W 0xF1FFFFFF

1947

#define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28)

1948

#define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF)

1949

#define C_030010_BASE_LEVEL 0x0FFFFFFF

1950

#define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014

1951

#define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0)

1952

#define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF)

1953

#define C_030014_LAST_LEVEL 0xFFFFFFF0

1954

#define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4)

1955

#define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF)

1956

#define C_030014_BASE_ARRAY 0xFFFE000F

1957

#define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17)

1958

#define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF)

1959

#define C_030014_LAST_ARRAY 0xC001FFFF

1960

#define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018

1961

#define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0)

1962

#define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7)

1963

#define C_030018_MAX_ANISO 0xFFFFFFF8

1964

#define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3)

1965

#define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7)

1966

#define C_030018_PERF_MODULATION 0xFFFFFFC7

1967

#define S_030018_INTERLACED(x) (((x) & 0x1) << 6)

1968

#define G_030018_INTERLACED(x) (((x) >> 6) & 0x1)

1969

#define C_030018_INTERLACED 0xFFFFFFBF

1970

#define S_030018_TILE_SPLIT(x) (((x) & 0x7) << 29)

1971

#define G_030018_TILE_SPLIT(x) (((x) >> 29) & 0x7)

1972

#define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C

1973

#define S_03001C_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6)

1974

#define G_03001C_MACRO_TILE_ASPECT(x) (((x) >> 6) & 0x3)

1975

#define S_03001C_BANK_WIDTH(x) (((x) & 0x3) << 8)

1976

#define G_03001C_BANK_WIDTH(x) (((x) >> 8) & 0x3)

1977

#define S_03001C_BANK_HEIGHT(x) (((x) & 0x3) << 10)

1978

#define G_03001C_BANK_HEIGHT(x) (((x) >> 10) & 0x3)

1979

#define S_03001C_NUM_BANKS(x) (((x) & 0x3) << 16)

1980

#define G_03001C_NUM_BANKS(x) (((x) >> 16) & 0x3)

1981

#define S_03001C_TYPE(x) (((x) & 0x3) << 30)

1982

#define G_03001C_TYPE(x) (((x) >> 30) & 0x3)

1983

#define C_03001C_TYPE 0x3FFFFFFF

1984

#define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000

1985

#define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001

1986

#define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002

1987

#define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003

1988

#define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0)

1989

#define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F)

1990

#define C_03001C_DATA_FORMAT 0xFFFFFFC0

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1991

Ilija Hadzic

2011-10-12 23:29:36 -0400

[diff] [blame]

1992

#define SQ_VTX_CONSTANT_WORD0_0 0x30000

1993

#define SQ_VTX_CONSTANT_WORD1_0 0x30004

1994

#define SQ_VTX_CONSTANT_WORD2_0 0x30008

1995

# define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0)

1996

# define SQ_VTXC_STRIDE(x) ((x) << 8)

1997

# define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30)

1998

# define SQ_ENDIAN_NONE 0

1999

# define SQ_ENDIAN_8IN16 1

2000

# define SQ_ENDIAN_8IN32 2

2001

#define SQ_VTX_CONSTANT_WORD3_0 0x3000C

2002

# define SQ_VTCX_SEL_X(x) ((x) << 3)

2003

# define SQ_VTCX_SEL_Y(x) ((x) << 6)

2004

# define SQ_VTCX_SEL_Z(x) ((x) << 9)

2005

# define SQ_VTCX_SEL_W(x) ((x) << 12)

2006

#define SQ_VTX_CONSTANT_WORD4_0 0x30010

2007

#define SQ_VTX_CONSTANT_WORD5_0 0x30014

2008

#define SQ_VTX_CONSTANT_WORD6_0 0x30018

2009

#define SQ_VTX_CONSTANT_WORD7_0 0x3001c

2010

Jerome Glisse

2012-01-05 22:11:05 -0500

[diff] [blame]

2011

#define TD_PS_BORDER_COLOR_INDEX 0xA400

2012

#define TD_PS_BORDER_COLOR_RED 0xA404

2013

#define TD_PS_BORDER_COLOR_GREEN 0xA408

2014

#define TD_PS_BORDER_COLOR_BLUE 0xA40C

2015

#define TD_PS_BORDER_COLOR_ALPHA 0xA410

2016

#define TD_VS_BORDER_COLOR_INDEX 0xA414

2017

#define TD_VS_BORDER_COLOR_RED 0xA418

2018

#define TD_VS_BORDER_COLOR_GREEN 0xA41C

2019

#define TD_VS_BORDER_COLOR_BLUE 0xA420

2020

#define TD_VS_BORDER_COLOR_ALPHA 0xA424

2021

#define TD_GS_BORDER_COLOR_INDEX 0xA428

2022

#define TD_GS_BORDER_COLOR_RED 0xA42C

2023

#define TD_GS_BORDER_COLOR_GREEN 0xA430

2024

#define TD_GS_BORDER_COLOR_BLUE 0xA434

2025

#define TD_GS_BORDER_COLOR_ALPHA 0xA438

2026

#define TD_HS_BORDER_COLOR_INDEX 0xA43C

2027

#define TD_HS_BORDER_COLOR_RED 0xA440

2028

#define TD_HS_BORDER_COLOR_GREEN 0xA444

2029

#define TD_HS_BORDER_COLOR_BLUE 0xA448

2030

#define TD_HS_BORDER_COLOR_ALPHA 0xA44C

2031

#define TD_LS_BORDER_COLOR_INDEX 0xA450

2032

#define TD_LS_BORDER_COLOR_RED 0xA454

2033

#define TD_LS_BORDER_COLOR_GREEN 0xA458

2034

#define TD_LS_BORDER_COLOR_BLUE 0xA45C

2035

#define TD_LS_BORDER_COLOR_ALPHA 0xA460

2036

#define TD_CS_BORDER_COLOR_INDEX 0xA464

2037

#define TD_CS_BORDER_COLOR_RED 0xA468

2038

#define TD_CS_BORDER_COLOR_GREEN 0xA46C

2039

#define TD_CS_BORDER_COLOR_BLUE 0xA470

2040

#define TD_CS_BORDER_COLOR_ALPHA 0xA474

2041

Alex Deucher

c175ca9

2011-03-02 20:07:37 -0500

[diff] [blame]

2042

/* cayman 3D regs */

Jerome Glisse

2012-01-05 22:11:05 -0500

[diff] [blame]

2043

#define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4

2044

#define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48

Alex Deucher

c175ca9

2011-03-02 20:07:37 -0500

[diff] [blame]

2045

#define CAYMAN_DB_EQAA 0x28804

2046

#define CAYMAN_DB_DEPTH_INFO 0x2803C

2047

#define CAYMAN_PA_SC_AA_CONFIG 0x28BE0

2048

#define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0

2049

#define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7

Alex Deucher

033b565

2011-06-08 15:26:45 -0400

[diff] [blame]

2050

#define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358

Alex Deucher

c175ca9

2011-03-02 20:07:37 -0500

[diff] [blame]

2051

/* cayman packet3 addition */

2052

#define CAYMAN_PACKET3_DEALLOC_STATE 0x14

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

2053

Jerome Glisse

eaaa698

2013-01-02 15:12:15 -0500

[diff] [blame]

2054

/* DMA regs common on r6xx/r7xx/evergreen/ni */

Jerome Glisse

64c56e8

2013-01-02 17:30:35 -0500

[diff] [blame]

2055

#define DMA_RB_CNTL 0xd000

2056

# define DMA_RB_ENABLE (1 << 0)

2057

# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */

2058

# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */

2059

# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)

2060

# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */

2061

# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */

Jerome Glisse

eaaa698

2013-01-02 15:12:15 -0500

[diff] [blame]

2062

#define DMA_STATUS_REG 0xd034

Alex Deucher

0ecebb9

2013-01-03 12:40:13 -0500

[diff] [blame]

2063

# define DMA_IDLE (1 << 0)

Jerome Glisse

eaaa698

2013-01-02 15:12:15 -0500

[diff] [blame]

2064

Alex Deucher